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553 lines
22 KiB
553 lines
22 KiB
/*++
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Copyright (c) 1993 Digital Equipment Corporation
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Module Name:
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gamma.h
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Abstract:
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This file defines the structures and definitions common to all
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sable-based platforms.
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Author:
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Joe Notarangelo 26-Oct-1993
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Steve Jenness 26-Oct-1993
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Environment:
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Kernel mode
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Revision History:
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28-Dec 1994 Steve Brooks
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t2.h and rattler.h extracted from this file.
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--*/
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#ifndef _GAMMAH_
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#define _GAMMAH_
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#include "sableref.h" // Sable reference IO structure
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#include "lynxref.h" // Lynx interrupt structure
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#include "xioref.h" // XIO interrupt structure
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#if !defined(_LANGUAGE_ASSEMBLY)
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#include "errframe.h"
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#endif
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//
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// Constants used by dense space I/O routines
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//
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#define GAMMA_PCI0_DENSE_BASE_PHYSICAL_SUPERPAGE 0xfffffc83c0000000
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#define GAMMA_PCI1_DENSE_BASE_PHYSICAL_SUPERPAGE 0xfffffc8180000000
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#define PCI0_DENSE_BASE_PHYSICAL_SUPERPAGE \
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(GAMMA_PCI0_DENSE_BASE_PHYSICAL_SUPERPAGE - SABLE_PCI0_DENSE_MEMORY_QVA)
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#define PCI1_DENSE_BASE_PHYSICAL_SUPERPAGE \
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(GAMMA_PCI1_DENSE_BASE_PHYSICAL_SUPERPAGE - SABLE_PCI1_DENSE_MEMORY_QVA)
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#if !defined(_LANGUAGE_ASSEMBLY)
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#include "rattler.h" // Rattler chipset definitions
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#include "t2.h" // T2 chipset definitions
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#include "icic.h" // ICIC definitions
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#define GAMMA_QVA_PHYSICAL_BASE ((ULONGLONG)0x8000000000)
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//
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// QVA
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// HAL_MAKE_QVA(
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// ULONGLONG PhysicalAddress
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// )
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//
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// Routine Description:
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//
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// This macro returns the Qva for a physical address in system space.
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//
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// Arguments:
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//
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// PhysicalAddress - Supplies a 64-bit physical address.
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//
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// Return Value:
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//
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// The Qva associated with the physical address.
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//
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#define HAL_MAKE_QVA(PA) \
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( (PVOID)( QVA_ENABLE | \
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(ULONG)( ((PA)-GAMMA_QVA_PHYSICAL_BASE) >> IO_BIT_SHIFT) ) )
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//
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// Define physical address spaces for GAMMA.
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//
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// PCI0 - 32bit PCI bus
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// PCI1 - 64bit PCI bus
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//
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#define GAMMA_PCI1_DENSE_MEMORY_PHYSICAL ((ULONGLONG)0x8180000000)
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#define GAMMA_PCI1_SPARSE_IO_PHYSICAL ((ULONGLONG)0x81C0000000)
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#define GAMMA_PCI0_SPARSE_MEMORY_PHYSICAL ((ULONGLONG)0x8200000000)
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#define GAMMA_PCI1_SPARSE_MEMORY_PHYSICAL ((ULONGLONG)0x8300000000)
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#define GAMMA_PCI1_SPARSE_ISA_LEGACY_MEMORY_PHYSICAL ((ULONGLONG)0x8302000000)
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#define GAMMA_PCI1_SPARSE_ISA_LEGACY_IO_PHYSICAL ((ULONGLONG)0x8200000000)
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#define GAMMA_CBUS_CSRS_PHYSICAL ((ULONGLONG)0x8380000000)
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#define GAMMA_CPU0_CSRS_PHYSICAL ((ULONGLONG)0x8380000000)
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#define GAMMA_CPU1_CSRS_PHYSICAL ((ULONGLONG)0x8381000000)
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#define GAMMA_CPU2_CSRS_PHYSICAL ((ULONGLONG)0x8382000000)
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#define GAMMA_CPU3_CSRS_PHYSICAL ((ULONGLONG)0x8383000000)
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#define GAMMA_CPU0_SICR_PHYSICAL ((ULONGLONG)0x8380000320)
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#define GAMMA_CPU1_SICR_PHYSICAL ((ULONGLONG)0x8381000320)
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#define GAMMA_CPU2_SICR_PHYSICAL ((ULONGLONG)0x8382000320)
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#define GAMMA_CPU3_SICR_PHYSICAL ((ULONGLONG)0x8383000320)
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#define GAMMA_MEM0_CSRS_PHYSICAL ((ULONGLONG)0x8388000000)
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#define GAMMA_MEM1_CSRS_PHYSICAL ((ULONGLONG)0x8389000000)
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#define GAMMA_MEM2_CSRS_PHYSICAL ((ULONGLONG)0x838A000000)
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#define GAMMA_MEM3_CSRS_PHYSICAL ((ULONGLONG)0x838B000000)
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#define GAMMA_T2_CSRS_PHYSICAL ((ULONGLONG)0x838E000000)
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#define GAMMA_T4_CSRS_PHYSICAL ((ULONGLONG)0x838F000000)
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#define T2_CSRS_QVA (HAL_MAKE_QVA(GAMMA_T2_CSRS_PHYSICAL))
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#define T4_CSRS_QVA (HAL_MAKE_QVA(GAMMA_T4_CSRS_PHYSICAL))
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#define GAMMA_PCI0_CONFIGURATION_PHYSICAL ((ULONGLONG)0x8390000000)
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#define GAMMA_PCI1_CONFIGURATION_PHYSICAL ((ULONGLONG)0x8398000000)
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#define GAMMA_PCI0_SPARSE_IO_PHYSICAL ((ULONGLONG)0x83A0000000)
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#define GAMMA_PCI0_DENSE_MEMORY_PHYSICAL ((ULONGLONG)0x83C0000000)
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//
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// Define the limits of User mode Sparse and dense space:
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// A special hack is applied to these values for Gamma, since these addresses
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// are 40 bits in length, and are therefore beyond the range of QVAs. Bit 36
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// is set in these constants, which will get shifted to bit 31 when a QVA is
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// formed. When the physical address is then generated by the access macros,
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// the high order bits will get set, forcing bit 39 to be set, causing a
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// noncached access to occur
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//
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#define GAMMA_USER_PCI1_DENSE_MEMORY_PHYSICAL ((ULONGLONG)0x8980000000)
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#define GAMMA_USER_PCI1_SPARSE_IO_PHYSICAL ((ULONGLONG)0x89c0000000)
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#define GAMMA_USER_PCI0_SPARSE_MEMORY_PHYSICAL ((ULONGLONG)0x8A00000000)
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#define GAMMA_USER_PCI0_SPARSE_MEMORY_END_PHYSICAL ((ULONGLONG)0x8b00000000)
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#define GAMMA_USER_PCI1_SPARSE_MEMORY_PHYSICAL ((ULONGLONG)0x8b00000000)
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#define GAMMA_USER_PCI1_SPARSE_MEMORY_END_PHYSICAL ((ULONGLONG)0x8b80000000)
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#define GAMMA_USER_PCI0_SPARSE_IO_PHYSICAL ((ULONGLONG)0x8ba0000000)
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#define GAMMA_USER_PCI0_SPARSE_IO_END_PHYSICAL ((ULONGLONG)0x8bc0000000)
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#define GAMMA_USER_PCI0_DENSE_MEMORY_PHYSICAL ((ULONGLONG)0x8bc0000000)
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#define GAMMA_EDGE_LEVEL_CSRS_PHYSICAL ((ULONGLONG)0x83A00004C0)
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#define GAMMA_INTERRUPT_CSRS_PHYSICAL ((ULONGLONG)0x83A000A640)
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#define XIO_INTERRUPT_CSRS_PHYSICAL ((ULONGLONG)0x81C000A640)
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//
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// For compatability, define the SABLE_* constants to refer to the GAMMA_*
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// constants. This allows gamma to share sources from the sable tree.
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//
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#define SABLE_PCI1_DENSE_MEMORY_PHYSICAL GAMMA_PCI1_DENSE_MEMORY_PHYSICAL
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#define SABLE_PCI1_SPARSE_IO_PHYSICAL GAMMA_PCI1_SPARSE_IO_PHYSICAL
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#define SABLE_PCI0_SPARSE_MEMORY_PHYSICAL GAMMA_PCI0_SPARSE_MEMORY_PHYSICAL
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#define SABLE_PCI1_SPARSE_MEMORY_PHYSICAL GAMMA_PCI1_SPARSE_MEMORY_PHYSICAL
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#define SABLE_USER_PCI1_DENSE_MEMORY_PHYSICAL GAMMA_USER_PCI1_DENSE_MEMORY_PHYSICAL
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#define SABLE_USER_PCI1_SPARSE_IO_PHYSICAL GAMMA_USER_PCI1_SPARSE_IO_PHYSICAL
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#define SABLE_USER_PCI0_SPARSE_MEMORY_PHYSICAL GAMMA_USER_PCI0_SPARSE_MEMORY_PHYSICAL
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#define SABLE_USER_PCI0_SPARSE_MEMORY_END_PHYSICAL GAMMA_USER_PCI0_SPARSE_MEMORY_END_PHYSICAL
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#define SABLE_USER_PCI1_SPARSE_MEMORY_PHYSICAL GAMMA_USER_PCI1_SPARSE_MEMORY_PHYSICAL
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#define SABLE_USER_PCI1_SPARSE_MEMORY_END_PHYSICAL GAMMA_USER_PCI1_SPARSE_MEMORY_END_PHYSICAL
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#define SABLE_USER_PCI0_SPARSE_IO_PHYSICAL GAMMA_USER_PCI0_SPARSE_IO_PHYSICAL
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#define SABLE_USER_PCI0_SPARSE_IO_END_PHYSICAL GAMMA_USER_PCI0_SPARSE_IO_END_PHYSICAL
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#define SABLE_USER_PCI0_DENSE_MEMORY_PHYSICAL GAMMA_USER_PCI0_DENSE_MEMORY_PHYSICAL
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#define SABLE_CBUS_CSRS_PHYSICAL GAMMA_CBUS_CSRS_PHYSICAL
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#define SABLE_CPU0_CSRS_PHYSICAL GAMMA_CPU0_CSRS_PHYSICAL
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#define SABLE_CPU1_CSRS_PHYSICAL GAMMA_CPU1_CSRS_PHYSICAL
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#define SABLE_CPU2_CSRS_PHYSICAL GAMMA_CPU2_CSRS_PHYSICAL
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#define SABLE_CPU3_CSRS_PHYSICAL GAMMA_CPU3_CSRS_PHYSICAL
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#define SABLE_CPU0_IPIR_PHYSICAL GAMMA_CPU0_SICR_PHYSICAL
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#define SABLE_CPU1_IPIR_PHYSICAL GAMMA_CPU1_SICR_PHYSICAL
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#define SABLE_CPU2_IPIR_PHYSICAL GAMMA_CPU2_SICR_PHYSICAL
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#define SABLE_CPU3_IPIR_PHYSICAL GAMMA_CPU3_SICR_PHYSICAL
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#define SABLE_PCI0_CONFIGURATION_PHYSICAL GAMMA_PCI0_CONFIGURATION_PHYSICAL
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#define SABLE_PCI1_CONFIGURATION_PHYSICAL GAMMA_PCI1_CONFIGURATION_PHYSICAL
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#define SABLE_PCI0_SPARSE_IO_PHYSICAL GAMMA_PCI0_SPARSE_IO_PHYSICAL
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#define SABLE_PCI0_DENSE_MEMORY_PHYSICAL GAMMA_PCI0_DENSE_MEMORY_PHYSICAL
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//
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// Define Interrupt Controller CSRs.
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//
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#define SABLE_EDGE_LEVEL_CSRS_QVA (HAL_MAKE_QVA(GAMMA_EDGE_LEVEL_CSRS_PHYSICAL))
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#define SABLE_INTERRUPT_CSRS_QVA (HAL_MAKE_QVA(GAMMA_INTERRUPT_CSRS_PHYSICAL))
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//
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// Define XIO interrupt controller CSRs.
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//
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#define XIO_INTERRUPT_CSRS_QVA (HAL_MAKE_QVA(XIO_INTERRUPT_CSRS_PHYSICAL))
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#define SABLE_PCI_CONFIG_BASE_QVA (HAL_MAKE_QVA(GAMMA_PCI0_CONFIGURATION_PHYSICAL))
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//
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// Gamma uses the Rattler chipset for the CBUS bridge. Define the Sable
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// CPU CSRS to be Rattler CPU Csrs.
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//
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#define SABLE_CPU_CSRS RATTLER_CPU_CSRS
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#define PSABLE_CPU_CSRS PRATTLER_CPU_CSRS
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//
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// Define CPU CSRs and masks.
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//
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#define SABLE_CPU0_CSRS_QVA (HAL_MAKE_QVA(GAMMA_CPU0_CSRS_PHYSICAL))
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#define SABLE_CPU1_CSRS_QVA (HAL_MAKE_QVA(GAMMA_CPU1_CSRS_PHYSICAL))
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#define SABLE_CPU2_CSRS_QVA (HAL_MAKE_QVA(GAMMA_CPU2_CSRS_PHYSICAL))
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#define SABLE_CPU3_CSRS_QVA (HAL_MAKE_QVA(GAMMA_CPU3_CSRS_PHYSICAL))
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#define GAMMA_MEM0_CSRS_QVA (HAL_MAKE_QVA(GAMMA_MEM0_CSRS_PHYSICAL))
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#define GAMMA_MEM1_CSRS_QVA (HAL_MAKE_QVA(GAMMA_MEM1_CSRS_PHYSICAL))
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#define GAMMA_MEM2_CSRS_QVA (HAL_MAKE_QVA(GAMMA_MEM2_CSRS_PHYSICAL))
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#define GAMMA_MEM3_CSRS_QVA (HAL_MAKE_QVA(GAMMA_MEM3_CSRS_PHYSICAL))
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#define GAMMA_PRIMARY_PROCESSOR ((ULONG)0x0)
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#define GAMMA_SECONDARY_PROCESSOR ((ULONG)0x1)
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#define GAMMA_MAXIMUM_PROCESSOR ((ULONG)0x3)
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#define HAL_PRIMARY_PROCESSOR (GAMMA_PRIMARY_PROCESSOR)
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#define HAL_MAXIMUM_PROCESSOR (GAMMA_MAXIMUM_PROCESSOR)
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//
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// Define the default processor frequency to be used before the actual
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// frequency can be determined.
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//
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#define DEFAULT_PROCESSOR_FREQUENCY_MHZ (275)
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enum {
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NoError,
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UncorrectableError,
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CorrectableError
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} ErrorType;
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//
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// Define the memory module CSRs (from chapter 10 of the GAMMA CPU spec)
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//
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//
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// Error Summary register
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//
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typedef struct _GAMMA_ESREG_CSR1 {
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union {
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ULONG EVBCorrecectableError0: 3; // 0-2
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ULONG Resrved1: 1; // 3
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ULONG EVBFatalError0: 4; // 4-7
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ULONG DTError0: 2; // 8-9
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ULONG DTSummary0: 1; // 10
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ULONG Reserved2: 1; // 11
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ULONG IBParError0: 1; // 12
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ULONG IBErrorInfo0: 2; // 13-14
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ULONG IBSummary0: 1; // 15
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ULONG CBError0: 8; // 16-23
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ULONG CBSummary0: 1; // 24
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ULONG CBCommand0: 1; // 25
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ULONG Reserved3: 2; // 26-27
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ULONG EVNoResponse0: 1; // 28
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ULONG Reserved4: 3; // 29-31
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ULONG EVBCorrecectableError1: 3; // 32-34
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ULONG Resrved5: 1; // 35
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ULONG EVBFatalError1: 4; // 36-39
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ULONG DTError1: 2; // 40-41
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ULONG DTSummary1: 1; // 42
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ULONG Reserved6: 1; // 43
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ULONG IBParError1: 1; // 44
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ULONG IBErrorInfo1: 2; // 45-46
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ULONG IBSummary1: 1; // 47
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ULONG CBError1: 4; // 48-51
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ULONG Reserved7: 4; // 52-55
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ULONG CBSummary1: 1; // 56
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ULONG CBCommand1: 1; // 57
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ULONG Reserved8: 2; // 58-59
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ULONG EVNoResponse1: 1; // 60
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ULONG Reserved9: 3; // 61-63
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};
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ULONGLONG all;
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} GAMMA_ESREG_CSR1, *PGAMMA_ESREG_CSR1;
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typedef struct _GAMMA_EVBCR_CSR2 {
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union {
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ULONG EnableAddressCommandBusParityCheck0: 1; // 0
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ULONG Reserved1: 3; // 1-3
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ULONG EnableCorrectionErrorInterrupt0: 1; // 4
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ULONG EnableECCCorrection0: 1; // 5
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ULONG EnableRattlerECCCheck0: 1; // 6
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ULONG Reserved2: 20; // 7-26
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ULONG ForceFilledShared: 1; // 27
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ULONG RmmStxcFillShared: 1; // 28
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ULONG Reserved3: 3; // 29-31
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ULONG EnableAddressCommandBusParityCheck1: 1; // 32
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ULONG Reserved4: 4; // 33-35
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ULONG EnableCorrectionErrorInterrupt1: 1; // 36
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ULONG EnableECCCorrection1: 1; // 37
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ULONG EnableRattlerECCCheck1: 1; // 38
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ULONG DisableEV5ECCChecking1: 1; // 39
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ULONG Reserved5: 24; // 40-63
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};
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ULONGLONG all;
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} GAMMA_EVBCR_CSR2, *PGAMMA_EVBCR_CSR2;
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typedef struct _GAMMA_EVBVEAR_CSR3 {
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union {
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ULONG EVBVictimErrorAddress0: 30; // 0-29
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ULONG Reserved1: 2; // 30-31
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ULONG EVBVictimErrorAddress1: 30; // 32-61
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ULONG Reserved2: 2; // 62-63
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};
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} GAMMA_EVBVEAR_CSR3, *PGAMMA_EVBVEAR_CSR3;
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typedef struct _GAMMA_EVBCER_CSR4 {
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union {
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ULONG CorrectableError0: 2; // 0-1
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ULONG ReadDirty0: 1; // 2
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ULONG MissedCorrectable0: 1; // 3
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ULONG Reserved1: 4; // 4-7
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ULONG ECCSyndrome0: 8; // 8-15
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ULONG ECCSyndrome2: 8; // 16-23
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ULONG Reserved2: 8; // 24-31
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ULONG CorrectableError1: 2; // 32-33
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ULONG ReadDirty1: 1; // 34
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ULONG MissedCorrectable1: 1; // 35
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ULONG Reserved3: 4; // 36-39
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ULONG ECCSyndrome1: 8; // 40-47
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ULONG ECCSyndrome3: 8; // 48-55
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ULONG Reserved4: 8; // 56-63
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};
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ULONGLONG all;
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} GAMMA_EVBCER_CSR4, *PGAMMA_EVBCER_CSR4;
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typedef struct _GAMMA_EVBCEAR_CSR5 {
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union {
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ULONG EVBCorrectableErrorAddress0: 32; // 0-31
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ULONG EVBCorrectableErrorAddress1: 32; // 32-63
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};
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ULONGLONG all;
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} GAMMA_EVBCEAR_CSR5, *PGAMMA_EVBCEAR_CSR5;
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typedef struct _GAMMA_EVBUER_CSR6 {
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union {
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ULONG UncorrectableError0: 2; // 0-1
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ULONG ReadDirty0: 1; // 2
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ULONG Reserved1: 1; // 3
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ULONG ParityErrorOnAddressCommand0: 1; // 4
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ULONG ParityErrorOnVictim0: 1; // 5
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ULONG Reserved2: 2; // 6-7
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ULONG ECCSyndrome0: 8; // 8-15
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ULONG ECCSyndrome2: 8; // 16-23
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ULONG Reserved3: 4; // 24-27
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ULONG EVBCommand0: 4; // 28-31
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ULONG UncorrectableError1: 2; // 32-33
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ULONG ReadDirty1: 1; // 34
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ULONG Reserved4: 1; // 35
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ULONG ParityErrorOnAddressCommand1: 1; // 36
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ULONG ParityErrorOnVictim1: 1; // 37
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ULONG Reserved5: 2; // 38-39
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ULONG ECCSyndrome1: 8; // 40-47
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ULONG ECCSyndrome3: 8; // 48-55
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ULONG Reserved6: 4; // 56-59
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ULONG EVBCommand1: 4; // 60-63
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};
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ULONGLONG all;
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} GAMMA_EVBUER_CSR6, *PGAMMA_EVBUER_CSR6;
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typedef struct _GAMMA_EVBUEAR_CSR7 {
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union {
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ULONG EVBUncorrectableErrorAddress0: 32; // 0-31
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ULONG EVBUncorrectableErrorAddress1: 32; // 32-63
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};
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ULONGLONG all;
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} GAMMA_EVBEUAR_CSR7, *PGAMMA_EVBUEAR_CSR7;
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typedef struct _GAMMA_CBER_CSR18 {
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union {
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ULONG UncorrectableReadError0: 1; // 0
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ULONG Reserved1: 3; // 1-3
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ULONG CAParity0ErrorL: 1; // 4
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ULONG CAParity0ErrorH: 1; // 5
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ULONG Reserved2: 2; // 6-7
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ULONG ParityErrorWriteDataLW0: 1; // 8
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ULONG ParityErrorWriteDataLW1: 1; // 9
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ULONG ParityErrorWriteDataLW4: 1; // 10
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ULONG ParityErrorWriteDataLW5: 1; // 11
|
|
ULONG Reserved3: 4; // 12-15
|
|
ULONG ParityErrorReadDataLW0: 1; // 16
|
|
ULONG ParityErrorReadDataLW1: 1; // 17
|
|
ULONG ParityErrorReadDataLW4: 1; // 18
|
|
ULONG ParityErrorReadDataLW5: 1; // 19
|
|
ULONG UnexpectedSharedResponse: 1; // 20
|
|
ULONG Reserved4: 3; // 21-23
|
|
ULONG CANotAcked: 1; // 24
|
|
ULONG Reserved5: 3; // 25-27
|
|
ULONG Data0NotAcked: 1; // 28
|
|
ULONG Data1NotAcked: 1; // 29
|
|
ULONG Reserved6: 2; // 30-31
|
|
|
|
ULONG UncorrectableReadError1: 1; // 32
|
|
ULONG Reserved7: 3; // 33-35
|
|
ULONG CAParity1ErrorL: 1; // 36
|
|
ULONG CAParity1ErrorH: 1; // 37
|
|
ULONG Reserved8: 2; // 38-39
|
|
ULONG ParityErrorWriteDataLW2: 1; // 40
|
|
ULONG ParityErrorWriteDataLW3: 1; // 41
|
|
ULONG ParityErrorWriteDataLW6: 1; // 42
|
|
ULONG ParityErrorWriteDataLW7: 1; // 43
|
|
ULONG Reserved9: 4; // 44-47
|
|
ULONG ParityErrorReadDataLW2: 1; // 48
|
|
ULONG ParityErrorReadDataLW3: 1; // 49
|
|
ULONG ParityErrorReadDataLW6: 1; // 50
|
|
ULONG ParityErrorReadDataLW7: 1; // 51
|
|
ULONG Reserved10: 12; // 52-63
|
|
};
|
|
ULONGLONG all;
|
|
|
|
} GAMMA_CBER_CSR18, *PGAMMA_CBER_CSR18;
|
|
|
|
typedef struct _GAMMA_CBEALR_CSR19 {
|
|
union {
|
|
ULONG CBusErrorLowAddress0: 32; // 0-31
|
|
ULONG CBusErrorLowAddress1: 32; // 32-63
|
|
};
|
|
ULONGLONG all;
|
|
|
|
} GAMMA_CBEALR_CSR19, *PGAMMA_CBEALR_CSR19;
|
|
|
|
typedef struct _GAMMA_CBEAHR_CSR20 {
|
|
union {
|
|
ULONG CBusErrorHighAddress0: 32; // 0-31
|
|
ULONG CBusErrorHighAddress1: 32; // 32-63
|
|
};
|
|
ULONGLONG all;
|
|
|
|
} GAMMA_CBEAHR_CSR20, *PGAMMA_CBEAHR_CSR20;
|
|
|
|
|
|
typedef struct _SGL_MEM_CSR0 {
|
|
union {
|
|
ULONG ErrorSummary1: 1; // 0
|
|
ULONG SyncError1: 1; // 1
|
|
ULONG CAParityError1: 1; // 2
|
|
ULONG CAMissedParityError1: 1; // 3
|
|
ULONG WriteParityError1: 1; // 4
|
|
ULONG MissedWriteParityError1: 1; // 5
|
|
ULONG Reserved1: 2; // 6-7
|
|
|
|
ULONG CAParityErrorLW0: 1; // 8
|
|
ULONG CAParityErrorLW2: 1; // 9
|
|
ULONG ParityErrorLW0: 1; // 10
|
|
ULONG ParityErrorLW2: 1; // 11
|
|
ULONG ParityErrorLW4: 1; // 12
|
|
ULONG ParityErrorLW6: 1; // 13
|
|
ULONG Reserved2: 2; // 14-15
|
|
|
|
ULONG EDCUncorrectable1: 1; // 16
|
|
ULONG EDCMissedUncorrectable1: 1; // 17
|
|
ULONG EDCCorrectable1: 1; // 18
|
|
ULONG EDCMissdedCorrectable1: 1; // 19
|
|
ULONG Reserved3: 12; // 20-31
|
|
|
|
ULONG ErrorSummary2: 1; // 32
|
|
ULONG SyncError2: 1; // 33
|
|
ULONG CAParityError2: 1; // 34
|
|
ULONG CAMissedParityError2: 1; // 35
|
|
ULONG WriteParityError2: 1; // 36
|
|
ULONG MissedWriteParityError2: 1; // 37
|
|
ULONG Reserved4: 2; // 38-39
|
|
|
|
ULONG CAParityErrorLW1: 1; // 40
|
|
ULONG CAParityErrorLW3: 1; // 41
|
|
ULONG ParityErrorLW1: 1; // 42
|
|
ULONG ParityErrorLW3: 1; // 43
|
|
ULONG ParityErrorLW5: 1; // 44
|
|
ULONG ParityErrorLW7: 1; // 45
|
|
ULONG Reserved5: 2; // 46-47
|
|
|
|
ULONG EDCUncorrectable2: 1; // 48
|
|
ULONG EDCMissedUncorrectable2: 1; // 49
|
|
ULONG EDCCorrectable2: 1; // 50
|
|
ULONG EDCMissdedCorrectable2: 1; // 51
|
|
ULONG Reserved6: 12; // 52-63
|
|
};
|
|
ULONGLONG all;
|
|
|
|
} SGL_MEM_CSR0, *PSGL_MEM_CSR0;
|
|
|
|
//
|
|
// Define the per-processor data structures allocated in the PCR
|
|
// for each Gamma processor.
|
|
//
|
|
// NOTE: If the IpirSva field is moved, the change must be reflected in
|
|
// the routine HalpGammaIpiInterrupt
|
|
//
|
|
|
|
typedef struct _GAMMA_PCR{
|
|
ULONGLONG HalpCycleCount; // 64-bit per-processor cycle count
|
|
ULONGLONG IpirSva; // Superpage Va of per-processor IPIR CSR
|
|
PVOID CpuCsrsQva; // Qva of per-cpu csrs
|
|
EV5ProfileCount ProfileCount; // Profile counter state
|
|
} GAMMA_PCR, *PGAMMA_PCR;
|
|
|
|
#define HAL_PCR ( (PGAMMA_PCR)(&(PCR->HalReserved)) )
|
|
|
|
|
|
//
|
|
// Define Miscellaneous Gamma routines.
|
|
//
|
|
|
|
VOID
|
|
WRITE_CPU_REGISTER(
|
|
PVOID,
|
|
ULONGLONG
|
|
);
|
|
|
|
ULONGLONG
|
|
READ_CPU_REGISTER(
|
|
PVOID
|
|
);
|
|
|
|
ULONGLONG
|
|
READ_MEM_REGISTER(
|
|
PVOID
|
|
);
|
|
|
|
BOOLEAN
|
|
HalpGammaDispatch(
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
HalpGammaIpiInterrupt(
|
|
VOID
|
|
);
|
|
|
|
#endif //!_LANGUAGE_ASSEMBLY
|
|
|
|
#endif //_GAMMAH_
|