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1046 lines
35 KiB
1046 lines
35 KiB
/*++
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Copyright (c) 1993 Digital Equipment Corporation
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Module Name:
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gammaio.s
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Abstract:
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This contains assembler code routines for the Gamma system.
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The module contains the functions to turn quasi virtual
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addresses into an Alpha superpage virtual address
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and then read or write based on the request.
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(We are using EV4 64-bit superpage mode.)
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Author:
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Joe Notarangelo 25-Oct-1993
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Environment:
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Executes in kernel mode.
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Revision History:
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--*/
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#include "gamma.h"
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#include "halalpha.h"
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// Superpage VA
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//
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// This value is used to define the base physical address from which
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// QVA's are defined.
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//
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// This value is specified as a negative number so that the value will
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// be sign extended when loaded into a register. If defined positive, the
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// assembler will prevent sign extension.
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//
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#define GAMMA_IO_SVA -0x3800 // negative of 0xc800
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.set noreorder
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LEAF_ENTRY(WRITE_T2_REGISTER)
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ALTERNATE_ENTRY(WRITE_CPU_REGISTER)
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ALTERNATE_ENTRY(WRITE_MEM_REGISTER)
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/*++
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Routine Description:
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Writes a T2 or a CPU CSR.
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Arguments:
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a0 QVA of register to be written.
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a1 Longword to be written.
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Return Value:
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None.
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--*/
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and a0, QVA_SELECTORS, t1 // get qva selector bits
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xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set in selectors
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bne t1, 2f // if ne, iff failed
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zap a0, 0xf0, a0 // clear <63:32>
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bic a0, QVA_ENABLE, a0 // clear QVA fields so shift is correct
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sll a0, IO_BIT_SHIFT, t0
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ldiq t4, GAMMA_IO_SVA // 0xffff ffff ffff c800
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sll t4, 28, t4 // 0xffff fc80 0000 0000
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or t0, t4, t0 // superpage mode
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stq a1, (t0) // write the quadword
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mb // order the write
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mb
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ret zero, (ra)
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2:
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BREAK_DEBUG_STOP // Bad Qva
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ret zero, (ra)
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.end WRITE_T2_REGISTER
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LEAF_ENTRY(READ_T2_REGISTER)
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ALTERNATE_ENTRY(READ_CPU_REGISTER)
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ALTERNATE_ENTRY(READ_MEM_REGISTER)
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/*++
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Routine Description:
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Read a T2 or CPU CSR.
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Arguments:
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a0 QVA of register to be read.
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Return Value:
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The quadword read from the register.
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--*/
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and a0, QVA_SELECTORS, t1 // get qva selector bits
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xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set in selectors
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bne t1, 2f // if ne, iff failed
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zap a0, 0xf0, a0 // clear <63:32>
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bic a0, QVA_ENABLE, a0 // clear QVA fields so shift is correct
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sll a0, IO_BIT_SHIFT, t0
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ldiq t4, GAMMA_IO_SVA // 0xffff ffff ffff c800
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sll t4, 28, t4 // 0xffff fc80 0000 0000
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or t0, t4, t0 // superpage mode
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//
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// Save Address of Config space access for the machine check handler:
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// (This isn't a config space access, but the exception handling is identical)
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//
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lda t1, HalpConfigIoAccess
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lda t4, CPUCsrRead // machine check return address
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stl t4, 0(t1)
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mb // commit the store before reading
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DISABLE_INTERRUPTS // don't allow ints before Mcheck
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CPUCsrRead:
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ldq v0, (t0) // read the register
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mb // synchronize
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mb //
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stl zero, 0(t1) // Restore HalpConfigIoAccess
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ENABLE_INTERRUPTS // Interrupts OK after Mcheck
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ret zero, (ra)
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2:
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BREAK_DEBUG_STOP // Bad Qva
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ret zero, (ra)
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.end READ_T2_REGISTER
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//
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// Values and structures used to access configuration space.
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//
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//
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// Define the QVA for the Configuration Cycle Type register within the
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// IOC.
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//
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// PASS 1 SABLE SUPPORT
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#define T2_HAE0_2_QVA (0xbc700008)
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#define T2_HAE02_CYCLETYPE_SHIFT 30
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#define T2_HAE02_CYCLETYPE_MASK 0xc0000000
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// PASS 2 SABLE SUPPORT
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#define T2_HAE03_CYCLETYPE_SHIFT 30
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#define T2_HAE03_CYCLETYPE_MASK 0xc0000000
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#define T2_HAE0_3_QVA (0xbc700012)
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#define T2_CONFIG_ADDR_QVA (0xbc800000)
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//
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// T4 Support:
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//
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#define T4_HAE0_3_QVA (0xbc780012)
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#define T4_CONFIG_ADDR_QVA (0xbcc00000)
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//
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// Define the configuration routines stack frame.
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//
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.struct 0
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CfgRa: .space 8 // return address
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CfgA0: .space 8 // saved ConfigurationAddress
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CfgA1: .space 8 // saved ConfigurationData
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CfgA2: .space 8 // padding for 16 byte alignment
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CfgFrameLength:
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//++
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//
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// ULONG
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// READ_CONFIG_UCHAR(
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// ULONG ConfigurationAddress,
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// ULONG ConfigurationCycleType
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// )
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//
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// Routine Description:
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//
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// Read an unsigned byte from PCI configuration space.
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//
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// Arguments:
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//
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// ConfigurationAddress(a0) - Supplies the QVA of configuration to be read.
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//
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// ConfigurationCycleType(a1) - Supplies the type of the configuration cycle.
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//
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// Return Value:
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//
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// (v0) Returns the value of configuration space at the specified location.
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//
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// N.B. - This routine follows a protocol for reading from PCI configuration
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// space that allows the HAL or firmware to fixup and continue
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// execution if no device exists at the configuration target address.
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// The protocol requires 2 rules:
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// (1) The configuration space load must use a destination register
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// of v0
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// (2) The instruction immediately following the configuration space
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// load must use v0 as an operand (it must consume the value
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// returned by the load)
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//
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//--
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NESTED_ENTRY( READ_CONFIG_UCHAR, CfgFrameLength, zero )
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lda sp, -CfgFrameLength(sp) // allocate stack frame
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stq ra, CfgRa(sp) // save return address
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PROLOGUE_END // end prologue
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//
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// Depending on whether it's a pass 1 or pass 2 T2 the configuration
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// cycle type is in different registers
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//
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ldl t0, T2VersionNumber // load version number
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beq t0, 1f // if 0 then pass 1 T2
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//
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// PASS 2 T2 or XIO access:
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// Cycle type are the only bits in HAE0_3 register
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//
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stq a0, CfgA0(sp) // save config space address
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//
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// Determine whether access is to T2 or T4 space:
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// Isolate the Base address bits: bit 22 indicates T4 space access
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//
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ldil t0, T4_CONFIG_ADDR_QVA // check for QVA in T4 space
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and t0, a0, t1 // isolate QVA base address
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ldil a0, T2_HAE0_3_QVA // address of T2 space HAE0_3
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xor t0, t1, t0 // T4 address space ? (bit 22 set)
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ldil t1, T4_HAE0_3_QVA // load address of T4 HAE register
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cmoveq t0, t1, a0 // if in T4 space, update a0
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sll a1, T2_HAE03_CYCLETYPE_SHIFT, a1 // put cycle type in position
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bsr ra, WRITE_T2_REGISTER // write updated HAE
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br zero, 2f // go do actual read
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//
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// PASS 1 T2
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// Merge the configuration cycle type into the HAE0_2 register within
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// the T2.
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//
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1:
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stq a0, CfgA0(sp) // save config space address
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stq a1, CfgA1(sp) // save config cycle type
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ldil a0, T2_HAE0_2_QVA // address of HAE0_2
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bsr ra, READ_T2_REGISTER // read current value
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ldq a1, CfgA1(sp) // restore config cycle type
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ldil t0, T2_HAE02_CYCLETYPE_MASK // get cycle type field mask
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bic v0, t0, t0 // clear config cycle type field
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sll a1, T2_HAE02_CYCLETYPE_SHIFT, a1// put cycle type in position
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bis a1, t0, a1 // merge config cycle type
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ldil a0, T2_HAE0_2_QVA // address of HAE0_2
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bsr ra, WRITE_T2_REGISTER // write updated HAE
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//
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// Perform the read from configuration space after restoring the
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// configuration space address.
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//
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2:
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ldq a0, CfgA0(sp) // restore config space address
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and a0, QVA_SELECTORS, t1 // get qva selector bits
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and a0, 0x3, t3 // capture byte lane
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xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set
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bne t1, 3f // if ne, iff failed
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zap a0, 0xf0, a0 // clear <63:32>
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bic a0, QVA_ENABLE, a0 // clear QVA fields
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sll a0, IO_BIT_SHIFT, t0 //
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ldiq t4, GAMMA_IO_SVA // 0xffff ffff ffff c800
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sll t4, 28, t4 // 0xffff fc80 0000 0000
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bis t0, t4, t0 // superpage mode
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bis t0, IO_BYTE_LEN, t0 // or in the byte enables
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//
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// Save Address of Config space address for the machine check handler:
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//
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lda t1, HalpConfigIoAccess
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lda t4, CfgUcharRead // machine check return address
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stl t4, 0(t1)
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mb // commit the store before reading
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DISABLE_INTERRUPTS // don't allow ints before Mcheck
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CfgUcharRead:
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ldl v0, (t0) // read the longword
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extbl v0, t3, v0 // return byte from requested lane
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// also, consume loaded value
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// to cause a pipeline stall
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mb // Gamma requires MBs or the
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mb // machine check may happen
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// much later
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stl zero, 0(t1) // Restore HalpConfigIoAccess
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ENABLE_INTERRUPTS // Interrupts OK after Mcheck
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3: //
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ldq ra, CfgRa(sp) // restore return address
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lda sp, CfgFrameLength(sp) // deallocate stack frame
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ret zero, (ra) // return
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.end READ_CONFIG_UCHAR
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//++
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//
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// VOID
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// WRITE_CONFIG_UCHAR(
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// ULONG ConfigurationAddress,
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// UCHAR ConfigurationData,
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// ULONG ConfigurationCycleType
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// )
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//
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// Routine Description:
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//
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// Read an unsigned byte from PCI configuration space.
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//
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// Arguments:
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//
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// ConfigurationAddress(a0) - Supplies the QVA to write.
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//
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// ConfigurationData(a1) - Supplies the data to be written.
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//
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// ConfigurationCycleType(a2) - Supplies the type of the configuration cycle.
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//
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// Return Value:
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//
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// None.
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//
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// N.B. - The configuration address must exist within the address space
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// allocated to an existing PCI device. Otherwise, the access
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// below will initiate an unrecoverable machine check.
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//
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//--
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NESTED_ENTRY( WRITE_CONFIG_UCHAR, CfgFrameLength, zero )
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lda sp, -CfgFrameLength(sp) // allocate stack frame
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stq ra, CfgRa(sp) // save return address
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PROLOGUE_END // end prologue
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//
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// Depending on whether it's a pass 1 or pass 2 T2 the configuration
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// cycle type is in different registers
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//
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ldl t0, T2VersionNumber // load version number
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beq t0, 1f // if 0 then pass 1 T2
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//
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// PASS 2 T2 or XIO access:
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// Merge the configuration cycle type into the HAE0_3 register within
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// the T2.
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//
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stq a0, CfgA0(sp) // save config space address
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stq a1, CfgA1(sp) // save config data
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//
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// Determine whether access is to T2 or T4 space:
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// Isolate the Base address bits: bit 22 indicates T4 space access
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//
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ldil t0, T4_CONFIG_ADDR_QVA // check for QVA in T4 space
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and t0, a0, t1 // isolate QVA base address
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ldil a0, T2_HAE0_3_QVA // address of HAE0_3
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xor t0, t1, t0 // T4 address space ? (bit 22 set)
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ldil t1, T4_HAE0_3_QVA // load address of T4 HAE register
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cmoveq t0, t1, a0 // if in T4 space, update a0
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sll a2, T2_HAE03_CYCLETYPE_SHIFT, a1 // put cycle type into position
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bsr ra, WRITE_T2_REGISTER // write updated HAE
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br zero, 2f
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//
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// Merge the configuration cycle type into the HAE0_3 register within
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// the T2.
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//
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1:
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stq a0, CfgA0(sp) // save config space address
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stq a1, CfgA1(sp) // save config data
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stq a2, CfgA2(sp) // save config cycle type
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ldil a0, T2_HAE0_2_QVA // address of HAE0_2
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bsr ra, READ_T2_REGISTER // read current value
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ldq a1, CfgA2(sp) // restore config cycle type
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ldil t0, T2_HAE02_CYCLETYPE_MASK // get cycle type field mask
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bic v0, t0, t0 // clear config cycle type field
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sll a1, T2_HAE02_CYCLETYPE_SHIFT, a1 // put cycle type into position
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bis a1, t0, a1 // merge config cycle type
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ldil a0, T2_HAE0_2_QVA // address of HAE0_2
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bsr ra, WRITE_T2_REGISTER // write updated HAE
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//
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// Perform the read from configuration space after restoring the
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// configuration space address and data.
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//
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2:
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ldq a0, CfgA0(sp) // restore config space address
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ldq a1, CfgA1(sp) // restore config data
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and a0, QVA_SELECTORS, t1 // get qva selector bits
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and a0, 0x3, t3 // capture byte lane
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xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE
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bne t1, 3f // if ne, iff failed
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zap a0, 0xf0, a0 // clear <63:32>
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bic a0, QVA_ENABLE, a0 // clear QVA fields
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sll a0, IO_BIT_SHIFT, t0 //
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ldiq t4, GAMMA_IO_SVA // 0xffff ffff ffff c800
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sll t4, 28, t4 // 0xffff fc80 0000 0000
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bis t0, t4, t0 // superpage mode
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bis t0, IO_BYTE_LEN, t0 // or in the byte length indicator
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insbl a1, t3, t4 // put byte in the appropriate lane
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stl t4, (t0) // write the configuration byte
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mb // synchronize
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mb // synchronize
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3:
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ldq ra, CfgRa(sp) // restore return address
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lda sp, CfgFrameLength(sp) // deallocate stack frame
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ret zero, (ra) // return
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.end WRITE_CONFIG_UCHAR
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//++
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//
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// ULONG
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// READ_CONFIG_USHORT(
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// ULONG ConfigurationAddress,
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// ULONG ConfigurationCycleType
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// )
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//
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// Routine Description:
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//
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// Read a longword from PCI configuration space.
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//
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// Arguments:
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//
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// ConfigurationAddress(a0) - Supplies the QVA of quadword to be read.
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//
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// ConfigurationCycleType(a1) - Supplies the type of the configuration cycle.
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//
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// Return Value:
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//
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// (v0) Returns the value of configuration space at the specified location.
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//
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// N.B. - This routine follows a protocol for reading from PCI configuration
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// space that allows the HAL or firmware to fixup and continue
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// execution if no device exists at the configuration target address.
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// The protocol requires 2 rules:
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// (1) The configuration space load must use a destination register
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// of v0
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// (2) The instruction immediately following the configuration space
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// load must use v0 as an operand (it must consume the value
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// returned by the load)
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//--
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NESTED_ENTRY( READ_CONFIG_USHORT, CfgFrameLength, zero )
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lda sp, -CfgFrameLength(sp) // allocate stack frame
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stq ra, CfgRa(sp) // save return address
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PROLOGUE_END // end prologue
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//
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// Depending on whether it's a pass 1 or pass 2 T2 the configuration
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// cycle type is in different registers
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//
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ldl t0, T2VersionNumber // load version number
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beq t0, 1f // if 0 then pass 1 T2
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//
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// PASS 2 T2 or XIO access:
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// Merge the configuration cycle type into the HAE0_2 register within
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// the T2.
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//
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stq a0, CfgA0(sp) // save config space address
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//
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// Determine whether access is to T2 or T4 space:
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// Isolate the Base address bits: bit 22 indicates T4 space access
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//
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ldil t0, T4_CONFIG_ADDR_QVA // check for QVA in T4 space
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and t0, a0, t1 // isolate QVA base address
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|
ldil a0, T2_HAE0_3_QVA // address of HAE0_3
|
|
xor t0, t1, t0 // T4 address space ? (bit 22 set)
|
|
|
|
ldil t1, T4_HAE0_3_QVA // load address of T4 HAE register
|
|
cmoveq t0, t1, a0 // if in T4 space, update a0
|
|
|
|
sll a1, T2_HAE03_CYCLETYPE_SHIFT, a1 // put cycle type into position
|
|
bsr ra, WRITE_T2_REGISTER // write updated HAE
|
|
|
|
br zero, 2f // go do actual io
|
|
|
|
//
|
|
// Pass 1 T2
|
|
// Merge the configuration cycle type into the HAE0_2 register within
|
|
// the T2.
|
|
//
|
|
1:
|
|
|
|
stq a0, CfgA0(sp) // save config space address
|
|
stq a1, CfgA1(sp) // save config cycle type
|
|
|
|
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
|
|
bsr ra, READ_T2_REGISTER // read current value
|
|
|
|
ldq a1, CfgA1(sp) // restore configuration cycle type
|
|
ldil t0, T2_HAE02_CYCLETYPE_MASK // get cycle type field mask
|
|
bic v0, t0, t0 // clear config cycle type field
|
|
|
|
sll a1, T2_HAE02_CYCLETYPE_SHIFT, a1 // put cycle type into position
|
|
bis a1, t0, a1 // merge config cycle type
|
|
|
|
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
|
|
bsr ra, WRITE_T2_REGISTER // write updated HAE
|
|
|
|
//
|
|
// Perform the read from configuration space after restoring the
|
|
// configuration space address.
|
|
//
|
|
2:
|
|
ldq a0, CfgA0(sp) // restore config space address
|
|
|
|
and a0, QVA_SELECTORS, t1 // get qva selector bits
|
|
and a0, 0x3, t3 // capture word offset
|
|
xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set
|
|
bne t1, 3f // if ne, iff failed
|
|
|
|
zap a0, 0xf0, a0 // clear <63:32>
|
|
bic a0, QVA_ENABLE, a0 // clear QVA fields
|
|
sll a0, IO_BIT_SHIFT, t0 //
|
|
ldiq t4, GAMMA_IO_SVA // 0xffff ffff ffff c800
|
|
sll t4, 28, t4 // 0xffff fc80 0000 0000
|
|
bis t0, t4, t0 // superpage mode
|
|
|
|
bis t0, IO_WORD_LEN, t0 // or in the byte enables
|
|
|
|
//
|
|
// Save Address of Config space address for the machine check handler:
|
|
//
|
|
lda t1, HalpConfigIoAccess
|
|
lda t4, CfgShortRead // machine check return address
|
|
stl t4, 0(t1)
|
|
mb // commit the store before reading
|
|
|
|
DISABLE_INTERRUPTS // don't allow ints before Mcheck
|
|
|
|
CfgShortRead:
|
|
|
|
ldl v0, (t0) // read the longword
|
|
extwl v0, t3, v0 // return word from requested lanes
|
|
// also, consume loaded value
|
|
// to cause a pipeline stall
|
|
mb // Gamma requires MBs or the
|
|
mb // machine check may happen
|
|
// much later
|
|
|
|
stl zero, 0(t1) // restore HalpConfigIoAccess
|
|
|
|
ENABLE_INTERRUPTS // Interrupts OK after Mcheck
|
|
|
|
3:
|
|
|
|
ldq ra, CfgRa(sp) // restore return address
|
|
lda sp, CfgFrameLength(sp) // deallocate stack frame
|
|
ret zero, (ra) // return
|
|
|
|
.end READ_CONFIG_USHORT
|
|
|
|
//++
|
|
//
|
|
// VOID
|
|
// WRITE_CONFIG_USHORT(
|
|
// ULONG ConfigurationAddress,
|
|
// USHORT ConfigurationData,
|
|
// ULONG ConfigurationCycleType
|
|
// )
|
|
//
|
|
// Routine Description:
|
|
//
|
|
// Read a longword from PCI configuration space.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// ConfigurationAddress(a0) - Supplies the QVA to write.
|
|
//
|
|
// ConfigurationData(a1) - Supplies the data to be written.
|
|
//
|
|
// ConfigurationCycleType(a2) - Supplies the type of the configuration cycle.
|
|
//
|
|
// Return Value:
|
|
//
|
|
// (v0) Returns the value of configuration space at the specified location.
|
|
//
|
|
// N.B. - The configuration address must exist within the address space
|
|
// allocated to an existing PCI device. Otherwise, the access
|
|
// below will initiate an unrecoverable machine check.
|
|
//
|
|
//--
|
|
|
|
NESTED_ENTRY( WRITE_CONFIG_USHORT, CfgFrameLength, zero )
|
|
|
|
lda sp, -CfgFrameLength(sp) // allocate stack frame
|
|
stq ra, CfgRa(sp) // save return address
|
|
|
|
PROLOGUE_END // end prologue
|
|
|
|
//
|
|
// Depending on whether it's a pass 1 or pass 2 T2 the configuration
|
|
// cycle type is in different registers
|
|
//
|
|
|
|
ldl t0, T2VersionNumber // load version number
|
|
beq t0, 1f // if 0 then pass 1 T2
|
|
|
|
//
|
|
// PASS 2 T2 or XIO access:
|
|
// Merge the configuration cycle type into the HAE0_2 register within
|
|
// the T2.
|
|
//
|
|
|
|
stq a0, CfgA0(sp) // save config space address
|
|
stq a1, CfgA1(sp) // save config data
|
|
|
|
//
|
|
// Determine whether access is to T2 or T4 space:
|
|
// Isolate the Base address bits: bit 22 indicates T4 space access
|
|
//
|
|
|
|
ldil t0, T4_CONFIG_ADDR_QVA // check for QVA in T4 space
|
|
and t0, a0, t1 // isolate QVA base address
|
|
|
|
ldil a0, T2_HAE0_3_QVA // address of HAE0_3
|
|
xor t0, t1, t0 // T4 address space ? (bit 22 set)
|
|
|
|
ldil t1, T4_HAE0_3_QVA // load address of T4 HAE register
|
|
cmoveq t0, t1, a0 // if in T4 space, update a0
|
|
|
|
sll a2, T2_HAE03_CYCLETYPE_SHIFT, a1 // put cycle type into position
|
|
bsr ra, WRITE_T2_REGISTER // write updated HAE
|
|
|
|
br zero, 2f // go do actual transfer
|
|
|
|
|
|
//
|
|
// Pass 1 T2
|
|
// Merge the configuration cycle type into the HAE0_2 register within
|
|
// the T2.
|
|
//
|
|
1:
|
|
|
|
stq a0, CfgA0(sp) // save config space address
|
|
stq a1, CfgA1(sp) // save config data
|
|
stq a2, CfgA2(sp) // save config cycle type
|
|
|
|
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
|
|
bsr ra, READ_T2_REGISTER // read current value
|
|
|
|
ldq a1, CfgA2(sp) // restore configuration cycle type
|
|
ldil t0, T2_HAE02_CYCLETYPE_MASK // get cycle type field mask
|
|
bic v0, t0, t0 // clear config cycle type field
|
|
|
|
sll a1, T2_HAE02_CYCLETYPE_SHIFT, a1 // put cycle type into position
|
|
bis a1, t0, a1 // merge config cycle type
|
|
|
|
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
|
|
bsr ra, WRITE_T2_REGISTER // write updated HAE
|
|
|
|
|
|
//
|
|
// Perform the read from configuration space after restoring the
|
|
// configuration space address and data.
|
|
//
|
|
2:
|
|
|
|
ldq a0, CfgA0(sp) // restore config space address
|
|
ldq a1, CfgA1(sp) // restore config data
|
|
|
|
and a0, QVA_SELECTORS, t1 // get qva selector bits
|
|
and a0, 0x3, t3 // capture word offset
|
|
xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set
|
|
bne t1, 3f // if ne, iff failed
|
|
|
|
zap a0, 0xf0, a0 // clear <63:32>
|
|
bic a0, QVA_ENABLE, a0 // clear QVA fields
|
|
sll a0, IO_BIT_SHIFT, t0 //
|
|
ldiq t4, GAMMA_IO_SVA // 0xffff ffff ffff c800
|
|
sll t4, 28, t4 // 0xffff fc80 0000 0000
|
|
bis t0, t4, t0 // superpage mode
|
|
|
|
bis t0, IO_WORD_LEN, t0 // or in the byte enables
|
|
|
|
inswl a1, t3, t4 // put data to appropriate lane
|
|
stl t4, (t0) // read the longword
|
|
mb // synchronize
|
|
mb // synchronize
|
|
3:
|
|
ldq ra, CfgRa(sp) // restore return address
|
|
lda sp, CfgFrameLength(sp) // deallocate stack frame
|
|
ret zero, (ra) // return
|
|
|
|
.end WRITE_CONFIG_USHORT
|
|
|
|
//++
|
|
//
|
|
// ULONG
|
|
// READ_CONFIG_ULONG(
|
|
// ULONG ConfigurationAddress,
|
|
// ULONG ConfigurationCycleType
|
|
// )
|
|
//
|
|
// Routine Description:
|
|
//
|
|
// Read a longword from PCI configuration space.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// ConfigurationAddress(a0) - Supplies the QVA of quadword to be read.
|
|
//
|
|
// ConfigurationCycleType(a1) - Supplies the type of the configuration cycle.
|
|
//
|
|
// Return Value:
|
|
//
|
|
// (v0) Returns the value of configuration space at the specified location.
|
|
//
|
|
// N.B. - This routine follows a protocol for reading from PCI configuration
|
|
// space that allows the HAL or firmware to fixup and continue
|
|
// execution if no device exists at the configuration target address.
|
|
// The protocol requires 2 rules:
|
|
// (1) The configuration space load must use a destination register
|
|
// of v0
|
|
// (2) The instruction immediately following the configuration space
|
|
// load must use v0 as an operand (it must consume the value
|
|
// returned by the load)
|
|
//--
|
|
|
|
NESTED_ENTRY( READ_CONFIG_ULONG, CfgFrameLength, zero )
|
|
|
|
lda sp, -CfgFrameLength(sp) // allocate stack frame
|
|
stq ra, CfgRa(sp) // save return address
|
|
|
|
PROLOGUE_END // end prologue
|
|
|
|
//
|
|
// Depending on whether it's a pass 1 or pass 2 T2 the configuration
|
|
// cycle type is in different registers
|
|
//
|
|
ldl t0, T2VersionNumber // load version number
|
|
beq t0, 1f // if 0 then pass 1 T2
|
|
|
|
//
|
|
// PASS 2 T2 or XIO access:
|
|
// Cycle type are the only bits in HAE0_3 register
|
|
//
|
|
stq a0, CfgA0(sp) // save config space address
|
|
|
|
//
|
|
// Determine whether access is to T2 or T4 space:
|
|
// Isolate the Base address bits: bit 22 indicates T4 space access
|
|
//
|
|
|
|
ldil t0, T4_CONFIG_ADDR_QVA // check for QVA in T4 space
|
|
and t0, a0, t1 // isolate QVA base address
|
|
|
|
ldil a0, T2_HAE0_3_QVA // address of HAE0_3
|
|
xor t0, t1, t0 // T4 address space ? (bit 22 set)
|
|
|
|
ldil t1, T4_HAE0_3_QVA // load address of T4 HAE register
|
|
cmoveq t0, t1, a0 // if in T4 space, update a0
|
|
|
|
sll a1, T2_HAE03_CYCLETYPE_SHIFT, a1 // put cycle type in position
|
|
bsr ra, WRITE_T2_REGISTER // write updated HAE
|
|
|
|
br zero, 2f // go do actual read
|
|
|
|
//
|
|
// PASS 1 T2
|
|
// Merge the configuration cycle type into the HAE0_2 register within
|
|
// the T2.
|
|
//
|
|
|
|
1:
|
|
|
|
stq a0, CfgA0(sp) // save config space address
|
|
stq a1, CfgA1(sp) // save config cycle type
|
|
|
|
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
|
|
bsr ra, READ_T2_REGISTER // read current value
|
|
|
|
ldq a1, CfgA1(sp) // restore config cycle type
|
|
ldil t0, T2_HAE02_CYCLETYPE_MASK // get cycle type field mask
|
|
bic v0, t0, t0 // clear config cycle type field
|
|
|
|
sll a1, T2_HAE02_CYCLETYPE_SHIFT, a1// put cycle type in position
|
|
bis a1, t0, a1 // merge config cycle type
|
|
|
|
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
|
|
bsr ra, WRITE_T2_REGISTER // write updated HAE
|
|
|
|
//
|
|
// Perform the read from configuration space after restoring the
|
|
// configuration space address.
|
|
//
|
|
|
|
2:
|
|
ldq a0, CfgA0(sp) // restore config space address
|
|
|
|
and a0, QVA_SELECTORS, t1 // get qva selector bits
|
|
xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set
|
|
bne t1, 3f // if ne, iff failed
|
|
|
|
zap a0, 0xf0, a0 // clear <63:32>
|
|
bic a0, QVA_ENABLE,a0 // clear QVA fields
|
|
sll a0, IO_BIT_SHIFT, t0 //
|
|
ldiq t4, GAMMA_IO_SVA // 0xffff ffff ffff c800
|
|
sll t4, 28, t4 // 0xffff fc80 0000 0000
|
|
or t0, t4, t0 // superpage mode
|
|
|
|
or t0, IO_LONG_LEN, t0 // or in the byte enables
|
|
|
|
//
|
|
// Save Address of Config space address for the machine check handler:
|
|
//
|
|
|
|
lda t1, HalpConfigIoAccess
|
|
lda t4, CfgUlongRead // machine check return address
|
|
stl t4, 0(t1)
|
|
mb // commit the store before reading
|
|
|
|
DISABLE_INTERRUPTS // don't take interrupt before MCHK
|
|
|
|
CfgUlongRead:
|
|
|
|
ldl v0, (t0) // read the longword
|
|
bis v0, zero, t4 // consume loaded value to cause
|
|
// a pipeline stall
|
|
mb // Gamma requires MBs or the
|
|
mb // machine check may happen
|
|
// much later
|
|
|
|
stl zero, 0(t1) // restore HalpConfigIoAccess
|
|
|
|
ENABLE_INTERRUPTS // Mcheck has occurred: allow ints
|
|
|
|
3:
|
|
ldq ra, CfgRa(sp) // restore return address
|
|
lda sp, CfgFrameLength(sp) // deallocate stack frame
|
|
ret zero, (ra) // return
|
|
|
|
.end READ_CONFIG_ULONG
|
|
|
|
|
|
//++
|
|
//
|
|
// VOID
|
|
// WRITE_CONFIG_ULONG(
|
|
// ULONG ConfigurationAddress,
|
|
// ULONG ConfigurationData,
|
|
// ULONG ConfigurationCycleType
|
|
// )
|
|
//
|
|
// Routine Description:
|
|
//
|
|
// Read a longword from PCI configuration space.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// ConfigurationAddress(a0) - Supplies the QVA to write.
|
|
//
|
|
// ConfigurationData(a1) - Supplies the data to be written.
|
|
//
|
|
// ConfigurationCycleType(a2) - Supplies the type of the configuration cycle.
|
|
//
|
|
// Return Value:
|
|
//
|
|
// (v0) Returns the value of configuration space at the specified location.
|
|
//
|
|
// N.B. - The configuration address must exist within the address space
|
|
// allocated to an existing PCI device. Otherwise, the access
|
|
// below will initiate an unrecoverable machine check.
|
|
//
|
|
//--
|
|
|
|
NESTED_ENTRY( WRITE_CONFIG_ULONG, CfgFrameLength, zero )
|
|
|
|
lda sp, -CfgFrameLength(sp) // allocate stack frame
|
|
stq ra, CfgRa(sp) // save return address
|
|
|
|
PROLOGUE_END // end prologue
|
|
|
|
//
|
|
// Depending on whether it's a pass 1 or pass 2 T2 the configuration
|
|
// cycle type is in different registers
|
|
//
|
|
|
|
ldl t0, T2VersionNumber // load version number
|
|
beq t0, 1f // if 0 then pass 1 T2
|
|
|
|
//
|
|
// PASS 2 T2 or XIO access:
|
|
// Merge the configuration cycle type into the HAE0_2 register within
|
|
// the T2.
|
|
//
|
|
|
|
stq a0, CfgA0(sp) // save config space address
|
|
stq a1, CfgA1(sp) // save config data
|
|
|
|
//
|
|
// Determine whether access is to T2 or T4 space:
|
|
// Isolate the Base address bits: bit 22 indicates T4 space access
|
|
//
|
|
|
|
ldil t0, T4_CONFIG_ADDR_QVA // check for QVA in T4 space
|
|
and t0, a0, t1 // isolate QVA base address
|
|
|
|
ldil a0, T2_HAE0_3_QVA // address of HAE0_3
|
|
xor t0, t1, t0 // T4 address space ? (bit 22 set)
|
|
|
|
ldil t1, T4_HAE0_3_QVA // load address of T4 HAE register
|
|
cmoveq t0, t1, a0 // if in T4 space, update a0
|
|
|
|
sll a2, T2_HAE03_CYCLETYPE_SHIFT, a1 // put cycle type into position
|
|
bsr ra, WRITE_T2_REGISTER // write updated HAE
|
|
|
|
br zero, 2f // go do actual transfer
|
|
|
|
|
|
//
|
|
// Pass 1 T2
|
|
// Merge the configuration cycle type into the HAE0_2 register within
|
|
// the T2.
|
|
//
|
|
1:
|
|
|
|
stq a0, CfgA0(sp) // save config space address
|
|
stq a1, CfgA1(sp) // save config data
|
|
stq a2, CfgA2(sp) // save config cycle type
|
|
|
|
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
|
|
bsr ra, READ_T2_REGISTER // read current value
|
|
|
|
ldq a1, CfgA2(sp) // restore configuration cycle type
|
|
ldil t0, T2_HAE02_CYCLETYPE_MASK // get cycle type field mask
|
|
bic v0, t0, t0 // clear config cycle type field
|
|
|
|
sll a1, T2_HAE02_CYCLETYPE_SHIFT, a1 // put cycle type into position
|
|
bis a1, t0, a1 // merge config cycle type
|
|
|
|
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
|
|
bsr ra, WRITE_T2_REGISTER // write updated HAE
|
|
|
|
//
|
|
// Perform the read from configuration space after restoring the
|
|
// configuration space address and data.
|
|
//
|
|
2:
|
|
|
|
ldq a0, CfgA0(sp) // restore config space address
|
|
ldq a1, CfgA1(sp) // restore config data
|
|
|
|
and a0, QVA_SELECTORS, t1 // get qva selector bits
|
|
xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set
|
|
bne t1, 3f // if ne, iff failed
|
|
|
|
zap a0, 0xf0, a0 // clear <63:32>
|
|
bic a0, QVA_ENABLE, a0 // clear QVA fields
|
|
sll a0, IO_BIT_SHIFT, t0 //
|
|
ldiq t4, GAMMA_IO_SVA // 0xffff ffff ffff c800
|
|
sll t4, 28, t4 // 0xffff fc80 0000 0000
|
|
bis t0, t4, t0 // superpage mode
|
|
|
|
bis t0, IO_LONG_LEN, t0 // or in the byte enables
|
|
|
|
stl a1, (t0) // write the longword
|
|
mb // synchronize
|
|
mb // synchronize
|
|
|
|
3: //
|
|
ldq ra, CfgRa(sp) // restore return address
|
|
lda sp, CfgFrameLength(sp) // deallocate stack frame
|
|
ret zero, (ra) // return
|
|
|
|
.end WRITE_CONFIG_ULONG
|