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587 lines
12 KiB
587 lines
12 KiB
/*++
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Copyright (c) 1990 Microsoft Corporation
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Copyright (c) 1992, 1993, 1994 Digital Equipment Corporation
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Module Name:
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pic8259.c
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Abstract:
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The module provides the interrupt support for the PCI SIO
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programmable interrupt controller.
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Author:
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Eric Rehm (DEC) 4-Feburary-1994
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Revision History:
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--*/
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#include "halp.h"
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#include "eisa.h"
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#if 0 //[wem] not yet
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extern PVOID HalpSioIntAckQva;
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extern ULONG HalpLegoPciRoutingType;
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#endif
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//
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// Import save area for SIO interrupt mask registers.
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//
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UCHAR HalpSioInterrupt1Mask;
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UCHAR HalpSioInterrupt2Mask;
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UCHAR HalpSioInterrupt1Level;
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UCHAR HalpSioInterrupt2Level;
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//
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// Define the context structure for use by interrupt service routines.
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//
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typedef BOOLEAN (*PSECOND_LEVEL_DISPATCH)(
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PKINTERRUPT InterruptObject
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);
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VOID
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HalpInitializeSioInterrupts (
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VOID
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)
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/*++
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Routine Description:
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This routine initializes the standard dual 8259 programmable interrupt
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controller.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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UCHAR DataByte;
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//
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// Initialize the SIO interrupt controller. There are two cascaded
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// interrupt controllers, each of which must initialized with 4 initialize
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// control words.
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//
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DataByte = 0;
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((PINITIALIZATION_COMMAND_1) &DataByte)->Icw4Needed = 1;
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((PINITIALIZATION_COMMAND_1) &DataByte)->InitializationFlag = 1;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort0,
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DataByte
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);
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort0,
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DataByte
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);
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//
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// The second intitialization control word sets the iterrupt vector to
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// 0-15.
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//
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DataByte = 0;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1,
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DataByte
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);
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DataByte = 0x08;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1,
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DataByte
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);
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//
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// The thrid initialization control word set the controls for slave mode.
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// The master ICW3 uses bit position and the slave ICW3 uses a numberic.
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//
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DataByte = 1 << SLAVE_IRQL_LEVEL;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1,
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DataByte
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);
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DataByte = SLAVE_IRQL_LEVEL;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1,
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DataByte
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);
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//
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// The fourth initialization control word is used to specify normal
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// end-of-interrupt mode and not special-fully-nested mode.
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//
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DataByte = 0;
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((PINITIALIZATION_COMMAND_4) &DataByte)->I80x86Mode = 1;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1,
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DataByte
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);
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1,
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DataByte
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);
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//
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// Disable all of the interrupts except the slave.
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//
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HalpSioInterrupt1Mask = (UCHAR)(~(1 << SLAVE_IRQL_LEVEL));
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1,
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HalpSioInterrupt1Mask
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);
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HalpSioInterrupt2Mask = 0xFF;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1,
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HalpSioInterrupt2Mask
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);
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//
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// Initialize the edge/level register masks to 0 which is the default
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// edge sensitive value.
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//
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HalpSioInterrupt1Level = 0;
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HalpSioInterrupt2Level = 0;
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return;
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}
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VOID
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HalpDisableSioInterrupt(
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IN ULONG Vector
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)
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/*++
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Routine Description:
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This function Disables the SIO bus specified SIO bus interrupt.
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Arguments:
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Vector - Supplies the vector of the ESIA interrupt that is Disabled.
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Return Value:
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None.
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--*/
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{
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//
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// Calculate the SIO interrupt vector.
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//
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Vector -= ISA_VECTORS;
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//
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// Determine if this vector is for interrupt controller 1 or 2.
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//
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if (Vector & 0x08) {
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//
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// The interrupt is in controller 2.
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//
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Vector &= 0x7;
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HalpSioInterrupt2Mask |= (UCHAR) 1 << Vector;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1,
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HalpSioInterrupt2Mask
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);
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} else {
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//
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// The interrupt is in controller 1.
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//
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Vector &= 0x7;
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//
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// never disable IRQL2, it is the slave interrupt
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//
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if (Vector != SLAVE_IRQL_LEVEL) {
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HalpSioInterrupt1Mask |= (ULONG) 1 << Vector;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1,
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HalpSioInterrupt1Mask
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);
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}
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}
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}
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VOID
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HalpEnableSioInterrupt(
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IN ULONG Vector,
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IN KINTERRUPT_MODE InterruptMode
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)
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/*++
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Routine Description:
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This function enables the SIO bus specified SIO bus interrupt.
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Arguments:
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Vector - Supplies the vector of the SIO interrupt that is enabled.
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InterruptMode - Supplies the mode of the interrupt; LevelSensitive or
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Latched.
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Return Value:
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None.
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--*/
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{
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//
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// Calculate the SIO interrupt vector.
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//
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Vector -= ISA_VECTORS;
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//
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// Determine if this vector is for interrupt controller 1 or 2.
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//
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if (Vector & 0x08) {
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//
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// The interrupt is in controller 2.
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//
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Vector &= 0x7;
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HalpSioInterrupt2Mask &= (UCHAR) ~(1 << Vector);
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1,
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HalpSioInterrupt2Mask
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);
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//
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// Set the level/edge control register.
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//
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if (InterruptMode == LevelSensitive) {
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HalpSioInterrupt2Level |= (UCHAR) (1 << Vector);
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} else {
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HalpSioInterrupt2Level &= (UCHAR) ~(1 << Vector);
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}
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2EdgeLevel,
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HalpSioInterrupt2Level
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);
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} else {
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//
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// The interrupt is in controller 1.
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//
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Vector &= 0x7;
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HalpSioInterrupt1Mask &= (UCHAR) ~(1 << Vector);
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1,
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HalpSioInterrupt1Mask
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);
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//
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// Set the level/edge control register.
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//
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if (InterruptMode == LevelSensitive) {
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HalpSioInterrupt1Level |= (UCHAR) (1 << Vector);
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} else {
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HalpSioInterrupt1Level &= (UCHAR) ~(1 << Vector);
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}
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1EdgeLevel,
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HalpSioInterrupt1Level
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);
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}
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}
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UCHAR
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HalpAcknowledgeSioInterrupt(
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PVOID ServiceContext
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)
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/*++
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Routine Description:
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Acknowledge the Sio interrupt. Return the vector number of the
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highest priority pending interrupt.
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Arguments:
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ServiceContext - Service context of the interrupt service - supplies
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a QVA to Lego's Master PCI interrupt register.
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Return Value:
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Return the value of the highest priority pending interrupt,
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or 0xff if none.
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--*/
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{
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UCHAR ISAVector;
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UCHAR Int1Isr;
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UCHAR Int2Isr;
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//
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// If PCI interrupts are being routed through the SIO, then
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// a write to HalpEisaIntAckBase will generate a correct
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// PCI Interrupt Acknowledge cycle for both PCI and ISA devices.
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//
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// If PCI interrupts are being routed through the interrupt
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// accelerator, then the Interrupt Acknowledge cannot be issued
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// on the PCI bus (since the SIO no longer has complete knowledge
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// of interrupts). Instead, ISA interrupts must be acknowledged
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// via a special port of the SIO, and PCI interrupts must be
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// acknowledged via a PCI Interrupt Acknowledge (but that's another
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// story).
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//
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#if 0 //[wem] not yet
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if (HalpLegoPciRoutingType == PCI_INTERRUPT_ROUTING_FULL) {
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//
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// The interrupt accelerator is active. Issue the
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// interrupt acknowledge directly to the SIO
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//
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ISAVector = READ_PORT_UCHAR(HalpSioIntAckQva);
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}
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else {
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// The interrupt accelerator is in PICMG mode. All
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// interrupts are going through the SIO, so a PCI
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// interrupt acknowledge is safe.
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//
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ISAVector = READ_PORT_UCHAR(HalpEisaIntAckBase);
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}
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#else
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//
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// Acknowledge the PCI/ISA interrupt via the SIO
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//
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// Note: This path is not used for PCI interrupts when
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// interrupt accelerator is active.
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//
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ISAVector = READ_PORT_UCHAR(HalpEisaIntAckBase);
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#endif
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if ((ISAVector & 0x07) == 0x07) {
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//
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// Check for a passive release by looking at the inservice register.
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// If there is a real IRQL7 interrupt, just go along normally. If there
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// is not, then it is a passive release. So just dismiss it.
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//
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort0,
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0x0B
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);
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Int1Isr = READ_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort0);
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//
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// do second controller
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//
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort0,
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0x0B
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);
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Int2Isr = READ_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort0);
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if (!(Int2Isr & 0x80) && !(Int1Isr & 0x80)) {
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//
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// Clear the master controller to clear situation
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//
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if (!(Int2Isr & 0x80)) {
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort0,
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NONSPECIFIC_END_OF_INTERRUPT
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);
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}
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return 0xFF; // ecrfix - now returns a value
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}
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}
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return ISAVector & 0x0F;
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}
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BOOLEAN
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HalpSioDispatch(
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VOID
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)
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/*++
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Routine Description:
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This routine is entered as the result of an interrupt being generated
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via the vector that is directly connected to an interrupt object that
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describes the SIO device interrupts. Its function is to call the second
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level interrupt dispatch routine and acknowledge the interrupt at the SIO
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controller.
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Arguments:
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None.
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Return Value:
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Returns the value returned from the second level routine.
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--*/
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{
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UCHAR ISAVector;
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PKPRCB Prcb;
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BOOLEAN returnValue;
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USHORT PCRInOffset;
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PULONG DispatchCode;
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PKINTERRUPT InterruptObject;
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//[wem] DEBUG - count SIO dispatch entries
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//
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static long SioCount = 0;
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#if DBG
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SioCount++;
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if (SioCount<5) {
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DbgPrint("II<SIO><");
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}
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if (SioCount % 1000 == 0) {
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DbgPrint("II<SIO><%08x><",SioCount);
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}
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#endif
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//
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// Acknowledge the Interrupt controller and receive the returned
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// interrupt vector.
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//
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ISAVector = HalpAcknowledgeSioInterrupt(NULL);
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if (ISAVector==0xff)
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return FALSE;
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//
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// Dispatch to the secondary interrupt service routine.
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//
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PCRInOffset = ISAVector + ISA_VECTORS;
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DispatchCode = (PULONG)PCR->InterruptRoutine[PCRInOffset];
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InterruptObject = CONTAINING_RECORD(DispatchCode,
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KINTERRUPT,
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DispatchCode);
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returnValue = ((PSECOND_LEVEL_DISPATCH)InterruptObject->DispatchAddress)(InterruptObject);
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//
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// Dismiss the interrupt in the SIO interrupt controllers.
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//
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//
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// If this is a cascaded interrupt then the interrupt must be dismissed in
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// both controlles.
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//
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if (ISAVector & 0x08) {
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort0,
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NONSPECIFIC_END_OF_INTERRUPT
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);
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}
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort0,
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NONSPECIFIC_END_OF_INTERRUPT
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);
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#if DBG //[wem]
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if (SioCount<5 || (SioCount % 1000)==0) {
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DbgPrint("%02x>.", returnValue);
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}
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#endif
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return(returnValue);
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}
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