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108 lines
2.3 KiB
108 lines
2.3 KiB
/*++
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Copyright (c) 1993 Microsoft Corporationn, Digital Equipment Corporation
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Module Name:
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pcibus.c
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Abstract:
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Platform-specific PCI bus routines
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Author:
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Environment:
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Kernel mode
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Revision History:
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--*/
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#include "halp.h"
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#include "pci.h"
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#include "pcip.h"
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#include "machdep.h"
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//
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// This references a boolean variable that identifies the APECS revision.
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//
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extern ULONG PCIMaxBus;
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PCI_CONFIGURATION_TYPES
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HalpPCIConfigCycleType(
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IN PBUS_HANDLER BusHandler
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)
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{
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if (BusHandler->BusNumber == 0) {
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return PciConfigType0;
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} else {
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return PciConfigType1;
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}
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}
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VOID
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HalpPCIConfigAddr (
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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PPCI_CFG_CYCLE_BITS pPciAddr
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)
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{
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PCI_CONFIGURATION_TYPES ConfigType;
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ConfigType = HalpPCIConfigCycleType(BusHandler);
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if (ConfigType == PciConfigType0)
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{
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//
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// Initialize PciAddr for a type 0 configuration cycle
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//
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// Device number is mapped to address bits 11:24, which, in APECS
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// pass 1, are wired to IDSEL pins. In pass 2, the format of a type
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// 0 cycle is the same as the format of a type 1. Note that
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// HalpValidPCISlot has already done bounds checking on DeviceNumber.
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//
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// PciAddr can be intialized for different bus numbers
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// with distinct configuration spaces here.
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//
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pPciAddr->u.AsULONG = (ULONG) APECS_PCI_CONFIG_BASE_QVA;
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pPciAddr->u.AsULONG += ( (Slot.u.bits.DeviceNumber) << 11 );
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pPciAddr->u.bits0.FunctionNumber = Slot.u.bits.FunctionNumber;
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pPciAddr->u.bits0.Reserved1 = PciConfigType0;
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#if HALDBG
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DbgPrint("HalpPCIConfigAddr: Type 0 PCI Config Access @ %x\n", pPciAddr->u.AsULONG);
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#endif // DBG
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}
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else
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{
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//
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// Initialize PciAddr for a type 1 configuration cycle
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//
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//
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pPciAddr->u.AsULONG = (ULONG) APECS_PCI_CONFIG_BASE_QVA;
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pPciAddr->u.bits1.BusNumber = BusHandler->BusNumber;
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pPciAddr->u.bits1.FunctionNumber = Slot.u.bits.FunctionNumber;
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pPciAddr->u.bits1.DeviceNumber = Slot.u.bits.DeviceNumber;
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pPciAddr->u.bits1.Reserved1 = PciConfigType1;
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#if HALDBG
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DbgPrint("Type 1 PCI Config Access @ %x\n", pPciAddr->u.AsULONG);
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#endif // DBG
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}
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return;
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}
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