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722 lines
22 KiB
722 lines
22 KiB
/*++
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Copyright (c) 1993 Digital Equipment Corporation
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Module Name:
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mikasa.h
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Abstract:
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This module specifies platform-specific definitions for the
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Mikasa modules.
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Author:
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Joe Notarangelo 25-Oct-1993
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Revision History:
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James Livingston 29-Apr-1994
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Adapted from Avanti module for Mikasa.
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Janet Schneider (Digital) 27-July-1995
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Added support for the Noritake.
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--*/
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#ifndef _MIKASA_
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#define _MIKASA_
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#include "alpharef.h"
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#include "apecs.h"
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#include "isaaddr.h"
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#define NUMBER_MIKASA_EISA_SLOTS 7
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#define NUMBER_MIKASA_PCI_SLOTS 3
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#define NUMBER_MIKASA_COMBO_SLOTS 1
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#define NUMBER_NORITAKE_EISA_SLOTS 2
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#define NUMBER_NORITAKE_PCI_SLOTS 7
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// Highest local PCI virtual slot number is 13 == IDSEL PCI_AD[24]
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#define PCI_MAX_LOCAL_DEVICE 13
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#if !defined (_LANGUAGE_ASSEMBLY)
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#if !defined (AXP_FIRMWARE)
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//
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// Define the per-processor data structures allocated in the PCR
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// for each EV4 processor.
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//
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typedef struct _MIKASA_PCR{
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ULONGLONG HalpCycleCount; // 64-bit per-processor cycle count
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EV4ProfileCount ProfileCount; // Profile counter state, do not move
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EV4IrqStatus IrqStatusTable[MaximumIrq]; // Irq status table
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} MIKASA_PCR, *PMIKASA_PCR;
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#endif
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//
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// Define the Mikasa server management data structure.
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//
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typedef union _MIKASA_SRV{
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struct {
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UCHAR FlashRomEnable : 1; // rw
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UCHAR DcPowerDisable : 1; // rw
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UCHAR HaltIncoming : 1; // ro
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UCHAR TempFail : 1; // ro
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UCHAR DcOk1 : 1; // ro
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UCHAR DcOk2 : 1; // ro
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UCHAR Fan1Fault : 1; // ro
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UCHAR Fan2Fault : 1; // ro
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};
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UCHAR All;
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} MIKASA_SRV, *PMIKASA_SRV;
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//
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// Define the Mikasa interrupt mask register. This is how we enable
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// and disable individual PCI interrupts. Actually, it's here more
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// for reference, since the interrupt enable/disable is done with a
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// computational algorithm.
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//
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typedef union _MIKASA_IMR{
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struct {
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ULONG Slot0IntA : 1;
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ULONG Slot0IntB : 1;
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ULONG Slot0IntC : 1;
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ULONG Slot0IntD : 1;
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ULONG Slot1IntA : 1;
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ULONG Slot1IntB : 1;
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ULONG Slot1IntC : 1;
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ULONG Slot1IntD : 1;
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ULONG Slot2IntA : 1;
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ULONG Slot2IntB : 1;
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ULONG Slot2IntC : 1;
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ULONG Slot2IntD : 1;
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ULONG Ncr810Scsi : 1;
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ULONG PwrInt : 1;
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ULONG TempWarn : 1;
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ULONG Reserved : 17;
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};
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ULONG All;
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} MIKASA_IMR, *PMIKASA_IMR;
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//
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// Define the Noritake server management data structure.
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//
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typedef union _NORITAKE_SRV{
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struct {
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UCHAR FlashRomEnable : 1; // rw
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UCHAR DcPowerDisable : 1; // rw
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UCHAR Reserved1: 2;
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UCHAR HaltIncoming : 1; // ro
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UCHAR FlashReady: 1; // ro
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UCHAR Reserved2: 1;
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UCHAR EmbeddedVGAStatus: 1; // rw
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};
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UCHAR All;
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} NORITAKE_SRV, *PNORITAKE_SRV;
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//
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// Define the Noritake interrupt mask registers. This is how we enable
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// and disable individual PCI interrupts. Actually, it's here more
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// for reference, since the interrupt enable/disable is done with a
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// computational algorithm.
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//
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//
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// Note: Slots 0 through 2 are on PCI bus 0, and slots 3 through 6 are
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// on PCI bus 1.
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//
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typedef union _NORITAKE_IMR1{
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struct {
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ULONG SumIr2And3 : 1;
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ULONG QLogic: 1;
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ULONG Slot0IntA : 1;
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ULONG Slot0IntB : 1;
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ULONG Slot1IntA : 1;
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ULONG Slot1IntB : 1;
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ULONG Slot2IntA : 1;
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ULONG Slot2IntB : 1;
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ULONG Slot3IntA : 1;
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ULONG Slot3IntB : 1;
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ULONG Slot4IntA : 1;
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ULONG Slot4IntB : 1;
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ULONG Slot5IntA : 1;
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ULONG Slot5IntB : 1;
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ULONG Slot6IntA : 1;
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ULONG Slot6IntB : 1;
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ULONG Reserved : 16;
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};
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ULONG ALL;
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} NORITAKE_IMR1, *PNORITAKE_IMR1;
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typedef union _NORITAKE_IMR2{
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struct {
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ULONG SumUnmaskedIr2 : 1;
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ULONG SecondaryPCIBusInt : 1;
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ULONG Slot0IntC : 1;
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ULONG Slot0IntD : 1;
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ULONG Slot1IntC : 1;
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ULONG Slot1IntD : 1;
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ULONG Slot2IntC : 1;
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ULONG Slot2IntD : 1;
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ULONG Slot3IntC : 1;
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ULONG Slot3IntD : 1;
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ULONG Slot4IntC : 1;
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ULONG Slot4IntD : 1;
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ULONG Slot5IntC : 1;
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ULONG Slot5IntD : 1;
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ULONG Slot6IntC : 1;
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ULONG Slot6IntD : 1;
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ULONG Reserved : 16;
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};
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ULONG ALL;
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} NORITAKE_IMR2, *PNORITAKE_IMR2;
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typedef union _NORITAKE_IMR3{
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struct {
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ULONG Reserved1 : 2;
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ULONG Power2Int : 1;
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ULONG Power1Int : 1;
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ULONG TempFail : 1;
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ULONG TempWarn : 1;
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ULONG Fan2Fail : 1;
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ULONG Fan1Fail : 1;
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ULONG Reserved2 : 24;
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};
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ULONG ALL;
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} NORITAKE_IMR3, *PNORITAKE_IMR3;
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#endif //!_LANGUAGE_ASSEMBLY
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#define HAL_PCR ( (PMIKASA_PCR)(&(PCR->HalReserved)) )
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#define PCI_VECTOR PRIMARY0_VECTOR // from alpharef.h
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#define PCI_MAX_INTERRUPT_VECTOR MAXIMUM_PCI_VECTOR // from alpharef.h
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#define PCI_SPARSE_IO_BASE_QVA ((ULONG)(HAL_MAKE_QVA(APECS_PCI_IO_BASE_PHYSICAL)))
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//
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// The combined Vendor ID, Device ID for the PCEB of the PCI/EISA bridge
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// chip set.
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//
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#define INTEL_PCI_EISA_BRIDGE_ID 0x04828086
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//
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// PCI-EISA Bridge chip configuration space base is at physical address
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// 0x1e0000000. The equivalent QVA is:
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// (0x1e0000000 >> IO_BIT_SHIFT) | QVA_ENABLE
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//
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// N.B.: The PCI configuration space address is what we're really referring
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// to, here.
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//
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#define PCI_CONFIGURATION_BASE_QVA 0xaf000000
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#define PCI_CONFIG_CYCLE_TYPE_0 0x0 // Local PCI device
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#define PCI_CONFIG_CYCLE_TYPE_1 0x1 // Nested PCI device
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#define PCI_EISA_BRIDGE_HEADER_OFFSET (0x00070000 >> IO_BIT_SHIFT) // AD[18]
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//
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// PCI-EISA Bridge Non-Configuration control register offsets. These should
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// be simply ored with PCI_SPARSE_IO_BASE_QVA; they match what's in the
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// Intel handbook for the 82374EB (ESC).
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//
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#define ESC_EDGE_LEVEL_CONTROL_1 0x4d0
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#define ESC_EDGE_LEVEL_CONTROL_2 0x4d1
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#define ESC_CMOS_ISA_PORT 0x800
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//
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// BIOS timer address port. This value is stuffed into PCEB configuration
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// space at PCEB/ESC cofiguration.
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//
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#define BIOS_TIMER_PORT 0x78
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//
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// Mikasa-unique registers, accessed via PCI_SPARSE_IO_BASE_QVA, via the
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// same protocol as above. Locations of these are intermixed with
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// ESC-specific and ordinary ISA registers in this space. N.B.: the
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// term "port" is used for compatibility with PC industry terminology.
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// We know Alphas don't have I/O instructions, nor ports, as such.
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//
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#define COMBO_CHIP_CONFIG_INDEX_PORT 0x398
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#define COMBO_CHIP_CONFIG_DATA_PORT 0x399
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//
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// Define I2C constants
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//
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#define I2C_INTERFACE_DATA_PORT 0x530
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#define I2C_INTERFACE_CSR_PORT 0x531
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#define I2C_INTERFACE_LENGTH 0x2
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#define I2C_INTERFACE_MASK 0x1
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//
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// This is the same for both Noritake and Mikasa
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//
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#define SERVER_MANAGEMENT_REGISTER 0x532
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//
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// Noritake interrupt and interrupt mask register offsets.
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//
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#define PCI_INTERRUPT_BASE_ADDRESS 0x540
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#define PCI_INTERRUPT_REGISTER_1 0x542
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#define PCI_INTERRUPT_REGISTER_2 0x544
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#define PCI_INTERRUPT_REGISTER_3 0x546
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#define PCI_INTERRUPT_MASK_REGISTER_1 0x54A
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#define PCI_INTERRUPT_MASK_REGISTER_2 0x54C
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#define PCI_INTERRUPT_MASK_REGISTER_3 0x54E
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//
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// Noritake PCI vector offsets. Interrupt vectors that originate from register
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// 1 start at 0x11 for bit position 0. So, when servicing an interrupt from
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// register 1, you must add 0x11 to the bit position to get the interrupt
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// vector. Likewise, if you have an interrupt vector, and you would like to
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// determine which interrupt register it resides in, you can use the vector
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// offsets to determine this. All vectors in interrupt register 1 are between
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// 0x11 and 0x20. All vectors in interrupt register 2 are between 0x21 and
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// 0x30. All vectors in interrupt register 3 are between 0x31 and 0x38.
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// Subtracting the vector offset for a register from the interrupt vector will
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// give you the bit position of the vector. For example, Vector 0x14
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// corresponds to bit 3 of interrupt register 1, Vector 0x27 corresponds to bit
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// 6 of interrupt register 2, and so on.
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//
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#define REGISTER_1_VECTOR_OFFSET 0x11
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#define REGISTER_2_VECTOR_OFFSET 0x21
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#define REGISTER_3_VECTOR_OFFSET 0x31
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//
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// Mikasa interrupt and interrupt mask register offsets.
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//
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#define PCI_INTERRUPT_REGISTER 0x534
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#define PCI_INTERRUPT_MASK_REGISTER 0x536
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//
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// Define the index and data ports for the NS Super IO (87312) chip.
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//
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#define SUPERIO_INDEX_PORT 0x398
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#define SUPERIO_DATA_PORT 0x399
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#define SUPERIO_PORT_LENGTH 0x2
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//
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// PCI Sparse I/O space offsets for unique functions on the ESC. They are
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// used as the offsets above.
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//
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#define ESC_CONFIG_ADDRESS 0x22
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#define ESC_CONFIG_DATA 0x23
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//
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// ESC configuration register index addresses. The protocol is:
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// write the configuration register address (one of the following)
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// into ESC_CONTROL_INDEX, then write the data into ESC_CONTROL_DATA.
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//
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#define ESC_INDEX_ESC_ID 0x02 // write 0xf to enable
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#define ESC_INDEX_REVISION_ID 0x08 // ro
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#define ESC_INDEX_MODE_SELECT 0x40 // rw
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#define ESC_INDEX_BIOS_CHIP_SELECT_A 0x42 // rw
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#define ESC_INDEX_BIOS_CHIP_SELECT_B 0x43 // rw
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#define ESC_INDEX_BCLK_CLOCK_DIVISOR 0x4d // rw
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#define ESC_INDEX_PERIPHERAL_CHIP_SELECT_A 0x4e // rw
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#define ESC_INDEX_PERIPHERAL_CHIP_SELECT_B 0x4f // rw
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#define ESC_INDEX_EISA_ID_BYTE_1 0x50 // rw
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#define ESC_INDEX_EISA_ID_BYTE_2 0x51 // rw
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#define ESC_INDEX_EISA_ID_BYTE_3 0x52 // rw
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#define ESC_INDEX_EISA_ID_BYTE_4 0x53 // rw
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#define ESC_INDEX_SG_RELOCATE_BASE 0x57 // rw
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#define ESC_INDEX_PIRQ0_ROUTE_CONTROL 0x60 // rw
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#define ESC_INDEX_PIRQ1_ROUTE_CONTROL 0x61 // rw
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#define ESC_INDEX_PIRQ2_ROUTE_CONTROL 0x62 // rw
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#define ESC_INDEX_PIRQ3_ROUTE_CONTROL 0x63 // rw
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#define ESC_INDEX_GPCS0_BASE_LOW 0x64 // rw
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#define ESC_INDEX_GPCS0_BASE_HIGH 0x65 // rw
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#define ESC_INDEX_GPCS0_MASK 0x66 // rw
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#define ESC_INDEX_GPCS1_BASE_LOW 0x68 // rw
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#define ESC_INDEX_GPCS1_BASE_HIGH 0x69 // rw
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#define ESC_INDEX_GPCS1_MASK 0x6a // rw
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#define ESC_INDEX_GPCS2_BASE_LOW 0x6c // rw
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#define ESC_INDEX_GPCS2_BASE_HIGH 0x6d // rw
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#define ESC_INDEX_GPCS2_MASK 0x6e // rw
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#define ESC_INDEX_GP_XBUS_CONTROL 0x6f // rw
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#if !defined (_LANGUAGE_ASSEMBLY)
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typedef union _ESC_MODESEL{
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struct {
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UCHAR EisaMasterSupport: 2;
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UCHAR Reserved1: 1;
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UCHAR SystemErrorEnable : 1;
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UCHAR EscSelect : 1;
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UCHAR CramPageEnable : 1;
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UCHAR MreqPirqEnable : 1;
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UCHAR Reserved2: 2;
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};
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UCHAR All;
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}ESC_MODESEL, *PESC_MODESEL;
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#define MS_4_EISA_MASTERS 0x00
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#define MS_6_EISA_MASTERS 0x01
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#define MS_7_EISA_MASTERS 0x02
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#define MS_8_EISA_MASTERS 0x03
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#define MS_RESERVED_MASK 0x84
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#define BIOSCSA_RESERVED_MASK 0xc0
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#define BIOSCSB_RESERVED_MASK 0xf0
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#define GPXBC_RESERVED_MASK 0xf8
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typedef union _ESC_CLKDIV{
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struct {
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UCHAR ClockDivisor: 3;
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UCHAR Reserved1: 1;
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UCHAR MouseInterruptEnable : 1;
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UCHAR CoprocessorError : 1;
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UCHAR Reserved2: 2;
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};
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UCHAR All;
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}ESC_CLKDIV, *PESC_CLKDIV;
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#define CLKDIV_33MHZ_EISA 0x00
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#define CLKDIV_25MHZ_EISA 0x01
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#define CLKDIV_RESERVED_MASK 0xc8
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typedef union _ESC_PCSA{
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struct {
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UCHAR RtcDecode: 1;
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UCHAR KeyboardControllerDecode: 1;
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UCHAR FloppyDiskSecondaryDecode : 1;
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UCHAR FloppyDiskPrimaryDecode : 1;
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UCHAR IdeDecode : 1;
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UCHAR FloppyIdeSpaceSecondary : 1;
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UCHAR Reserved : 2;
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};
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UCHAR All;
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}ESC_PCSA, *PESC_PCSA;
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#define PCSA_RESERVED_MASK 0xc0
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typedef union _ESC_PCSB{
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struct {
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UCHAR SerialPortADecode: 2;
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UCHAR SerialPortBDecode: 2;
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UCHAR ParallelPortDecode : 2;
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UCHAR Port92Decode : 1;
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UCHAR CramDecode : 1;
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};
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UCHAR All;
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}ESC_PCSB, *PESC_PCSB;
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#define PCSB_DECODE_DISABLE 0x3
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typedef union _ESC_PIRQ{
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struct {
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UCHAR IrqxRoutingBits: 7;
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UCHAR RoutePciInterrupts: 1;
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};
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UCHAR All;
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}ESC_PIRQ, *PESC_PIRQ;
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#define PIRQ_DISABLE_ROUTING 0x01
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#define PIRQ_ENABLE_ROUTING 0x00
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typedef union _ESC_GPXBC{
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struct {
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UCHAR EnableGpcs0: 1;
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UCHAR EnableGpcs1: 1;
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UCHAR EnableGpcs2: 1;
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UCHAR Reserved: 5;
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};
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UCHAR All;
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}ESC_GPXBC, *PESC_GPXBC;
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#endif // !_LANGUAGE_ASSEMBLY
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//
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// PCI-EISA Bridge Configuration register offsets. These should be
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// simply ored with PCI_CONFIGURATION_BASE_QVA; they match what's
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// in the Intel handbook for the 82375EB (PCEB).
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//
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#define PCI_VENDOR_ID 0x00 // ro
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#define PCI_DEVICE_ID 0x02 // ro
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#define PCI_COMMAND 0x04 // rw
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#define PCI_DEVICE_STATUS 0x06 // ro, rw clear
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#define PCI_REVISION 0x08 // ro
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#define PCI_MASTER_LATENCY_TIMER 0x0d // rw
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#define PCI_CONTROL 0x40 // rw
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#define PCI_ARBITER_CONTROL 0x41 // rw
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#define PCI_ARBITER_PRIORITY_CONTROL 0x42 // rw
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#define PCI_MEMCS_CONTROL 0x44 // rw
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#define PCI_MEMCS_BOTTOM_OF_HOLE 0x45 // rw
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#define PCI_MEMCS_TOP_OF_HOLE 0x46 // rw
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#define PCI_MEMCS_TOP_OF_MEMORY 0x47 // rw
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#define PCI_EISA_ADDRESS_DECODE_CONTROL_1 0x48 // rw
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#define PCI_ISA_IO_RECOVERY_TIME_CONTROL 0x4c // rw
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#define PCI_MEMCS_ATTRIBUTE_REGISTER_1 0x54 // rw
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#define PCI_MEMCS_ATTRIBUTE_REGISTER_2 0x55 // rw
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#define PCI_MEMCS_ATTRIBUTE_REGISTER_3 0x56 // rw
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#define PCI_DECODE_CONTROL 0x58 // rw
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#define PCI_EISA_ADDRESS_DECODE_CONTROL_2 0x5a // rw
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#define PCI_EISA_TO_PCI_MEMORY_REGIONS_ATTR 0x5c // rw
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#define PCI_EISA_TO_PCI_MEMORY_REGION1_REGISTER 0x60 // rw
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#define PCI_EISA_TO_PCI_MEMORY_REGION2_REGISTER 0x64 // rw
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#define PCI_EISA_TO_PCI_MEMORY_REGION3_REGISTER 0x68 // rw
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#define PCI_EISA_TO_PCI_MEMORY_REGION4_REGISTER 0x6c // rw
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#define PCI_EISA_TO_PCI_IO_REGION1_REGISTER 0x70 // rw
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#define PCI_EISA_TO_PCI_IO_REGION2_REGISTER 0x74 // rw
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#define PCI_EISA_TO_PCI_IO_REGION3_REGISTER 0x78 // rw
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#define PCI_EISA_TO_PCI_IO_REGION4_REGISTER 0x7c // rw
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#define PCI_BIOS_TIMER_BASE_ADDRESS 0x80 // rw
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#define PCI_EISA_LATENCY_TIMER_CONTROL_REGISTER 0x84 // rw
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#if !defined (_LANGUAGE_ASSEMBLY)
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//
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// Structure definitions of registers in PCEB PCI configuration space.
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// fields marked "Not supported" are Intel placeholders, apparently.
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//
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typedef union _PCEB_PCICMD{
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struct {
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USHORT IoSpaceEnable : 1;
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USHORT MemorySpaceEnable : 1;
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USHORT BusMasterEnable : 1;
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USHORT SpecialCycleEnable: 1; // Not supported
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USHORT MemoryWriteInvalidateEnable : 1; // Not supported
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USHORT VgaPaletteSnoop : 1; // Not supported
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USHORT ParityErrorEnable : 1;
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USHORT WaitStateControl : 1; // Not supported
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USHORT SerreEnable : 1; // Not supported
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USHORT Reserved : 7;
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};
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USHORT All;
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} PCEB_PCICMD, *PPCEB_PCICMD;
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typedef union _PCEB_PCISTS{
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struct {
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USHORT Reserved : 9;
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USHORT DevselTiming: 2; // ro
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USHORT SignaledTargetAbort : 1; // Not supported
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USHORT ReceivedTargetAbort: 1; // r/wc
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USHORT MasterAbort : 1; // r/wc
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USHORT Serrs : 1; // Not supported
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USHORT ParityError: 1; // r/wc
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};
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USHORT All;
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} PCEB_PCISTS, *PPCEB_PCISTS;
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typedef union _PCEB_MLT{
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struct {
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UCHAR Reserved : 3;
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UCHAR LatencyTimerCount: 5;
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};
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UCHAR All;
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} PCEB_MLT, *PPCEB_MLT;
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typedef union _PCEB_PCICON{
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struct {
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UCHAR Reserved1 : 2;
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UCHAR PciPostedWriteBuffersEnable: 1;
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UCHAR SubtractDecodeSamplePoint: 2;
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UCHAR InterruptAcknowledgeEnable: 1;
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UCHAR EisaToPciLineBuffersEnable: 1;
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UCHAR Reserved2 : 1;
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};
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|
UCHAR All;
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} PCEB_PCICON, *PPCEB_PCICON;
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#define PCICON_SDSP_SLOW 0x00
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#define PCICON_SDSP_TYPICAL 0x01
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#define PCICON_SDSP_FAST 0x02
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typedef union _PCEB_ARBCON{
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|
struct {
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|
UCHAR GuaranteedAccessTimeEnable : 1;
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|
UCHAR BusLockEnable: 1;
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|
UCHAR CpuBusParkEnable: 1;
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|
UCHAR MasterRetryTimer: 2;
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|
UCHAR Reserved : 2;
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|
UCHAR AutoPereqControlEnable: 1;
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|
};
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|
UCHAR All;
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} PCEB_ARBCON, *PPCEB_ARBCON;
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|
|
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#define ARBCON_RETRY_TIMER_DISABLE 0x00
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|
#define ARBCON_16_PCICLKS_UNMASK 0x01
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|
#define ARBCON_32_PCICLKS_UNMASK 0x02
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|
#define ARBCON_64_PCICLKS_UNMASK 0x03
|
|
|
|
typedef union _PCEB_ARBPRI{
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|
struct {
|
|
UCHAR Bank0FixedPriorityMode : 1;
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|
UCHAR Bank1FixedPriorityMode: 1;
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|
UCHAR Bank2FixedPriorityMode: 2;
|
|
UCHAR Bank0RotateEnable: 1;
|
|
UCHAR Bank1RotateEnable: 1;
|
|
UCHAR Bank2RotateEnable: 1;
|
|
UCHAR Bank3RotateEnable: 1;
|
|
};
|
|
UCHAR All;
|
|
} PCEB_ARBPRI, *PPCEB_ARBPRI;
|
|
|
|
#define ARBPRI_BANK0_BANK3_BANK1 0x00
|
|
#define ARBPRI_BANK3_BANK1_BANK0 0x10
|
|
#define ARBPRI_BANK1_BANK0_BANK3 0x01
|
|
|
|
typedef union _PCEB_MCSCON{
|
|
struct {
|
|
UCHAR ReadEnable512To640 : 1;
|
|
UCHAR WriteEnable512To640: 1;
|
|
UCHAR ReadEnableUpper64K: 1;
|
|
UCHAR WriteEnableUpper64K: 1;
|
|
UCHAR MemcsMasterEnable: 1;
|
|
UCHAR Reserved: 3;
|
|
};
|
|
UCHAR All;
|
|
} PCEB_MCSCON, *PPCEB_MCSCON;
|
|
|
|
typedef union _PCEB_EADC1{
|
|
struct {
|
|
USHORT Block0To512 : 1;
|
|
USHORT Block512To640: 1;
|
|
USHORT Block640To768: 1;
|
|
USHORT Reserved: 5;
|
|
USHORT Block768To784: 1;
|
|
USHORT Block784To800: 1;
|
|
USHORT Block800To816: 1;
|
|
USHORT Block816To832: 1;
|
|
USHORT Block832To848: 1;
|
|
USHORT Block848To864: 1;
|
|
USHORT Block864To880: 1;
|
|
USHORT Block880To896: 1;
|
|
};
|
|
UCHAR All;
|
|
} PCEB_EADC1, *PPCEB_EADC1;
|
|
|
|
typedef union _PCEB_IORT{
|
|
struct {
|
|
UCHAR RecoveryTimes16Bit : 2;
|
|
UCHAR RecoveryEnable16Bit: 1;
|
|
UCHAR RecoveryTimes8Bit : 3;
|
|
UCHAR RecoveryEnable8Bit: 1;
|
|
UCHAR Reserved: 1;
|
|
};
|
|
UCHAR All;
|
|
} PCEB_IORT, *PPCEB_IORT;
|
|
|
|
#define IORT_16BIT_1BCLK 0x01
|
|
#define IORT_16BIT_2BCLKS 0x02
|
|
#define IORT_16BIT_3BCLKS 0x03
|
|
#define IORT_16BIT_4BCLKS 0x00
|
|
|
|
#define IORT_8BIT_1BCLK 0x01
|
|
#define IORT_8BIT_2BCLKS 0x02
|
|
#define IORT_8BIT_3BCLKS 0x03
|
|
#define IORT_8BIT_4BCLKS 0x04
|
|
#define IORT_8BIT_5BCLKS 0x05
|
|
#define IORT_8BIT_6BCLKS 0x06
|
|
#define IORT_8BIT_7BCLKS 0x07
|
|
#define IORT_8BIT_8BCLKS 0x00
|
|
|
|
typedef union _PCEB_PDCON{
|
|
struct {
|
|
UCHAR PciDecodeMode : 1;
|
|
UCHAR Reserved1: 3;
|
|
UCHAR DecodeControlIde : 1;
|
|
UCHAR DecodeControl8259 : 1;
|
|
UCHAR Reserved2: 2;
|
|
};
|
|
UCHAR All;
|
|
} PCEB_PDCON, *PPCEB_PDCON;
|
|
|
|
#define SUBTRACTIVE_DECODE 0x00
|
|
#define NEGATIVE_DECODE 0x01
|
|
|
|
typedef struct _PCEB_EPMRA{
|
|
struct {
|
|
UCHAR Region1Attribute : 1;
|
|
UCHAR Region2Attribute : 1;
|
|
UCHAR Region3Attribute : 1;
|
|
UCHAR Region4Attribute : 1;
|
|
UCHAR Reserved: 4;
|
|
};
|
|
UCHAR All;
|
|
} PCEB_EPMRA, *PPCEB_EPMRA;
|
|
|
|
#define REGION_BUFFERED 0x01
|
|
|
|
typedef struct _PCEB_MEMREGN{
|
|
USHORT BaseAddress;
|
|
USHORT LimitAddress;
|
|
} PCEB_MEMREGN, *PPCEB_MEMREGN;
|
|
|
|
typedef union _PCEB_IOREGN{
|
|
struct {
|
|
ULONG Reserved1: 2;
|
|
ULONG BaseAddress : 14;
|
|
ULONG Reserved2: 2;
|
|
ULONG LimitAddress : 14;
|
|
};
|
|
ULONG All;
|
|
} PCEB_IOREGN, *PPCEB_IOREGN;
|
|
|
|
typedef union _PCEB_BTMR{
|
|
struct {
|
|
USHORT BiosTimerEnable: 1;
|
|
USHORT Reserved: 1;
|
|
USHORT BaseAddress2thru15 : 14;
|
|
};
|
|
USHORT All;
|
|
} PCEB_BTMR, *PPCEB_BTMR;
|
|
|
|
#endif
|
|
|
|
//
|
|
// ESC value for setting edge/level operation in the control words.
|
|
//
|
|
#define IRQ0_LEVEL_SENSITIVE 0x01
|
|
#define IRQ1_LEVEL_SENSITIVE 0x02
|
|
#define IRQ2_LEVEL_SENSITIVE 0x04
|
|
#define IRQ3_LEVEL_SENSITIVE 0x08
|
|
#define IRQ4_LEVEL_SENSITIVE 0x10
|
|
#define IRQ5_LEVEL_SENSITIVE 0x20
|
|
#define IRQ6_LEVEL_SENSITIVE 0x40
|
|
#define IRQ7_LEVEL_SENSITIVE 0x80
|
|
#define IRQ8_LEVEL_SENSITIVE 0x01
|
|
#define IRQ9_LEVEL_SENSITIVE 0x02
|
|
#define IRQ10_LEVEL_SENSITIVE 0x04
|
|
#define IRQ11_LEVEL_SENSITIVE 0x08
|
|
#define IRQ12_LEVEL_SENSITIVE 0x10
|
|
#define IRQ13_LEVEL_SENSITIVE 0x20
|
|
#define IRQ14_LEVEL_SENSITIVE 0x40
|
|
#define IRQ15_LEVEL_SENSITIVE 0x80
|
|
|
|
//
|
|
// Define primary (and only) CPU on an Mikasa system
|
|
//
|
|
|
|
#define HAL_PRIMARY_PROCESSOR ((ULONG)0x0)
|
|
#define HAL_MAXIMUM_PROCESSOR ((ULONG)0x0)
|
|
|
|
//
|
|
// Define the default processor clock frequency used before the actual
|
|
// value can be determined.
|
|
//
|
|
|
|
#define DEFAULT_PROCESSOR_FREQUENCY_MHZ (200)
|
|
|
|
#endif // _MIKASA_
|