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219 lines
5.1 KiB
219 lines
5.1 KiB
/*++
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Copyright (c) 1993 Digital Equipment Corporation
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Module Name:
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mkmapio.c
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Abstract:
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This module contains the functions to map HAL-accessed I/O addresses
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on the Mikasa system.
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Author:
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Joe Notarangelo 25-Oct-1993
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Environment:
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Kernel mode
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Revision History:
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James Livingston 29-Apr-1994
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Adapted from Avanti module for Mikasa.
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Janet Schneider (Digital) 27-July-1995
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Added support for the Noritake.
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--*/
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#include "halp.h"
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#include "mikasa.h"
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//
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// Define global data used to locate the EISA control space.
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//
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PVOID HalpEisaControlBase;
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PVOID HalpEisaIntAckBase;
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PVOID HalpCMOSRamBase;
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PVOID HalpServerControlQva;
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PVOID HalpMikasaPciIrQva;
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PVOID HalpMikasaPciImrQva;
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PVOID HalpNoritakePciIr1Qva;
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PVOID HalpNoritakePciIr2Qva;
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PVOID HalpNoritakePciIr3Qva;
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PVOID HalpNoritakePciImr1Qva;
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PVOID HalpNoritakePciImr2Qva;
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PVOID HalpNoritakePciImr3Qva;
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BOOLEAN
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HalpMapIoSpace (
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VOID
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)
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/*++
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Routine Description:
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This routine maps the HAL I/O space for a Mikasa system using
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the Quasi VA mechanism.
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Arguments:
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None.
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Return Value:
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If the initialization is successfully completed, than a value of TRUE
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is returned. Otherwise, a value of FALSE is returned.
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--*/
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{
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PVOID PciIoSpaceBase;
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//
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// Map base addresses in QVA space.
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//
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PciIoSpaceBase = HAL_MAKE_QVA( APECS_PCI_IO_BASE_PHYSICAL );
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HalpEisaControlBase = PciIoSpaceBase;
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HalpEisaIntAckBase = HAL_MAKE_QVA( APECS_PCI_INTACK_BASE_PHYSICAL );
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//
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// Set up the Mikasa interrupt registers.
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//
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// Map PCI interrupt and interrupt mask registers. The former register
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// receives the interrupt state of each individual pin in each PCI slot,
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// the state of the NCR 53C810 interrupt, and two server management
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// interrupts' states. The PCI interrupt mask register can mask each
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// of the interrupts in the IR.
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//
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HalpMikasaPciIrQva = (PVOID)((ULONG)PciIoSpaceBase
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+ PCI_INTERRUPT_REGISTER);
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HalpMikasaPciImrQva = (PVOID)((ULONG)PciIoSpaceBase
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+ PCI_INTERRUPT_MASK_REGISTER);
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//
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// Set up the Noritake interrupt registers.
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//
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// Map the PCI interrupt and interrupt mask registers for Noritake.
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// There are three interrupt registers, and three mask registers.
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// The exact contents are described in mikasa.h.
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//
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// The Base Address Register of the interrupt registers is set up in SROM.
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// We can change this if we choose.
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//
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HalpNoritakePciIr1Qva = (PVOID)((ULONG)PciIoSpaceBase
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+ PCI_INTERRUPT_REGISTER_1);
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HalpNoritakePciImr1Qva = (PVOID)((ULONG)PciIoSpaceBase
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+ PCI_INTERRUPT_MASK_REGISTER_1);
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HalpNoritakePciIr2Qva = (PVOID)((ULONG)PciIoSpaceBase
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+ PCI_INTERRUPT_REGISTER_2);
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HalpNoritakePciImr2Qva = (PVOID)((ULONG)PciIoSpaceBase
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+ PCI_INTERRUPT_MASK_REGISTER_2);
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HalpNoritakePciIr3Qva = (PVOID)((ULONG)PciIoSpaceBase
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+ PCI_INTERRUPT_REGISTER_3);
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HalpNoritakePciImr3Qva = (PVOID)((ULONG)PciIoSpaceBase
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+ PCI_INTERRUPT_MASK_REGISTER_3);
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//
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// Map the Mikasa server management register. This single byte register
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// contains the bits that enable control of the high-availability options
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// on Mikasa. This is at the same location in the Noritake, but it has a
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// slightly different content.
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//
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HalpServerControlQva = (PVOID)((ULONG)PciIoSpaceBase
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+ SERVER_MANAGEMENT_REGISTER);
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//
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// Map CMOS RAM address.
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//
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HalpCMOSRamBase = (PVOID)((ULONG)PciIoSpaceBase + ESC_CMOS_ISA_PORT);
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//
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// Map the real-time clock registers.
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//
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HalpRtcAddressPort = (PVOID)((ULONG)PciIoSpaceBase + RTC_ISA_ADDRESS_PORT);
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HalpRtcDataPort = (PVOID)((ULONG)PciIoSpaceBase + RTC_ISA_DATA_PORT);
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return TRUE;
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}
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ULONG
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HalpMapDebugPort(
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IN ULONG ComPort,
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OUT PULONG ReadQva,
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OUT PULONG WriteQva
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)
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/*++
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Routine Description:
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This routine maps the debug com port so that the kernel debugger
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may function - if called it is called very earlier in the boot sequence.
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Arguments:
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ComPort - Supplies the number of the com port to use as the debug port.
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ReadQva - Receives the QVA used to access the read registers of the debug
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port.
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WriteQva - Receives the QVA used to access the write registers of the
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debug port.
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Return Value:
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Returns the base bus address of the device used as the debug port.
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--*/
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{
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ULONG ComPortAddress;
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ULONG PortQva;
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//
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// Compute the port address, based on the desired com port.
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//
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switch( ComPort ){
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case 1:
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ComPortAddress = COM1_ISA_PORT_ADDRESS;
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break;
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case 2:
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default:
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ComPortAddress = COM2_ISA_PORT_ADDRESS;
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}
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//
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// Return the QVAs for read and write access.
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//
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PortQva = (ULONG)HAL_MAKE_QVA(APECS_PCI_IO_BASE_PHYSICAL) + ComPortAddress;
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*ReadQva = PortQva;
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*WriteQva = PortQva;
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return ComPortAddress;
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}
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