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551 lines
11 KiB
551 lines
11 KiB
/*++
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Copyright (c) 1993 Digital Equipment Corporation
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Module Name:
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mkinitnt.c
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Abstract:
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This module implements the HAL enable/disable system interrupt, and
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request interprocessor interrupt routines for the Mikasa system.
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Author:
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Joe Notarangelo 25-Oct-1993
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Environment:
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Kernel mode
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Revision History:
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James Livingston 29-Apr-1994
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Adapted from Avanti module for Mikasa.
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Janet Schneider (Digital) 27-July-1995
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Added support for the Noritake.
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--*/
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#include "halp.h"
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#include "mikasa.h"
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#include "axp21064.h"
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//
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// Function prototype
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//
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VOID
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HalpDisableMikasaPciInterrupt(
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IN ULONG Vector
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);
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VOID
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HalpDisableNoritakePciInterrupt(
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IN ULONG Vector
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);
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VOID
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HalpEnableMikasaPciInterrupt(
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IN ULONG Vector,
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IN KINTERRUPT_MODE InterruptMode
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);
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VOID
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HalpEnableNoritakePciInterrupt(
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IN ULONG Vector,
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IN KINTERRUPT_MODE InterruptMode
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);
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VOID
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HalpSetMachineCheckEnables(
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IN BOOLEAN DisableMachineChecks,
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IN BOOLEAN DisableProcessorCorrectables,
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IN BOOLEAN DisableSystemCorrectables
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);
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//
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// Define reference to the builtin device interrupt enables.
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//
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extern USHORT HalpBuiltinInterruptEnable;
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//
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// Define reference to platform identifier
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//
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extern BOOLEAN HalpNoritakePlatform;
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VOID
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HalDisableSystemInterrupt (
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IN ULONG Vector,
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IN KIRQL Irql
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)
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/*++
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Routine Description:
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This routine disables the specified system interrupt.
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Arguments:
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Vector - Supplies the vector of the system interrupt that is disabled.
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Irql - Supplies the IRQL of the interrupting source.
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Return Value:
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None.
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--*/
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{
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KIRQL OldIrql;
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//
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// Raise IRQL to the highest level.
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//
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KeRaiseIrql(HIGH_LEVEL, &OldIrql);
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//
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// If the vector number is within the range of the EISA interrupts, then
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// disable the EISA interrrupt.
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//
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if (Vector >= EISA_VECTORS &&
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Vector < MAXIMUM_EISA_VECTOR &&
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Irql == EISA_DEVICE_LEVEL) {
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HalpDisableEisaInterrupt(Vector);
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}
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//
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// If the vector number is within the range of the PCI interrupts, then
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// disable the PCI interrrupt.
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//
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if (Vector >= PCI_VECTORS &&
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Vector < MAXIMUM_PCI_VECTOR &&
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Irql == PCI_DEVICE_LEVEL) {
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if( HalpNoritakePlatform ) {
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HalpDisableNoritakePciInterrupt(Vector);
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} else {
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HalpDisableMikasaPciInterrupt(Vector);
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}
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}
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//
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// If the vector is a performance counter vector or one of the internal
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// device vectors then disable the interrupt for the 21064.
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//
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switch (Vector) {
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//
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// Performance counter 0 interrupt (internal to 21064)
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//
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case PC0_VECTOR:
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case PC0_SECONDARY_VECTOR:
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HalpDisable21064PerformanceInterrupt( PC0_VECTOR );
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break;
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//
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// Performance counter 1 interrupt (internal to 21064)
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//
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case PC1_VECTOR:
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case PC1_SECONDARY_VECTOR:
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HalpDisable21064PerformanceInterrupt( PC1_VECTOR );
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break;
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case CORRECTABLE_VECTOR:
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//
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// Disable the correctable error interrupt.
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//
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{
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EPIC_ECSR Ecsr;
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Ecsr.all = READ_EPIC_REGISTER(
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&((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->EpicControlAndStatusRegister );
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Ecsr.Dcei = 0x0;
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WRITE_EPIC_REGISTER(
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&((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->EpicControlAndStatusRegister,
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Ecsr.all );
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HalpSetMachineCheckEnables( FALSE, TRUE, TRUE );
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}
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break;
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} //end switch Vector
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//
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// Lower IRQL to the previous level.
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//
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KeLowerIrql(OldIrql);
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return;
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}
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BOOLEAN
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HalEnableSystemInterrupt (
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IN ULONG Vector,
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IN KIRQL Irql,
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IN KINTERRUPT_MODE InterruptMode
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)
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/*++
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Routine Description:
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This routine enables the specified system interrupt.
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Arguments:
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Vector - Supplies the vector of the system interrupt that is enabled.
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Irql - Supplies the IRQL of the interrupting source.
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InterruptMode - Supplies the mode of the interrupt; LevelSensitive or
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Latched.
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Return Value:
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TRUE if the system interrupt was enabled
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--*/
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{
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BOOLEAN Enabled = FALSE;
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KIRQL OldIrql;
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//
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// Raise IRQL to the highest level.
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//
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KeRaiseIrql(HIGH_LEVEL, &OldIrql);
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//
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// If the vector number is within the range of the EISA interrupts, then
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// enable the EISA interrrupt and set the Level/Edge register.
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//
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if (Vector >= EISA_VECTORS &&
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Vector < MAXIMUM_EISA_VECTOR &&
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Irql == EISA_DEVICE_LEVEL) {
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HalpEnableEisaInterrupt( Vector, InterruptMode );
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Enabled = TRUE;
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}
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//
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// If the vector number is within the range of the PCI interrupts, then
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// enable the PCI interrrupt.
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//
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if (Vector >= PCI_VECTORS &&
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Vector < MAXIMUM_PCI_VECTOR &&
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Irql == PCI_DEVICE_LEVEL) {
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if( HalpNoritakePlatform ) {
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HalpEnableNoritakePciInterrupt( Vector, InterruptMode );
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} else {
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HalpEnableMikasaPciInterrupt( Vector, InterruptMode );
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}
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Enabled = TRUE;
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}
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//
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// If the vector is a performance counter vector or one of the
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// internal device vectors then perform 21064-specific enable.
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//
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switch (Vector) {
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//
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// Performance counter 0 (internal to 21064)
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//
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case PC0_VECTOR:
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case PC0_SECONDARY_VECTOR:
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HalpEnable21064PerformanceInterrupt( PC0_VECTOR, Irql );
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Enabled = TRUE;
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break;
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//
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// Performance counter 1 (internal to 21064)
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//
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case PC1_VECTOR:
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case PC1_SECONDARY_VECTOR:
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HalpEnable21064PerformanceInterrupt( PC1_VECTOR, Irql );
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Enabled = TRUE;
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break;
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case CORRECTABLE_VECTOR:
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//
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// Enable the correctable error interrupt.
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//
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{
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EPIC_ECSR Ecsr;
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Ecsr.all = READ_EPIC_REGISTER(
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&((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->EpicControlAndStatusRegister );
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Ecsr.Dcei = 0x1;
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WRITE_EPIC_REGISTER(
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&((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->EpicControlAndStatusRegister,
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Ecsr.all );
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HalpSetMachineCheckEnables( FALSE, FALSE, FALSE );
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}
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Enabled = TRUE;
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break;
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} //end switch Vector
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//
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// Lower IRQL to the previous level.
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//
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KeLowerIrql(OldIrql);
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return Enabled;
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}
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ULONG
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HalpGetSystemInterruptVector(
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN ULONG BusInterruptLevel,
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IN ULONG BusInterruptVector,
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OUT PKIRQL Irql,
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OUT PKAFFINITY Affinity
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)
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/*++
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Routine Description:
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This function returns the system interrupt vector and IRQL level
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corresponding to the specified bus interrupt level and/or vector. The
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system interrupt vector and IRQL are suitable for use in a subsequent
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call to KeInitializeInterrupt.
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We only use InterfaceType and BusInterruptLevel. BusInterruptVector
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for EISA and ISA are the same as the InterruptLevel, so ignore.
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jwlfix - How does the above apply to PCI when it's done as in Mikasa? I've
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made the assumption the the same is true, but that must be checked.
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Arguments:
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BusHandler - Registered BUSHANDLER for the target configuration space
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RootHandler - Registered BUSHANDLER for the orginating HalGetBusData
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request.
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BusInterruptLevel - Supplies the bus-specific interrupt level.
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BusInterruptVector - Supplies the bus-specific interrupt vector.
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Irql - Returns the system request priority.
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Affinity - Returns the affinity for the requested vector
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Return Value:
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Returns the system interrupt vector corresponding to the specified device.
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--*/
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{
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INTERFACE_TYPE InterfaceType = BusHandler->InterfaceType;
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ULONG BusNumber = BusHandler->BusNumber;
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ULONG Vector;
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*Affinity = 1;
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switch (InterfaceType) {
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case ProcessorInternal:
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//
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// Handle the internal defined for the processor itself
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// and used to control the performance counters in the 21064.
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//
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if( (Vector = HalpGet21064PerformanceVector( BusInterruptLevel,
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Irql)) != 0 ){
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//
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// Performance counter was successfully recognized.
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//
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*Affinity = HalpActiveProcessors;
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return Vector;
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} else if ((Vector = HalpGet21064CorrectableVector( BusInterruptLevel,
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Irql)) != 0 ){
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//
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// Correctable error interrupt was sucessfully recognized.
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//
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*Affinity = 1;
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return Vector;
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} else {
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//
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// Unrecognized processor interrupt.
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//
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*Irql = 0;
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*Affinity = 0;
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return 0;
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} //end if Vector
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break;
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case Internal:
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//
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// This bus type is for things connected to the processor
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// in some way other than a standard bus, e.g., (E)ISA, PCI.
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// Since devices on this "bus," apart from the special case of
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// the processor, above, interrupt via the 82c59 cascade in the
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// ESC, we assign vectors based on (E)ISA_VECTORS - see below.
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// Firmware must agree on these vectors, as it puts them in
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// the CDS.
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//
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*Irql = ISA_DEVICE_LEVEL;
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return(BusInterruptLevel + ISA_VECTORS);
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break;
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case Isa:
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//
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// Assumes all ISA devices coming in on same processor pin
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//
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*Irql = ISA_DEVICE_LEVEL;
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//
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// The vector is equal to the specified bus level plus ISA_VECTORS.
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// N.B.: this encoding technique uses the notion of defining a
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// base interrupt vector in the space defined by the constant,
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// ISA_VECTORS, which may or may not differ from EISA_VECTORS or
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// PCI_VECTORS.
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//
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return(BusInterruptLevel + ISA_VECTORS);
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break;
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case Eisa:
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//
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// Assumes all EISA devices coming in on same processor pin
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//
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*Irql = EISA_DEVICE_LEVEL;
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//
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// The vector is equal to the specified bus level plus the EISA_VECTOR.
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//
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return(BusInterruptLevel + EISA_VECTORS);
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break;
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case PCIBus:
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//
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// Assumes all PCI devices coming in on same processor pin
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//
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*Irql = PCI_DEVICE_LEVEL;
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//
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// The vector is equal to the specified bus level plus the PCI_VECTOR
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//
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return((BusInterruptLevel) + PCI_VECTORS);
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break;
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default:
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//
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// Not an interface supported on Mikasa systems.
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//
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#if defined(HALDBG)
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DbgPrint("MKSYSINT: InterfaceType (%d) not supported on Mikasa\r\n",
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InterfaceType);
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#endif
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*Irql = 0;
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*Affinity = 0;
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return(0);
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break;
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} //end switch(InterfaceType)
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}
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VOID
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HalRequestIpi (
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IN ULONG Mask
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)
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/*++
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Routine Description:
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This routine requests an interprocessor interrupt on a set of processors.
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This routine performs no function on an Mikasa because it is a
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uni-processor system.
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Arguments:
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Mask - Supplies the set of processors that are sent an interprocessor
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interrupt.
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Return Value:
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None.
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--*/
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{
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return;
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}
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