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219 lines
8.1 KiB
219 lines
8.1 KiB
/*++
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Copyright (c) 1993 Microsoft Corporation
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Copyright (c) 1994 Digital Equipment Corporation
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Module Name:
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pintolin.h
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Abstract:
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This file includes the platform-dependent Pin To Line Table
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for Mikasa.
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Author:
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Environment:
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Kernel mode
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Revision History:
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James Livingston (Digital) 10-May-1994
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Extracted Mikasa-specific table from the combined table
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of pin-to-line assignments.
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Janet Schneider (Digital) 27-July-1995
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Added support for the Noritake.
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--*/
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//
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// This table represents the mapping from slot number and interrupt pin
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// into a PCI Interrupt Vector.
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//
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// On platforms that use an interrupt register or registers instead of,
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// or in addition to cascaded 85c59s, the Interrupt Vector is one greater
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// than the Interrupt Request Register bit, because interrupt vectors
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// can't be zero, and bits in a register are numbered from zero. On
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// Mikasa, the Interrupt Vector also represents the Interrupt Mask
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// Register bit, since the arrangement of its bits is identical to
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// that of the Interrupt Read Register.
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//
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// Formally, these mappings can be expressed as:
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//
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// PCIPinToLine:
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// (SlotNumber.DeviceNumber, InterruptPin) -> InterruptLine
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//
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// LineToVector:
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// InterruptLine -> InterruptVector
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//
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// VectorToIRRBit:
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// InterruptVector -> InterruptRequestRegisterBit + 1
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//
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// VectorToIMRBit:
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// InterruptVector -> InterruptMaskRegisterBit + 1
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//
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// SlotNumberToIDSEL:
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// SlotNumber.DeviceNumber -> IDSEL
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//
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// subject to:
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//
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// Slot.DeviceNumber in {0,...,15}
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//
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// InterruptPin in {1, 2, 3, 4}
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//
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// InterruptRequestRegisterBit in {0,...,15}
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//
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// InterruptMaskRegisterBit in {0,...,15}
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//
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// PCIPinToLine(SlotNumber.DeviceNumber, InterruptPin) =
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// PCIPinToLineTable[SlotNumber.DeviceNumber, InterruptPin]
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// (Table for lookup function is initialized below)
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//
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// LineToVector(InterruptLine) = PCI_VECTORS + InterruptLine
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//
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// VectorToIRRBit(InterruptVector) = InterruptVector - 1
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//
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// VectorToIMRBit(InterruptVector) [see below]
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//
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// SlotNumberToIDSEL(SlotNumber.DeviceNumber) = (Slot.DeviceNumber + 11)
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//
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// where:
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//
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// SlotNumber.DeviceNumber:
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// Alpha AXP Platforms receive interrupts on local PCI buses only, which
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// are limited to 16 devices (PCI AD[11]-AD[26]).
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//
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// InterruptPin:
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// Each virtual slot has up to four interrupt pins INTA#, INTB#, INTC#,
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// INTD#, per the PCI Spec. V2.0, Section 2.2.6. Devices having one
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// interrupt use INTA#; only multifunction devices use INTB#, INTC#,
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// INTD#.)
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//
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// PCI configuration space indicates which interrupt pin a device will use
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// in the InterruptPin register, which can have the values:
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//
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// INTA# = 1, INTB# = 2, INTC# = 3, INTD# = 4
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//
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// Note that there may be up to 8 functions/device on a PCI multifunction
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// device plugged into the option slots. Each function has its own PCI
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// configuration space, addressed by the SlotNumber.FunctionNumber field,
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// and will identify which interrput pin of the four it will use in its
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// own InterruptPin register.
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//
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// If the option is a PCI-PCI bridge, interrupts from "downstream" PCI
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// slots must somehow be combined to appear on some combination of the
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// four interrupt pins belonging to the bridge's slot.
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//
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// InterruptLine:
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// This PCI Configuration register is maintained by software, and holds
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// an offset into PCI interrupt vectors. Whenever HalGetBusData or
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// HalGetBusDataByOffset is called, HalpPCIPinToLine() computes the
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// correct InterruptLine register value by using the mapping in
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// HalpPCIPinToLineTable.
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//
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// InterruptRequestRegisterBit:
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// In the table, 0xff is used to mark an invalid cell; this cell cannot
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// be used to produce an interrupt request register bit.
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//
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// InterruptMaskRegisterBit:
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// On Mikasa, the pin-to-line table may also be used to write the
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// InterruptMaskRegister, via
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//
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// VectorToIMRBit(InterrruptVector) = InterruptVector - 1
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//
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// IDSEL:
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// For accessing PCI configuration space on a local PCI bus (as opposed
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// to over a PCI-PCI bridge), type 0 configuration cycles must be generated.
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// In this case, the IDSEL pin of the device to be accessed is tied to one
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// of the PCI Address lines AD[11] - AD[26]. (The function field in the
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// PCI address is used, should we be accessing a multifunction device.)
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// Virtual slot 0 represents the device with IDSEL = AD[11], and so on.
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//
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//
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// Interrupt Vector Table Mapping for Mikasa.
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//
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// Mikasa PCI interrupts are mapped to interrupt vectors in the table
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// below. The values are a 1-1 map of the bit numbers in the Mikasa
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// PCI interrupt register that are connected to PCI devices.
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//
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// N.B.: there are two other interrupts in the Mikasa IRR/IMR, but they
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// are not connected to I/O devices, and have no associated PCI virtual
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// slot, so they're not represented in the table. Entries in the table
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// are interrupt vector values for the device having the given virtual
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// slot and pin number.
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//
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// Limit init table to 14 entries, which is the
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// MAX_PCI_LOCAL_DEVICES_MIKASA.
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//
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// We won't ever try to set an InterruptLine register of a slot
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// greater than Virtual slot 13 = PCI_AD[24].
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//
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PULONG HalpPCIPinToLineTable;
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ULONG MikasaPCIPinToLineTable[][4]=
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{
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// Pin 1 Pin 2 Pin 3 Pin 4
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// ----- ----- ----- -----
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 0 = PCI_AD[11]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 1 = PCI_AD[12]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 2 = PCI_AD[13]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 3 = PCI_AD[14]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 4 = PCI_AD[15]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 5 = PCI_AD[16]
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{ 0xd, 0xff, 0xff, 0xff }, // Virtual Slot 6 = PCI_AD[17] SCSI
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 7 = PCI_AD[18] ESC
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 8 = PCI_AD[19]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 9 = PCI_AD[20]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 10 = PCI_AD[21]
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{ 0x1, 0x2, 0x3, 0x4 }, // Virtual Slot 11 = PCI_AD[22] Slot #0
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{ 0x5, 0x6, 0x7, 0x8 }, // Virtual Slot 12 = PCI_AD[23] Slot #1
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{ 0x9, 0xa, 0xb, 0xc } // Virtual Slot 13 = PCI_AD[24] Slot #2
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};
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//
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// Limit init table to 14 entries, which is the MAX_PCI_LOCAL_DEVICES_MIKASA.
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// (It is same for Noritake.)
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//
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// We won't ever try to set an InterruptLine register of a slot
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// greater than Virtual slot 13 = PCI_AD[24] on bus 0.
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//
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// Noritake PCI interrupts will be no lower than 0x11 so that they are disjoint
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// from EISA levels.
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//
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ULONG NoritakePCIPinToLineTable0[][4]=
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{
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// Pin 1 Pin 2 Pin 3 Pin 4
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// ----- ----- ----- -----
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 0 = PCI_AD[11]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 1 = PCI_AD[12]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 2 = PCI_AD[13]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 3 = PCI_AD[14]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 4 = PCI_AD[15]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 5 = PCI_AD[16]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 6 = PCI_AD[17]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 7 = PCI_AD[18] PCEB
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 8 = PCI_AD[19] PCI-PCI Bridge
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 9 = PCI_AD[20]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 10 = PCI_AD[21]
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{ 0x13, 0x14, 0x23, 0x24 }, // Virtual Slot 11 = PCI_AD[22] Slot 0
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{ 0x15, 0x16, 0x25, 0x26 }, // Virtual Slot 12 = PCI_AD[23] Slot 1
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{ 0x17, 0x18, 0x27, 0x28 } // Virtual Slot 13 = PCI_AD[24] Slot 2
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};
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ULONG NoritakePCIPinToLineTable1[][4]=
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{
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// Pin 1 Pin 2 Pin 3 Pin 4
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// ----- ----- ----- -----
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{ 0x12, 0xff, 0xff, 0xff }, // Virtual Slot 0 = PCI_AD[16] QLogic
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{ 0x19, 0x1a, 0x29, 0x2a }, // Virtual Slot 1 = PCI_AD[17] Slot 3
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{ 0x1b, 0x1c, 0x2b, 0x2c }, // Virtual Slot 2 = PCI_AD[18] Slot 4
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{ 0x1d, 0x1e, 0x2d, 0x2e }, // Virtual Slot 3 = PCI_AD[19] Slot 5
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{ 0x1f, 0x20, 0x2f, 0x30 } // Virtual Slot 4 = PCI_AD[20] Slot 6
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};
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