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560 lines
14 KiB
560 lines
14 KiB
;/*
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;++
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;
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; Copyright (c) 1992 Intel Corporation
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; All rights reserved
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;
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; INTEL CORPORATION PROPRIETARY INFORMATION
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;
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; This software is supplied to Microsoft under the terms
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; of a license agreement with Intel Corporation and may not be
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; copied nor disclosed except in accordance with the terms
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; of that agreement.
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;
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;
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; Module Name:
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;
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; pcmp_nt.inc
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;
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; Abstract:
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;
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; include file for PC+MP system.
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;
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; WARNING: This file is included by both ASM and C files.
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;
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; Author:
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;
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; Ron Mosgrove (Intel) 30-July-1993
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;
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;--
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;
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if 0 ; Begin C only code */
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#include "pcmp.inc"
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//#define DEBUGGING 1
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#ifdef DEBUGGING
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extern CHAR Cbuf[];
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#endif
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//
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// To allow the user to specify command line options to the HAL.
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//
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#define USER_SETABLE_OPTIONS
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// #define BUILD_FOR_OLD_IDW
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//
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// Default BusType
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//
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#ifndef MCA
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#define DEFAULT_PC_BUS Eisa
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#else
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#define DEFAULT_PC_BUS MicroChannel
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#endif
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//
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// Well known virtual address of local processor apic
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//
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#define LOCALAPIC 0xfffe0000
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#define pLocalApic ((volatile PULONG) LOCALAPIC)
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//
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// Additional CpuFlags Bits used by NT in PC+MP Table
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//
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#define CPU_NT_STARTED 0x40 // CPU Has Been Started
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#define CPU_NT_RUNNING 0x80 // CPU is Runing NT
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#define MAX_PROCESSORS 8
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#define MAX_IOAPICS 8
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//
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// This OS specific structure holds useful MP information. This information
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// is obtained from the PC+MP table and stored here for convenience.
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//
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typedef struct HalpMpInfo {
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ULONG ApicVersion; // 82489Dx or Not
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ULONG ProcessorCount; // Number of Enabled Processors
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ULONG NtProcessors; // Number of Running Processors
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ULONG BusCount; // Number of buses in system
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ULONG IOApicCount; // Number of Io Apics in system
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ULONG IntiCount; // Number of Io Apic interrupt input entries
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ULONG LintiCount; // Number of Local Apic interrupt input entries
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ULONG IMCRPresent; // Indicates if the IMCR is present
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ULONG LocalApicBase; // Base of local APIC
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PULONG IoApicBase[MAX_IOAPICS]; // The virtual addresses of the IoApics
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ULONG IoApicPhys[MAX_IOAPICS]; // The physical addresses of the IoApics
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// only good during initialization...
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PPCMPPROCESSOR ProcessorEntryPtr; // Ptr to 1st PC+MP processor entry
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PPCMPBUS BusEntryPtr; // Ptr to 1st PC+MP bus entry
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PPCMPIOAPIC IoApicEntryPtr; // Ptr to 1st PC+MP IoApic entry
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PPCMPINTI IntiEntryPtr; // Ptr to 1st PC+MP Inti entry
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PPCMPLINTI LintiEntryPtr; // Ptr to 1st PC+MP Linti entry
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PMPS_EXTENTRY ExtensionTable; // Ptr to 1st extension table entry
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PMPS_EXTENTRY EndOfExtensionTable;
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} ;
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typedef struct {
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PUCHAR PcMpType;
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BOOLEAN PhysicalInstance;
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UCHAR Level;
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INTERFACE_TYPE NtType;
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PINSTALL_BUS_HANDLER NewInstance;
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BUS_DATA_TYPE NtConfig;
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ULONG BusExtensionSize;
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} PCMPBUSTRANS, *PPCMPBUSTRANS;
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#define CFG_MUST_BE 0x02
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#define CFG_ERROR 0x80
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#define CFG_HIGH 0x01
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#define CFG_LOW 0x00
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#define CFG_EDGE 0x00
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#define CFG_LEVEL 0x01
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#define CFG_MB_EDGE (CFG_MUST_BE | CFG_EDGE)
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#define CFG_MB_LEVEL (CFG_MUST_BE | CFG_LEVEL)
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#define CFG_ERR_EDGE (CFG_ERROR | CFG_EDGE)
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#define CFG_ERR_LEVEL (CFG_ERROR | CFG_LEVEL)
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#define CFG_ERR_MB_EDGE (CFG_ERROR | CFG_MUST_BE | CFG_EDGE)
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#define CFG_ERR_MB_LEVEL (CFG_ERROR | CFG_MUST_BE | CFG_LEVEL)
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#define CFG_TYPE(a) (a & 1)
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//
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// The kernel leaves some space (64 byte) of the PCR for the HAL to use
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// as it needs. Currently this space is used for some efficiency in
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// some of the MP specific code and is highly implementation-dependent.
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//
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typedef struct {
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UCHAR PCMPApicID;
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UCHAR na[3];
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} HALPRCB, *PHALPRCB;
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//
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// interrupt vector definitions for C
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//
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#define ZERO_VECTOR 0x00 // IRQL 00 placeholder
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#define APIC_SPURIOUS_VECTOR 0x1f // IRQL Spurious handler
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#define APC_VECTOR 0x3D // IRQL 01 APC
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#define DPC_VECTOR 0x41 // IRQL 02 DPC
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#define APIC_REBOOT_VECTOR 0x50 // IRQL Vector used to reboot
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#define APIC_GENERIC_VECTOR 0xC1 // IRQL 27 broadcast function call
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#define APIC_CLOCK_VECTOR 0xD1 // IRQL 28 APIC INTI0 - CLOCK2_LEVEL
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#define APIC_SYNCH_VECTOR 0xD1 // IRQL 28 IPI_LEVEL-1
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#define APIC_IPI_VECTOR 0xE1 // IRQL 29 APIC IPI
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#define APIC_FAULT_VECTOR 0xE3 //
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#define POWERFAIL_VECTOR 0xEF // IRQL 30 reserved. not used
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#define APIC_PROFILE_VECTOR 0xFD // IRQL 31
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#define APIC_PERF_VECTOR 0xFE // IRQL 31
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#define NMI_VECTOR 0xFF // IRQL 31
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//
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// 8259/ISP interrupt controller register addresses
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//
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#define PIC1_PORT0 0x20
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#define PIC1_PORT1 0x21
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#ifndef PIC2_PORT0
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#define PIC2_PORT0 0xA0
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#define PIC2_PORT1 0xA1
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#endif
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#define PIC_SLAVE_IRQ 2
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#define PIC1_ELCR_PORT 0x04D0 // ISP edge/level control registers
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#define PIC2_ELCR_PORT 0x04D1
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#define PIC1_SPURIOUS_VECTOR 0x37
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//
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// Defines for HalpFeatureBits
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//
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extern ULONG HalpFeatureBits;
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//
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//
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//
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ULONG FASTCALL HalpAcquireHighLevelLock(PKSPIN_LOCK);
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VOID FASTCALL HalpReleaseHighLevelLock(PKSPIN_LOCK, ULONG);
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extern KSPIN_LOCK HalpAccountingLock;
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extern KAFFINITY HalpActiveProcessors;
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//
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// Prototypes
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//
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BOOLEAN
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HalpGetPcMpInterruptDesc (
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IN INTERFACE_TYPE BusType,
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IN ULONG BusNumber,
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IN ULONG BusInterruptLevel,
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OUT PULONG PcMpInti
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);
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VOID
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HalpCheckELCR (
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VOID
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);
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VOID
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HalpSetInternalVector (
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IN ULONG InternalVector,
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IN VOID (*HalInterruptSerivceRoutine)(VOID)
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);
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VOID
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HalpGenericCall (
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VOID (*Fnc)(ULONG),
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ULONG Context,
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KAFFINITY Processors
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);
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VOID
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HalpPollForBroadcast (
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VOID
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);
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ULONG
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FASTCALL
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HalpWaitForPending (
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IN ULONG Count,
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IN volatile ULONG *LuICR
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);
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VOID
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HalpPerfInterrupt(
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VOID
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);
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VOID
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HalpEnablePerfInterupt (
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ULONG Context
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);
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VOID
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HalpEnableNMI (
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VOID
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);
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NTSTATUS
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HalpSetSystemInformation (
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IN HAL_SET_INFORMATION_CLASS InformationClass,
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IN ULONG BufferSize,
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IN PVOID Buffer
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);
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/*
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endif
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;
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; Begin assembly part of the definitions
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;
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include i386\pcmp.inc
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;
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; Well known virtual address of local processor apic
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;
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LOCALAPIC equ 0fffe0000h
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APIC equ ds:[LOCALAPIC]
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DEBUGGING equ 0
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if DEBUGGING
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IRQL_METRICS equ 0
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endif
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;
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; To allow the user to specify command line options to the HAL.
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;
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USER_SETABLE_OPTIONS equ 1
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;
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; This OS specific structure holds useful MP information. This information
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; is obtained from the PC+MP table and stored here for convenience.
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;
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HalpMpInfo struc
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ApicVersion dd 0 ; 82489Dx or Not
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ProcessorCount dd 0 ; Number of Enabled Processors
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NtProcessors dd 0 ; Number of Running Processors
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BusCount dd 0 ; Number of buses in system
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IOApicCount dd 0 ; Number of Io Apics in system
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IntiCount dd 0 ; Num of Io Apic interrupt inputs
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LintiCount dd 0 ; Num of Local Apic interrupt inputs
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IMCRPresent dd 0 ; Indicates if the IMCR is present
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LocalApicBase dd 0 ; Base of local apic
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IoApicBase dd 8 dup (0) ; The virtual addresses of the IoApics
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IoApicPhys dd 8 dup (0) ; The physical addresses of the IoApics
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ProcessorEntryPtr dd 0 ; Ptr to 1st PC+MP processor entry
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BusEntryPtr dd 0 ; Ptr to 1st PC+MP bus entry
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IoApicEntryPtr dd 0 ; Ptr to 1st PC+MP IoApic entry
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IntiEntryPtr dd 0 ; Ptr to 1st PC+MP Inti entry
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LintiEntryPtr dd 0 ; Ptr to 1st PC+MP Linti entry
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ExtensionTable dd 0 ; Ptr to 1st extension table entry
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EndExtensionTable dd 0 ; Ptr to 1st extension table entry
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HalpMpInfo ends
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;
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; interrupt vector definitions for assembler
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;
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ZERO_VECTOR equ 000h ; IRQL 00 placeholder
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APIC_SPURIOUS_VECTOR equ 01fh ; Vector used for spurious handler
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APC_VECTOR equ 03Dh ; IRQL 01 APC
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DPC_VECTOR equ 041h ; IRQL 02 DPC
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APIC_REBOOT_VECTOR equ 050h ; Vector used to reboot
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DEVICE_LEVEL1 equ 051h
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DEVICE_LEVEL2 equ 061h
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DEVICE_LEVEL3 equ 071h
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DEVICE_LEVEL4 equ 081h
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DEVICE_LEVEL5 equ 091h
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DEVICE_LEVEL6 equ 0A1h
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DEVICE_LEVEL7 equ 0B1h
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APIC_GENERIC_VECTOR equ 0C1h ; IRQL 27 broadcast function call
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APIC_CLOCK_VECTOR equ 0D1h ; IRQL 28 APIC INTI0 - CLOCK2_LEVEL
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APIC_SYNCH_VECTOR equ 0D1h ; IRQL 28 IPI_LEVEL-1
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APIC_IPI_VECTOR equ 0E1h ; IRQL 29 APIC IPI
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APIC_FAULT_VECTOR equ 0E3h ;
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POWERFAIL_VECTOR equ 0EFh ; IRQL 30 reserved
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APIC_PROFILE_VECTOR equ 0FDh ; IRQL 27
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APIC_PERF_VECTOR equ 0FEh ; IRQL 27
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NMI_VECTOR equ 0FFh ; IRQL 31
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HAL_PROFILE_LEVEL equ HIGH_LEVEL
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;
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; 8259/ISP interrupt controller register addresses
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;
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PIC1_PORT0 equ 020H
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PIC1_PORT1 equ 021H
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PIC2_PORT0 equ 0A0H
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PIC2_PORT1 equ 0A1H
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PIC1_ELCR_PORT equ 04D0H ; ISP edge/level control registers
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PIC2_ELCR_PORT equ 04D1H
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;
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; Initialization control words for the PICs
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;
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ICW1_ICW4_NEEDED equ 01H
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ICW1_CASCADE equ 00H
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ICW1_INTERVAL8 equ 00H
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ICW1_LEVEL_TRIG equ 08H
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ICW1_EDGE_TRIG equ 00H
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ICW1_ICW equ 10H
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ICW4_8086_MODE equ 001H
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ICW4_AUTO_EOI equ 002H
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ICW4_NORM_EOI equ 000H
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ICW4_NON_BUF_MODE equ 000H
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ICW4_SPEC_FULLY_NESTED equ 010H
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ICW4_NOT_SPEC_FULLY_NESTED equ 000H
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PIC_SLAVE_IRQ equ 2
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PIC1_BASE equ 30H
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PIC2_BASE equ 38H
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PIC_CLOCK_VECTOR equ 30H
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PIC_DMA_VECTOR equ 3DH
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PIC1_SPURIOUS_VECTOR equ 37H
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PIC2_SPURIOUS_VECTOR equ 3FH
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;
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; Operation control words for the PICs
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;
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OCW2_NON_SPECIFIC_EOI equ 020H
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OCW2_SPECIFIC_EOI equ 060H
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OCW3_READ_ISR equ 0BH
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OCW3_READ_IRR equ 0AH
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OCW3_READ_POLLED equ 0CH
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;
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; A couple of definitions that shouldn't change on a Compatible
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;
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TimerPicInti equ 0
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DmaPic2Inti equ 5
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SlavePicInti equ 2
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DmaPicInti equ 13 ; DMA input relative to 0
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cr equ 0ah
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lf equ 0dh
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;
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; The kernel leaves some space (64 byte) of the PCR for the HAL to use
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; as it needs. Currently this space is used for some efficiency in
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; some of the MP specific code and is highly implementation-dependent.
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;
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PcrE struc
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PcrNumber db 0 ; Processor's number
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ShortDpc db 0 ; Short circut dpc interrupt
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DpcPending db 0 ; Dpc interrupt pending
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db 0 ; force dword alignment
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;
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; The next three dwords are used to manipulate the APIC counter
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;
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ApicClockFreqHz dd 0 ; Counter Freq in Hertz
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ApicClockFreqKhz dd 0 ; Counter Freq in Khertz (rounded)
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ProfileCountDown dd 0 ; Current Countdown Interval
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TSCHz dd 0 ; Time stamp counter hertz low
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; PerfCounterLow dd 0 ; PerProcessor Counter
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; PerfCounterHigh dd 0 ;
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; ProfileCountLast dd 0
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PcrE ends
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PrcbE struc
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PrcbPCMPApicID db 0 ; Processor's PCMP ApicID
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db 3 dup (0) ; force dword alignment
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PrcbE ends
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MsrTSC equ 10h
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;++
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;
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; STALL_WHILE_APIC_BUSY
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;
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; Wait for the APIC DELIVERY_PENDING bit to be clear
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;
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;--
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STALL_WHILE_APIC_BUSY macro
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local a, b
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if 0
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push eax
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mov eax, 5000h
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a: test dword ptr APIC[LU_INT_CMD_LOW],DELIVERY_PENDING
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jz short b
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dec eax
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jnz short a
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int 3
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jmp short a
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b: pop eax
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else
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a: test dword ptr APIC[LU_INT_CMD_LOW],DELIVERY_PENDING
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jnz short a
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endif
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endm
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;++
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;
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; APICFIX
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;
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; Macro Description:
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;
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; For internal testing use
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;
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; Arguments:
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;
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; None
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;
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;--
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APICFIX macro reg1
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; inc dword ptr PCR[PcKernel] ; Count # of times patched
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endm
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;++
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;
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; CHECKTPR
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;
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; Macro Description:
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;
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; For internal testing use
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;
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; Arguments:
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;
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; None
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;
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;--
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CHECKTPR macro reg1, reg2
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if DBG
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cmp reg1, reg2
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je short @f
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int 3
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@@:
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endif
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endm
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;++
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;
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; IODELAY
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;
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; Macro Description:
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;
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; This macro delays the CPU just a little so the PIC has time to settle
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; between IO port accesses. Current mechanism is to read an APIC local
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; unit register (eax is saved). Note that PUSHF/POPF is worth 10 clocks.
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;
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; Arguments:
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;
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; None
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;
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;--
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IODELAY macro
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pushf
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popf
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jmp $+2
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endm
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;++
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;
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; SET_8259_MASK
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;
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; Macro Description:
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;
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; This macro sets the 8259 PIC interrupt mask register with the mask
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; passed from eax register. Bits 7:0 are the mask for the master PIC
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; and bits 15:8 are the mask for the slave PIC.
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;
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; Arguments:
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;
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; (eax) = mask for setting 8259 PIC interrupt mask register
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;
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;--
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SET_8259_MASK macro
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out PIC1_PORT1, al ; set master 8259 mask
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shr eax, 8 ; shift slave 8259 mask to al
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out PIC2_PORT1, al ; set slave 8259 mask
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endm
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;*/
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