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453 lines
13 KiB
453 lines
13 KiB
;
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; Copyright (c) 1992 NCR Corporation
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;
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; Module Name:
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;
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; ncr.inc
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;
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; Abstract:
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;
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; This module contains the equates for defining the system memory
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; map for NCR Multiprocessor systems using the Voyager architecture
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; (3450/3550)
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;
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; Author:
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;
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; Environment:
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;
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; Kernel mode only.
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;
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; Revision History:
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;
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;--
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;
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; Maximum number of processors include boot processor and non-boot processors
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NCR_MAX_NUMBER_PROCESSORS equ 16
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NCR_MAX_NUMBER_DYADIC_PROCESSORS equ 8
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NCR_MAX_NUMBER_QUAD_PROCESSORS equ 16
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;
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;
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NCR_CPI_VECTOR_BASE equ 60H
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NCR_QIC_CPI_VECTOR_BASE equ 70H
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NCR_SECONDARY_VECTOR_BASE equ 40H
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NCR_QIC_SPURIOUS_VECTOR equ 50H
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NCR_IPI_LEVEL_CPI equ 0 ; cpi used for ipi
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NCR_CLOCK_LEVEL_CPI equ 2 ; cpi used for clock broadcast
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NCR_SYSTEM_INTERRUPT equ 8 ; system interrupt
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NCR_SINGLE_BIT_ERROR equ 0FH ; single bit error
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NCR_STARTUP_CPI equ 2 ; cpi used to start nonboot procs
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NCR_STARTUP_VECTOR_VIC equ (NCR_STARTUP_CPI+NCR_CPI_VECTOR_BASE) * 4
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NCR_STARTUP_VECTOR_QIC equ (NCR_STARTUP_CPI+NCR_QIC_CPI_VECTOR_BASE) * 4
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;
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; CPU flags
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;
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CPU_DYADIC equ 01h
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CPU_QUAD equ 02h
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CPU_EXTENDED equ 04h
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;
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; Define Voyager Configuration and Test (CAT) register set
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;
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CAT_BASE_ADDRESS equ 0F800h ; configuration register base
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CAT_ID_SELECT_PORT equ 97h ; ASIC select register
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_CAT_REGISTERS struc
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cat_CatIdReg db ? ; Offset 0x00
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cat_AsicInformationReg db ? ; Offset 0x01
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cat_ControlReg db ? ; Offset 0x02
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cat_DataPort1 db ? ; Offset 0x03
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cat_ConfigurationReg db ? ; Offset 0x04
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cat_Reserved0 db ?
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cat_SubAddressRegLsb db ? ; Offset 0x06
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cat_SubAddressRegMsb db ? ; Offset 0x07
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cat_DataPort2 db ? ; Offset 0x08
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cat_DataPort3 db ? ; Offset 0x09
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cat_PDataRead db ? ; Offset 0x0a
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cat_Reserved1 db 3 dup(?)
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cat_JtagCommandReg db ? ; Offset 0x0e
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cat_StatusReg db ? ; Offset 0x0f
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_CAT_REGISTERS ends
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MCADDR_CAT_ID equ 0C0h
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CAT_READ macro reg
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mov dx, CAT_BASE_ADDRESS+cat_®
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in al, dx
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endm
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CAT_WRITE macro reg, dbyte
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ifnb <dbyte>
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mov al, dbyte
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endif
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mov dx, CAT_BASE_ADDRESS+cat_®
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out dx, al
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endm
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;++
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;
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; SET_IRQ_MASK
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;
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; Macro Description:
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;
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; This macro sets 8259 interrupt mask register with the mask
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; passed from eax register.
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;
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; Note: Currently, only two 8259s are support. As a result,
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; only ax contains valid mask.
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;
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; Arguments:
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;
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; (eax) = mask for setting 8259 interrupt mask register
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;
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;--
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QIC_IRQ_ENABLE_MASK equ 0fah ; Mask for enabling the disabling interrupts on Qic
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SET_IRQ_MASK macro
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local a,b,c ; define local labels
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;
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; Turn off P5 counters
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;
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; push eax
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; mov ecx,011h
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; db 0fh,32h
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; push eax
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; and eax,0fe3ffe3fh
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; mov edx,0
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; db 0fh,30h
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; pop eax
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;
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; mov edx, eax
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; pop eax
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; push edx
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mov edx, PCR[PcHal.PcrMyProcessorFlags]
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test edx, CPU_QUAD
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jnz short b
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out PIC1_PORT1, al ; set master 8259 mask
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shr eax, 8 ; shift slave 8259 mask to al
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out PIC2_PORT1, al ; set slave 8259 mask
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jmp short c
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b:
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test edx, CPU_EXTENDED
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jz short a
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out PIC1_PORT1, al ; set master 8259 mask
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ror eax,8 ; set slave pic mask
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out PIC2_PORT1, al ; set slave 8259 mask
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rol eax,8 ; restore eax for Qic operation
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a:
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or al,QIC_IRQ_ENABLE_MASK
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QIC_WRITE QicMask1
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c:
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;
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; Turn counters back on
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;
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; pop eax
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; mov ecx,011h
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; mov edx,0
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; db 0fh,30h
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;
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endm
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;
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; Define Voyager Interrupt Controller (VIC) register set
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;
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VIC_BASE_ADDRESS equ 0FC00h ; base address for VIC registers
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QIC_BASE_ADDRESS equ 0FC70h ; base address for QIC registers
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_VIC_REGISTERS struc
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vic_CpiLevel0Reg db ? ; Offset 0x00
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vic_CpiLevel1Reg db ? ; Offset 0x01
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vic_Reserved0 db 6 dup (?)
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vic_CpiLevel2Reg db ? ; Offset 0x08
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vic_CpiLevel3Reg db ? ; Offset 0x09
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vic_Reserved1 db 6 dup (?)
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vic_CpiLevel4Reg db ? ; Offset 0x10
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vic_CpiLevel5Reg db ? ; Offset 0x11
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vic_Reserved2 db 6 dup (?)
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vic_CpiLevel6Reg db ? ; Offset 0x18
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vic_CpiLevel7Reg db ? ; Offset 0x19
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vic_Reserved3 db 6 dup (?)
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vic_ActivityReg db ? ; Offset 0x20
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vic_ProcessorIdReg db ? ; Offset 0x21
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vic_Reserved4 db 6 dup (?)
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vic_ProcessorAliveReg db ? ; Offset 0x28
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vic_ProcessorWhoAmIReg db ? ; Offset 0x29
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vic_Reserved5 db 6 dup (?)
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vic_FakeInterruptRegLsb db ? ; Offset 0x30
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vic_FakeInterruptRegMsb db ? ; Offset 0x31
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vic_Reserved6 db 6 dup (?)
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vic_ClaimRegLsb db ? ; Offset 0x38
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vic_ClaimRegMsb db ? ; Offset 0x39
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vic_Reserved9 db 6 dup (?)
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vic_SpareInterruptReg db ? ; Offset 0x40
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vic_CpiVectorBaseReg db ? ; Offset 0x41
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vic_Reserved10 db 6 dup (?)
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vic_ExtMasterVectorBaseReg db ? ; Offset 0x48
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vic_ExtSlaveVectorBaseReg db ? ; Offset 0x49
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vic_Reserved11 db 6 dup (?)
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vic_AddressOffsetReg db ? ; Offset 0x50
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vic_ParityErrorReg db ? ; Offset 0x51
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vic_Reserved12 db 6 dup (?)
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vic_AsicConfigurationReg db ? ; Offset 0x58
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vic_RevisionLevelReg db ? ; Offset 0x59
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vic_Reserved13 db 6 dup (?)
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vic_RedirectIrqReg0 db ? ; Offset 0x60
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vic_RedirectIrqReg1 db ? ; Offset 0x61
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_VIC_REGISTERS ends
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_QIC_REGISTERS struc
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qic_Configuration db ? ; Offset 0x00
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qic_ProcessorId db ? ; Offset 0x01
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qic_ExtendedProcessorSelect db ? ; Offset 0x02
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qic_SpuriousVectorReg db ? ; Offset 0x03
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qic_Reserved1 db 4 dup (?)
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qic_PerformanceTimerVector db ? ; Offset 0x08
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qic_VicCpiVectorBaseReg db ? ; Offset 0x09
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qic_QuadCpiVectorBaseReg db ? ; Offset 0x0a
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qic_LocalMemoryErrorVectorReg db ? ; Offset 0x0b
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qic_Reserved2 db 4 dup (?)
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qic_QicMask0 db ? ; Offset 0x10
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qic_QicMask1 db ? ; Offset 0x11
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qic_QicIrrReg0 db ? ; Offset 0x12
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qic_QicIrrReg1 db ? ; Offset 0x13
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qic_Reserved3 db 4 dup (?)
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qic_ProcessorWhoAmIReg db ? ; Offset 0x18
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qic_Reserved4 db 1 dup (?)
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qic_Clear0Reg db ? ; Offset 0x1a
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qic_Clear1Reg db ? ; Offset 0x1b
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qic_Reserved5 db 4 dup (?)
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qic_PerformanceTimerInitialCount db ? ; Offset 0x20
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qic_PerformanceTimerCurrentCount db ? ; Offset 0x22
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qic_Reserved6 db 45 dup (?)
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qic_QuadCpi0StatusReg db ? ; Offset 0x50
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qic_Reserved7 db 7 dup (?)
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qic_QuadCpi1StatusReg db ? ; Offset 0x58
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qic_Reserved8 db 7 dup (?)
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qic_QuadCpi2StatusReg db ? ; Offset 0x60
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qic_Reserved9 db 7 dup (?)
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qic_QuadCpi3StatusReg db ? ; Offset 0x68
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qic_Reserved10 db 7 dup (?)
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qic_QuadCpi4StatusReg db ? ; Offset 0x70
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qic_Reserved11 db 7 dup (?)
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qic_QuadCpi5StatusReg db ? ; Offset 0x78
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qic_Reserved12 db 7 dup (?)
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qic_QuadCpi6StatusReg db ? ; Offset 0x80
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qic_Reserved13 db 7 dup (?)
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qic_QuadCpi7StatusReg db ? ; Offset 0x88
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_QIC_REGISTERS ends
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;
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; Processor Identification register definition
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;
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ProcessorIdNumber equ 07h
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ProcessorIdSelect equ 08h
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;
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; Cross Processor Interrupt Base Vector register definition
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;
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InterruptType equ 008h ; 0 = cpi, 1 = system int or
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CpiBaseVectorMask equ 0F0h ; single bit error
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;
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; Read/Write VIC macro definitions
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;
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VIC_READ macro reg
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mov dx, VIC_BASE_ADDRESS+vic_®
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in al, dx
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endm
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VIC_WRITE macro reg, dbyte
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ifnb <dbyte>
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mov al, dbyte
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endif
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mov dx, VIC_BASE_ADDRESS+vic_®
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out dx, al
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endm
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;
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; Read the who_am_i register. If this is a Dyadic then clear carry flag and return who_am_i
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; if this is a Quad then set carry flag and translate who_am_i
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;
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WHO_AM_I macro
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local a,b
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mov dx, VIC_BASE_ADDRESS+vic_ProcessorWhoAmIReg
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in al,dx
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movzx eax, al
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mov dl,al
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and edx,0c0h ; check for quad processor
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cmp edx,0c0h
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jne short a
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;
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; this is a Quad
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;
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mov dl,al
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and edx,0fh ; this must change for 32 way currently ccvv is left
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push ecx
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mov eax,1h
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mov ecx,edx
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shr ecx,2h ; get shift for processor bit
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shl eax,cl ; now put processor bit in right position
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mov ecx,edx ; now lets adjust for processor slot
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and ecx,3h ; now isolate voyager slot number
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shl ecx,2h ; 1 slot is 4 processors
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shl eax,cl ; now mask is corrent
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pop ecx
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stc
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jmp short b
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a:
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;
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; this is a Dyadic
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;
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push ebx
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push ecx
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stdCall _NCRTranslateCMOSMask, <eax>
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pop ecx
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pop ebx
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clc
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b:
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endm
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;
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; Translate the Processors logical mask into a VIC hardware mask for sending CPIs
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; to processors on Dyadic boards
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;
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TRANSLATE_LOGICAL_TO_VIC macro
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local loop,almost,done
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push ebx ; save registers
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xor ebx,ebx ; set logical processor number to zero
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dec ebx ; dec logical so we and inc right away
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xor edx,edx ; clear VIC mask
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align dword
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loop:
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inc ebx ; logical processor number
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shr eax,1 ; shift logical mask into carry
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jz short almost ; if logical mask zero we are almost done
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jnb short loop ; if this processor mask not set check next
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or edx,dword ptr _NCRLogicalNumberToPhysicalMask[ebx*4] ; or in the VIC mask for this processor
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jmp short loop
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almost:
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jnb short done ; if logical bit not set we are done
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or edx,dword ptr _NCRLogicalNumberToPhysicalMask[ebx*4] ; or in the VIC mask for this processor
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done:
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mov eax,edx ; put VIC mask into eax for return value
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pop ebx ; restore registers
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endm
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PROCESSOR_SLOT macro
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bsf eax,eax
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shr eax,2
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endm
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;
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; Read/Write QIC macro definitions
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;
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QIC_READ macro reg
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mov dx, QIC_BASE_ADDRESS+qic_®
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in al, dx
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endm
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QIC_WRITE macro reg, dbyte
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ifnb <dbyte>
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mov al, dbyte
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endif
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mov dx, QIC_BASE_ADDRESS+qic_®
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out dx, al
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endm
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;; Constants
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TRUE equ 1
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FALSE equ 0
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;
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; the kernel reserved space for us in our pcr. this structure defines
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; that space. it MUST coincide with the corresponding 'C' structure.
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;
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PcrE struc
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PcrMyProcessorFlags dd 0 ; Processor Flags that Indicate type of processor
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PcrMyLogicalMask dd 0 ; logical processor mask
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PcrMyLogicalNumber dd 0 ; logical processor number
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PcrMyPICsIrql dd 0 ; last Irql written to PICs
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PcrMyAcquireCount dd 0
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PcrMyLockColl dd 0
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PcrMySpinCount dd 0
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PcrMySpinTSCLowDWord dd 0
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PcrMySpinTSCHighDWord dd 0
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PcrMyHighestSpinCount dd 0
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PcrMyHighestLock dd 0
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PcrMyHighestAddress dd 0
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PcrMyClaimedIRQs dd 0
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PcrMyClaimedIRQsCount dd 0
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PcrE ends
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;
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; Values for NCRPlatform
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;
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NCR3450 equ 35333433H
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NCR3550 equ 30353834H
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NCR3360 equ 33333630H
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;
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; functions to turn on and off the performance counters
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;
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