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170 lines
3.5 KiB
170 lines
3.5 KiB
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/*++
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Copyright (c) 1992 NCR - MSBU
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Module Name:
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ncrhwsup.c
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Abstract:
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Author:
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Richard Barton (o-richb) 11-Mar-1992
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Environment:
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Kernel mode only.
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Revision History:
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--*/
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#include "halp.h"
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#include "ncr.h"
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#include "ncrcat.h"
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#include "ncrpsi.h"
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extern ULONG NCRActiveProcessorCount;
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ULONG NCRSysIntCount;
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ULONG NCRSingleBitCount;
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ULONG NCRLockedExchangeAndAdd(PULONG, ULONG);
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VOID
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NCRHandleSysInt (TrapFramePtr, ExceptionRecordPtr)
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IN PKTRAP_FRAME TrapFramePtr;
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IN PVOID ExceptionRecordPtr;
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/*++
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Routine Description:
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Handles the NCR hardware generated System Interrupt
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Arguments:
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Return Value:
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none.
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--*/
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{
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DbgBreakPoint();
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return ;
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#if 0
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ULONG i;
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i = NCRLockedExchangeAndAdd(&NCRSysIntCount, 1);
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if (i != 0) {
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for (i = 100000;
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((NCRSysIntCount != NCRActiveProcessorCount) &&
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(i > 0)); --i) ;
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KiIpiServiceRoutine(TrapFramePtr, ExceptionRecordPtr);
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return;
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}
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DbgPrint("NCRHandleSysInt");
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DbgBreakPoint();
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NCRSysIntCount = 0;
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#endif
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}
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VOID
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NCRHandleSingleBitError (TrapFramePtr, ExceptionRecordPtr)
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IN PKTRAP_FRAME TrapFramePtr;
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IN PVOID ExceptionRecordPtr;
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/*++
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Routine Description:
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Handles the NCR hardware generated Single Bit Error Interrupt and a
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Status Change
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Arguments:
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Return Value:
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none.
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--*/
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{
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CAT_CONTROL cat_control;
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PSI_INFORMATION psi_information;
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cat_control.Module = PSI;
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cat_control.Asic = CAT_I;
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//
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// Lets get the CatBus spin lock because the status change interrupt is a broadcast
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// interrupt that goes to all CPU's
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//
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HalpAcquireCatBusSpinLock();
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//
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// read status registers from PSI. This will tell us if a status change interrupt occured.
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//
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cat_control.Command = READ_REGISTER;
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cat_control.Address = 0;
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cat_control.NumberOfBytes = sizeof(CAT_REGISTERS);
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HalpCatBusIo(&cat_control,(PUCHAR)&(psi_information.CatRegisters.CatRegs));
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if (psi_information.INTERRUPT_STATUS) {
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//
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// A status change interrupt has occured. Lets go read detailed status information so
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// the interrupt will be cleared.
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//
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//
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// read power supply mask registers
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//
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cat_control.Command = READ_SUBADDR;
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cat_control.Address = PSI_Pwr_Supply_Status_L5;
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cat_control.NumberOfBytes = 8;
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HalpCatBusIo(&cat_control,(PUCHAR)&(psi_information.PowerSupplyStatus));
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//
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// read disk power registers
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//
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cat_control.Command = READ_SUBADDR;
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cat_control.Address = PSI_DiskStatus_L5;
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cat_control.NumberOfBytes = 16;
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HalpCatBusIo(&cat_control,(PUCHAR)&(psi_information.DiskPowerStatus[0]));
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//
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// read DVM registers
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//
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cat_control.Command = READ_SUBADDR;
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cat_control.Address = PSI_Dvm_Select_L5;
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cat_control.NumberOfBytes = 1;
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HalpCatBusIo(&cat_control,(PUCHAR)&(psi_information.DvmSelect));
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cat_control.Command = READ_SUBADDR;
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cat_control.Address = DVM_DBASE;
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cat_control.NumberOfBytes = 4;
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HalpCatBusIo(&cat_control,(PUCHAR)&(psi_information.DvmData0));
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} else {
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//
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// This path means another CPU has handled the status change.
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//
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// NOTE: If single bit error reporting were enabled then this path could also
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// mean a single bit error occured.
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//
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}
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//
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// Release the CatBus spin lock.
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//
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HalpReleaseCatBusSpinLock();
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if (psi_information.INTERRUPT_STATUS) {
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DBGMSG(("A Status Change Interrupt was received: 0x%x\n",psi_information.INTERRUPT_STATUS));
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}
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}
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