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448 lines
8.4 KiB
448 lines
8.4 KiB
/*++
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Copyright (c) 1990 Microsoft Corporation
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Copyright (c) 1992, 1993 Digital Equipment Corporation
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Module Name:
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ebintsup.c
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Abstract:
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The module provides the interrupt support Noname SBC system.
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Author:
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Robin Alexander (DEC) 13-June-1994
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Modified from existing Avanti code.
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Revision History:
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--*/
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#include "halp.h"
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#include "eisa.h"
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#include "ebsgdma.h"
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#include "nondef.h"
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#include "pcrtc.h"
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#include "pintolin.h"
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//
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// Declare the interrupt handler for the PCI and ISA bus.
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//
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BOOLEAN
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HalpSioDispatch(
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VOID
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);
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//
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// The following is the interrupt object used for DMA controller interrupts.
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// DMA controller interrupts occur when a memory parity error occurs or a
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// programming error occurs to the DMA controller.
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//
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KINTERRUPT HalpEisaNmiInterrupt;
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//
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// The following function initializes NMI handling.
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//
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VOID
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HalpInitializeNMI(
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VOID
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);
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//
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// The following function is called when an ISA NMI occurs.
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//
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BOOLEAN
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HalHandleNMI(
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IN PKINTERRUPT Interrupt,
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IN PVOID ServiceContext
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);
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BOOLEAN
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HalpInitializePCIInterrupts (
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VOID
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)
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/*++
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Routine Description:
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This routine initializes the structures necessary for EISA & PCI operations
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and connects the intermediate interrupt dispatcher. It also initializes the
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ISA interrupt controller; in the case of the SIO-II in Noname, the
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integral interrupt controller is compatible with the EISA interrupt
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contoller used on Jensen.
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Arguments:
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None.
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Return Value:
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If the second level interrupt dispatcher is connected, then a value of
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TRUE is returned. Otherwise, a value of FALSE is returned.
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--*/
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{
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ULONG PciIsaBridgeHeaderOffset;
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KIRQL oldIrql;
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//
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// Initialize the EISA NMI interrupt.
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//
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HalpInitializeNMI();
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//
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// Directly connect the ISA interrupt dispatcher to the level for
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// ISA bus interrupt.
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//
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// N.B. This vector is reserved for exclusive use by the HAL (see
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// interrupt initialization.
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//
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PCR->InterruptRoutine[PIC_VECTOR] = HalpSioDispatch;
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HalEnableSystemInterrupt(PIC_VECTOR, ISA_DEVICE_LEVEL, LevelSensitive);
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(PVOID) HalpPCIPinToLineTable = (PVOID) NonamePCIPinToLineTable;
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//
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// Intitialize interrupt controller
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//
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KeRaiseIrql(ISA_DEVICE_LEVEL, &oldIrql);
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//
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// We must declare the right form for the APECS PCI/ISA bridge
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// configuration space device selector for use in the initialization
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// of the interrupts.
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//
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PciIsaBridgeHeaderOffset = PCI_ISA_BRIDGE_HEADER_OFFSET;
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//
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// Setup the Noname interrupt assignments for the C-Step SIO; this
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// is done with registers that are internal to the SIO-II, PIRQ0,
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// PIRQ1, PIRQ2, and PIRQ3. They're at offsets 0x60, 0x61, 0x62,
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// and 0x63 of the SIO-II's configuration registers. The effect
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// of these registers is to steer the PCI interrupts into the IRQx
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// inputs of the SIO's internal cascaded 82C59 interrupt controllers.
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// These controllers are then programmed in their usual fashion.
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//
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// Set up interrupts from PCI slots 0, 1, and 2, compatible with
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// Noname pass 1 MLB, i.e., steer the interrupt from each PCI
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// slot or device into the default IRQL from pass 1 Noname; enable
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// the routings.
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//
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WRITE_CONFIG_UCHAR((PCHAR)(PCI_CONFIGURATION_BASE_QVA
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| PciIsaBridgeHeaderOffset | PIRQ0_ROUTE_CONTROL),
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PIRQX_ROUTE_IRQ10 | PIRQX_ROUTE_ENABLE,
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PCI_CONFIG_CYCLE_TYPE_0);
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WRITE_CONFIG_UCHAR((PCHAR)(PCI_CONFIGURATION_BASE_QVA
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| PciIsaBridgeHeaderOffset | PIRQ1_ROUTE_CONTROL),
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PIRQX_ROUTE_IRQ15 | PIRQX_ROUTE_ENABLE,
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PCI_CONFIG_CYCLE_TYPE_0);
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WRITE_CONFIG_UCHAR((PCHAR)(PCI_CONFIGURATION_BASE_QVA
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| PciIsaBridgeHeaderOffset | PIRQ2_ROUTE_CONTROL),
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PIRQX_ROUTE_IRQ9 | PIRQX_ROUTE_ENABLE,
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PCI_CONFIG_CYCLE_TYPE_0);
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//
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// Set up interrupt from SCSI (IRQ11), and enable the routing.
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//
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WRITE_CONFIG_UCHAR((PCHAR)(PCI_CONFIGURATION_BASE_QVA
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| PciIsaBridgeHeaderOffset | PIRQ3_ROUTE_CONTROL),
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PIRQX_ROUTE_IRQ11 | PIRQX_ROUTE_ENABLE,
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PCI_CONFIG_CYCLE_TYPE_0);
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//
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// Select "level" operation for PCI PIRQx interrupt lines, and
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// "edge" for ISA devices, e.g., mouse at IRQL12. Default is "edge"
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// so no mention means "edge".
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//
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WRITE_REGISTER_UCHAR((PCHAR)(PCI_SPARSE_IO_BASE_QVA
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| SIO_II_EDGE_LEVEL_CONTROL_2),
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IRQ11_LEVEL_SENSITIVE | IRQ10_LEVEL_SENSITIVE |
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IRQ9_LEVEL_SENSITIVE | IRQ15_LEVEL_SENSITIVE);
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HalpInitializeSioInterrupts();
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//
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// Restore IRQL level.
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//
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KeLowerIrql(oldIrql);
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//
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// Initialize the DMA mode registers to a default value.
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// Disable all of the DMA channels except channel 4 which is the
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// cascade of channels 0-3.
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//
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Dma1BasePort.AllMask,
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0x0F
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);
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Dma2BasePort.AllMask,
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0x0E
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);
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return(TRUE);
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}
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VOID
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HalpInitializeNMI(
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VOID
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)
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/*++
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Routine Description:
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This function is called to intialize SIO NMI interrupts.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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UCHAR DataByte;
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//
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// Initialize the SIO NMI interrupt.
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//
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KeInitializeInterrupt( &HalpEisaNmiInterrupt,
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HalHandleNMI,
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NULL,
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NULL,
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EISA_NMI_VECTOR,
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EISA_NMI_LEVEL,
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EISA_NMI_LEVEL,
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LevelSensitive,
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FALSE,
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0,
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FALSE
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);
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//
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// Don't fail if the interrupt cannot be connected.
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//
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KeConnectInterrupt( &HalpEisaNmiInterrupt );
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//
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// Clear the Eisa NMI disable bit. This bit is the high order of the
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// NMI enable register.
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//
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DataByte = 0;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->NmiEnable,
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DataByte
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);
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}
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BOOLEAN
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HalHandleNMI(
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IN PKINTERRUPT Interrupt,
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IN PVOID ServiceContext
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)
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/*++
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Routine Description:
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This function is called when an EISA NMI occurs. It print the appropriate
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status information and bugchecks.
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Arguments:
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Interrupt - Supplies a pointer to the interrupt object
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ServiceContext - Bug number to call bugcheck with.
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Return Value:
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Returns TRUE.
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--*/
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{
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UCHAR StatusByte;
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StatusByte =
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READ_PORT_UCHAR(&((PEISA_CONTROL) HalpEisaControlBase)->NmiStatus);
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if (StatusByte & 0x80) {
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HalDisplayString ("NMI: Parity Check / Parity Error\n");
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}
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if (StatusByte & 0x40) {
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HalDisplayString ("NMI: Channel Check / IOCHK\n");
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}
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//
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// This is an Sio machine, no extnded nmi information, so just do it.
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//
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KeBugCheck(NMI_HARDWARE_FAILURE);
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return(TRUE);
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}
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UCHAR
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HalpAcknowledgeEisaInterrupt(
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PVOID ServiceContext
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)
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/*++
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Routine Description:
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Acknowledge the EISA interrupt from the programmable interrupt controller.
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Return the vector number of the highest priority pending interrupt.
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Arguments:
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ServiceContext - Service context of the interrupt service supplies
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a pointer to the EISA interrupt acknowledge register.
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Return Value:
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Return the value of the highest priority pending interrupt.
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--*/
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{
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UCHAR InterruptVector;
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//
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// Read the interrupt vector from the PIC.
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//
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InterruptVector = READ_PORT_UCHAR(ServiceContext);
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return( InterruptVector );
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}
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VOID
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HalpAcknowledgeClockInterrupt(
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VOID
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)
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/*++
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Routine Description:
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Acknowledge the clock interrupt from the interval timer. The interval
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timer for EB66 comes from the Dallas real-time clock.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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//
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// Acknowledge the clock interrupt by reading the control register C of
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// the Real Time Clock.
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//
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HalpReadClockRegister( RTC_CONTROL_REGISTERC );
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return;
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}
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