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393 lines
18 KiB
393 lines
18 KiB
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#ifndef _FALCONREG_
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#define _FALCONREG_
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#include <faldef.h>
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/////////////////////////////////////////////////////////////////////////////
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// //
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// //
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// Define Register bit definitions //
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// //
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// //
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/////////////////////////////////////////////////////////////////////////////
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//
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// Global Status register bit definitions
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//
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// Global status MC bit (0 = 64 bits, 1 = 128 bits)
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//
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#define GLOBAL_STATUS_MC REPLICATE_16(0x0001) // defines memory configuration
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#define GLOBAL_STATUS_MP REPLICATE_16(0x0002) // 2nd processor present (Processor B)
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#define GLOBAL_STATUS_ECP REPLICATE_16(0x0004) // external cache present
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#define GLOBAL_STATUS_MASK REPLICATE_16(0x0007) // Global Status register bit mask
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#define GLOBAL_STATUS_REV_MASK REPLICATE_16(0xFF00) // revision id field
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#define GLOBAL_STATUS_REVID_0 REPLICATE_16(0x0000) // revision id for 1.0 chip
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#define GLOBAL_STATUS_REVID_2 REPLICATE_16(0x0200) // revision id for 2.0 chip
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#define GLOBAL_STATUS_REVID_3 REPLICATE_16(0x0300) // revision id for 3.0 chip
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//
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// Global Ctrl register bit definitions
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//
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#define GLOBAL_CTRL_BMA REPLICATE_16(0x0001) // BootMode Processor A
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#define GLOBAL_CTRL_BMB REPLICATE_16(0x0002) // BootMode Processor B
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#define GLOBAL_CTRL_PCR REPLICATE_16(0x0004) // PCI EISA/ISA bus device reset
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#define GLOBAL_CTRL_PBE REPLICATE_16(0x0008) // Release Processor B, full sys access
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#define GLOBAL_CTRL_PWC0 REPLICATE_16(0x0000) // PCI write coherency control - none
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// No hardware I/O consistancy
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#define GLOBAL_CTRL_PWC1 REPLICATE_16(0x0010) // R4K caches inv on all PCI write
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// transactions from devs on PCI bus
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#define GLOBAL_CTRL_PWC2 REPLICATE_16(0x0020) // R4k caches inv on all PCI write & inv
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// transactions from devs on PCI bus
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#define GLOBAL_CTRL_PRI REPLICATE_16(0x0040) // PCI read & invalidate command
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#define GLOBAL_CTRL_ECE REPLICATE_16(0x0080) // External cache enable
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#define GLOBAL_CTRL_ECL REPLICATE_16(0x0300) // External Cache Line Size (see R4x00 config reg)
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#define GLOBAL_CTRL_ECL1 REPLICATE_16(0x0100) // E-Cache 32 byte line size
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#define GLOBAL_CTRL_ECL2 REPLICATE_16(0x0200) // E-Cache 64 byte line size
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#define GLOBAL_CTRL_SRE REPLICATE_16(0x0400) // Slow memory read enable
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#define GLOBAL_CTRL_SME REPLICATE_16(0x0800) // Slow miss enable
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#define GLOBAL_CTRL_MASK REPLICATE_16(0x00ff) // Global Ctrl bit mask
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#define GLOBAL_CTRL_MASK_PMP_V2 REPLICATE_16(0x03ff) // Global Ctrl bit mask
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//
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// WhoAmi register bit definitions
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//
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#define WHOAMI_PROC_A REPLICATE_16(0x0000) // Processor A initiates read
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#define WHOAMI_PROC_B REPLICATE_16(0x0001) // Processor B initiates read
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#define WHOAMI_REG_MASK WHOAMI_PROC_B // WhoAmI register bit mask
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//
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// PCI Status register bit definitions
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//
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#define PCI_STATUS_ME REPLICATE_16(0x0001) // PCI detected multiple errors
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#define PCI_STATUS_RSE REPLICATE_16(0x0002) // Recvd system error from PCI bus
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#define PCI_STATUS_RER REPLICATE_16(0x0004) // Recvd excess # of retries
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#define PCI_STATUS_IAE REPLICATE_16(0x0008) // Access error
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#define PCI_STATUS_MPE REPLICATE_16(0x0010) // Master parity error
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#define PCI_STATUS_RTA REPLICATE_16(0x0020) // Recvd target abort
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#define PCI_STATUS_RMA REPLICATE_16(0x0040) // Recvd master abort
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#define PCI_STATUS_CFG REPLICATE_16(0x0080) // Config write to PMP occurred
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#define PCI_STATUS_FER REPLICATE_16(0x0100) // Error occurred on first word of read
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#define PCI_STATUS_RW REPLICATE_16(0x0200) // R/W bit (0 = Write, 1 = Read)
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#define PCI_STATUS_CMD REPLICATE_16(0x1E00) // Pci command field
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#define PCI_STATUS_MASK REPLICATE_16(0x1fff) // PCI Status register bit mask
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#define PCI_STATUS_CMD_PMP_V2 REPLICATE_16(0x3C00) // Pci command field
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#define PCI_STATUS_MASK_PMP_V2 REPLICATE_16(0x3fff) // PCI Status register bit mask
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//
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// PCI Ctrl register bit definitions
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//
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#define PCI_CTRL_RPS0 REPLICATE_16(0x0000) // PCI read prefetch size = 8/16 bytes
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#define PCI_CTRL_RPS1 REPLICATE_16(0x0001) // PCI read prefetch size = 16/32 bytes
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#define PCI_CTRL_RPS2 REPLICATE_16(0x0002) // PCI read prefetch size = 24/48 bytes
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#define PCI_CTRL_RPS3 REPLICATE_16(0x0003) // PCI read prefetch size = 32/64 bytes
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#define PCI_CTRL_MSO REPLICATE_16(0x0004) // Set, adds 0x40000000 to sys mem addrs
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#define PCI_CTRL_FBP REPLICATE_16(0x0008) // Force bad parity on PCI bus
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#define PCI_CTRL_RAP REPLICATE_16(0x0010) // Report all parity errors on bus
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#define PCI_CTRL_ELR REPLICATE_16(0x0020) // Read/Write burst control
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#define PCI_CTRL_MASK REPLICATE_16(0x001f) // PCI Ctrl register bit mask
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#define PCI_CTRL_MASK_PMP_V2 REPLICATE_16(0x003f) // PCI Ctrl register bit mask
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//
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// PCI Err Ack register bit definitions
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//
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#define PCI_ERR_ACK_MASK PCI_STATUS_MASK // PCI err ack bit mask
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//
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// PCI Err Addr register bit definitions
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//
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#define PCI_ERR_ADDR_MASK_PMP_V2 0xffffffff // PCI err addr bit mask
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#define PCI_ERR_ADDR_RW_PMP_V2 0x00000000 // PCI err addr rw bit (!!removed!!)
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#define PCI_ERR_ADDR_RW 0x80000000 // PCI err addr rw bit
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#define PCI_ERR_ADDR_MASK 0x7fffffff // PCI err addr bit mask
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//
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// PCI Retry register bit definitions
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//
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#define PCI_RETRY_COUNT REPLICATE_16(0x00ff) // PCI retry count field
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#define PCI_RETRY_MASK REPLICATE_16(0x00ff) // PCI retry count bit mask
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//
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// PCI Space Map register bit definitions
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//
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#define PCI_SPACE_MAP_NIB0 REPLICATE_16(0x000f) // PCI bus addrs bit 28 is = 0
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#define PCI_SPACE_MAP_NIB1 REPLICATE_16(0x00f0) // PCI bus addrs bit 28 is = 1
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#define PCI_SPACE_MAP_MASK REPLICATE_16(0x00ff) // PCI Space Map bit mask
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//
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// PCI Config Addr register bit definitions
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//
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#define PCI_CONFIG_ADDR_TYPE0 0x00000000 // PCI local bus access
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#define PCI_CONFIG_ADDR_TYPE1 0x00000001 // PCI remote bus access
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#define PCI_CONFIG_ADDR_FUNCNUM 0x00000700 // PCI remote bus config mask
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#define PCI_CONFIG_ADDR_REMDEVNUM 0x0000f800 // PCI remote bus dev mask
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#define PCI_CONFIG_ADDR_REMBUSNUM 0x00ff0000 // PCI remote bus target mask
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#define PCI_CONFIG_ADDR_MASK 0x00ffff01 // PCI remote bus access
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//
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// PCI Config Select register bit definitions
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//
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#define PCI_CONFIG_DIS_ISA 0x00 // PCI-ISA disable configuration access
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#define PCI_CONFIG_SEL_ISA 0x01 // PCI-ISA select configuration access
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#define PCI_CONFIG_SEL_ENET 0x02 // PCI-ENET select configuration access
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#define PCI_CONFIG_SEL_SCSI 0x04 // PCI-SCSI select configuration access
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#define PCI_CONFIG_SEL_VID 0x08 // PCI-VID select configuration access
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#define PCI_CONFIG_SEL_SLOT0 0x10 // PCI-SLOT0 select configuration access
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#define PCI_CONFIG_SEL_SLOT1 0x20 // PCI-SLOT1 select configuration access
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#define PCI_CONFIG_SEL_SLOT2 0x40 // PCI-SLOT2 select configuration access
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#define PCI_CONFIG_SEL_PROC 0x80 // PCI-PROC select configuration access
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#define PCI_CONFIG_SEL_MASK 0xff // PCI select configuration access mask
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//
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// PCI Other Addr register bit definitions
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//
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#define PCI_OTHER_ADDR_MASK 0x00000000 // PCI Other Addr bit mask
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//
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// PCI Special register bit definitions
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//
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#define PCI_SPECIAL_MASK 0xffffffff // PCI Special bit mask
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//
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// MEM Status register bit definitions
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//
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#define MEM_STATUS_EUE 0x00000001 // UnCorrectable err on even hw memory
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#define MEM_STATUS_ECE 0x00000004 // Correctable err on even hw memory
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#define MEM_STATUS_OUE 0x00010000 // UnCorrectable err on odd hw memory
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#define MEM_STATUS_OCE 0x00040000 // Correctable err on odd hw memory
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#define MEM_STATUS_MUE REPLICATE_16(0x0002) // Multiple UnCorrectable errors
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#define MEM_STATUS_MCE REPLICATE_16(0x0008) // Multiple Correctable errors
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#define MEM_STATUS_FER REPLICATE_16(0x0010) // Error occurred on first word of read
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#define MEM_STATUS_ESYN 0x0000ff00 // Even HalfWord error Syndrome
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#define MEM_STATUS_OSYN 0xff000000 // ODD HalfWord error Syndrome
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#define MEM_STATUS_MASK REPLICATE_16(0xff1f) // Mem status register Mask
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//
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// MEM Ctrl register bit definitions
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//
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#define MEM_CTRL_CHKSEL0 REPLICATE_16(0x0000) // Diagnostic Mode
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#define MEM_CTRL_CHKSEL1 REPLICATE_16(0x0001) // ECC enable Mode
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#define MEM_CTRL_RCE REPLICATE_16(0x0004) // Report Correctable errors
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#define MEM_CTRL_RRC REPLICATE_16(0x0008) // Reset refresh counter
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#define MEM_CTRL_RD0 REPLICATE_16(0x0010) // Refresh disable sys addrs REPLICATE_16(0x00000000
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// & sys addrs 0x40000000
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#define MEM_CTRL_RD1 REPLICATE_16(0x0020) // Refresh disable sys addrs 0x10000000
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// & sys addrs 0x50000000
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#define MEM_CTRL_RD2 REPLICATE_16(0x0040) // Refresh disable sys addrs 0x20000000
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// & sys addrs 0x60000000
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#define MEM_CTRL_RD3 REPLICATE_16(0x0080) // Refresh disable sys addrs 0x30000000
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// & sys addrs 0x70000000
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#define MEM_CTRL_MASK REPLICATE_16(0x00ff) // Mem Control register mask
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//
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// MEM Err Ack register bit definitions
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//
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#define MEM_ERR_ACK_MASK MEM_STATUS_MASK // MEM err ack bit mask
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//
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// MEM Error Addr register bit definitions
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//
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#define MEM_ERR_ADDR_SRC 0x00000001 // Source of failed memory access
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#define MEM_ERR_ADDR_RW 0x80000000 // Access type failure
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#define MEM_ERR_ADDR_MASK 0x7ffffff8 // Sys address of last memory failure
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//
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// MEM Count register bit definitions
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//
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// XXX Check these with David B.
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#define MEM_COUNT_MASK 0xffffffff // MEM count bit mask
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#define MEM_COUNT_44MHZ_VALUE REPLICATE_16(0x02B0) // Memory refresh for 44MHz proc
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#define MEM_COUNT_50MHZ_VALUE REPLICATE_16(0x030D) // Memory refresh for 50MHz proc
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#define MEM_COUNT_67MHZ_VALUE REPLICATE_16(0x0411) // Memory refresh for 67MHz proc
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//
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// MEM Timing register bit definitions
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//
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#define MEM_TIMING_EDO REPLICATE_16(0x0001) // EDO Memory mode
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#define MEM_TIMING_RCW0 REPLICATE_16(0x0000) // Read CAS width of 3 Cycles
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#define MEM_TIMING_RCW1 REPLICATE_16(0x0002) // Read CAS width of 2 Cycles
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#define MEM_TIMING_RCW2 REPLICATE_16(0x0004) // Read CAS width of 1 Cycles
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#define MEM_TIMING_RCW3 REPLICATE_16(0x0006) // Illegal Read CAS width
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#define MEM_TIMING_WCW0 REPLICATE_16(0x0000) // Write CAS width of 3 Cycles
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#define MEM_TIMING_WCW1 REPLICATE_16(0x0008) // Write CAS width of 2 Cycles
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#define MEM_TIMING_WCW2 REPLICATE_16(0x0010) // Write CAS width of 1 Cycles
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#define MEM_TIMING_WCW3 REPLICATE_16(0x0018) // Illegal Write CAS width
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#define MEM_TIMING_RCA0 REPLICATE_16(0x0000) // RAS to column addrs duration 2 cycles
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#define MEM_TIMING_RCA1 REPLICATE_16(0x0020) // RAS to column addrs duration 1 cycle
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#define MEM_TIMING_RP0 REPLICATE_16(0x0000) // RAS precharge duration width 5 cycles
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#define MEM_TIMING_RP1 REPLICATE_16(0x0040) // RAS precharge duration width 4 cycles
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#define MEM_TIMING_RP2 REPLICATE_16(0x0080) // RAS precharge duration width 3 cycles
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#define MEM_TIMING_RP3 REPLICATE_16(0x00c0) // RAS precharge duration width 2 cycles
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#define MEM_TIMING_RAS0 REPLICATE_16(0x0000) // RAS refresh width x cycles
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#define MEM_TIMING_RAS1 REPLICATE_16(0x0100) // RAS refresh width x cycles
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#define MEM_TIMING_RAS2 REPLICATE_16(0x0200) // RAS refresh width x cycles
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#define MEM_TIMING_RAS3 REPLICATE_16(0x0300) // RAS refresh width x cycles
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#define MEM_TIMING_PEN REPLICATE_16(0x0400) // Parity SIMM Enable
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#define MEM_TIMING_MASK REPLICATE_16(0x07ff) // MEM Timing register bit mask
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//
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// MEM Diag register bit definitions
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//
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#define MEM_DIAG_EVENCHK 0x0000ff00 // Even check bits written to memory
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#define MEM_DIAG_ODDCHK 0xff000000 // Odd check bits written to memory
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#define MEM_DIAG_MASK REPLICATE_16(0xff00) // MEM Diag register bit mask
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//
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// INT Status register bit definitions
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//
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#define INT_STATUS_IOA REPLICATE_16(0x0001) // IO int pending for Processor A
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#define INT_STATUS_IOB REPLICATE_16(0x0002) // IO int pending for Processor B
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#define INT_STATUS_MA REPLICATE_16(0x0004) // Mem int pending for Processor A
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#define INT_STATUS_MB REPLICATE_16(0x0008) // Mem int pending for Processor B
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#define INT_STATUS_MNI REPLICATE_16(0x0010) // NMI int (from Mem controller) pending
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#define INT_STATUS_PA REPLICATE_16(0x0020) // PCI int pending for Processor A
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#define INT_STATUS_PB REPLICATE_16(0x0040) // PCI int pending for Processor B
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#define INT_STATUS_PNI REPLICATE_16(0x0080) // NMI int (from PCI controller pending)
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#define INT_STATUS_IPA REPLICATE_16(0x0100) // Interproc int pending for Processor A
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#define INT_STATUS_IPB REPLICATE_16(0x0200) // Interproc int pending for Processor B
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#define INT_STATUS_ITA REPLICATE_16(0x0400) // Interval Timer interrupt pending for Processor A
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#define INT_STATUS_ITB REPLICATE_16(0x0800) // Interval Timer interrupt pending for Processor B
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#define INT_STATUS_AMASK (INT_STATUS_IOA|INT_STATUS_MA|INT_STATUS_PA|INT_STATUS_IPA|INT_STATUS_ITA|INT_STATUS_MNI|INT_STATUS_PNI)
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#define INT_STATUS_BMASK (INT_STATUS_IOB|INT_STATUS_MB|INT_STATUS_PB|INT_STATUS_IPB|INT_STATUS_ITB|INT_STATUS_MNI|INT_STATUS_PNI)
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#define INT_STATUS_MASK REPLICATE_16(0x03ff) // Int Status bit mask
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#define INT_STATUS_MASK_PMP_V2 REPLICATE_16(0x0fff) // Int Status bit mask
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//
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// INT Ctrl register bit definitions
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//
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#define INT_CTRL_IOEA REPLICATE_16(0x0001) // I/O int enable for Processor A
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#define INT_CTRL_IOEB REPLICATE_16(0x0002) // I/O int enable for Processor B
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#define INT_CTRL_MIEA REPLICATE_16(0x0004) // Mem sys int enable for Processor A
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#define INT_CTRL_MIEB REPLICATE_16(0x0008) // Mem sys int enable for Processor B
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#define INT_CTRL_MNE REPLICATE_16(0x0010) // Mem sys NMI enable for Processor A&B
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#define INT_CTRL_PIEA REPLICATE_16(0x0020) // PCI sys int enable for Processor A
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#define INT_CTRL_PIEB REPLICATE_16(0x0040) // PCI sys int enable for Processor B
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#define INT_CTRL_PNE REPLICATE_16(0x0080) // PCI sys NMI enable for Processor A&B
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#define INT_CTRL_IPEA REPLICATE_16(0x0100) // Inter Proc int enable for Processor A
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#define INT_CTRL_IPEB REPLICATE_16(0x0200) // Inter Proc int enable for Processor B
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#define INT_CTRL_ITEA REPLICATE_16(0x0400) // Interval Timer interrupt enable for Processor A
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#define INT_CTRL_ITEB REPLICATE_16(0x0800) // Interval Timer interrupt enable for Processor B
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#define INT_CTRL_IED REPLICATE_16(0x2000) // Interrupt escalation disable
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#define INT_CTRL_SEC0 REPLICATE_16(0x0000) // Synchronous delivery of exceptions
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#define INT_CTRL_SEC1 REPLICATE_16(0x4000) // Asynchronous delivery of exceptions
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#define INT_CTRL_SEC2 REPLICATE_16(0x8000) // Asynchronous delivery of exceptions if
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// error is not on first word (Narrow) or
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// first doubleword (Wide)
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#define INT_CTRL_MASK REPLICATE_16(0xe3ff) // INT Ctrl register bit mask
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#define INT_CTRL_MASK_PMP_V2 REPLICATE_16(0xefff) // INT Ctrl register bit mask
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#define ENABLE_IP_INTERRUPTS (INT_CTRL_IPEA | INT_CTRL_IPEB) // Enable A&B IP interrupts
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//
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// INT Cause register bit definitions
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//
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#define INT_CAUSE_IO REPLICATE_16(0x0001) // I/O interrupt delivered
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#define INT_CAUSE_MEM REPLICATE_16(0x0002) // Mem system interrupt delivered
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#define INT_CAUSE_MNMI REPLICATE_16(0x0004) // Mem NMI system interrupt delivered
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#define INT_CAUSE_PCI REPLICATE_16(0x0008) // PCI system interrupt delivered
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#define INT_CAUSE_PNMI REPLICATE_16(0x0010) // PCI NMI system interrupt delivered
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#define INT_CAUSE_IPC REPLICATE_16(0x0020) // InterProcessor interrupt delivered
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#define INT_CAUSE_TIMER REPLICATE_16(0x0040) // Interval Timer interrupt delivered
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#define INT_CAUSE_MASK REPLICATE_16(0x003f) // INT Cause register bit mask
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#define INT_CAUSE_MASK_PMP_V2 REPLICATE_16(0x007f) // INT Cause register bit mask
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//
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// IP Int Gen register bit definitions
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//
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#define IP_INT_GEN_IPIA REPLICATE_16(0x0001) // Gen InterProc int to Processor A
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#define IP_INT_GEN_IPIB REPLICATE_16(0x0002) // Gen InterProc int to Processor B
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#define IP_INT_GEN_MASK REPLICATE_16(0x0003) // IP Int Gen register bit mask
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//
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// IP Int Ack register bit definitions
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//
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#define IP_INT_ACK_IP REPLICATE_16(0x0001) // InterProcessor A Int pending
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#define IP_INT_ACK_MASK REPLICATE_16(0x0001) // IP Int Ack register bit mask
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//
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// IO Int Ack register bit definitions
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//
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#define IO_INT_ACK_MASK 0xff // IO Int ack bit mask
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//
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// Line buffer burst registers bit definitions
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//
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#define LBUF_BURST_MAP_MASK 0xFFFFFFE0 // bits define address field 31:5
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// where low-order five bits are
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// always 0 (minimum 32 byte aligned)
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#define LBUF_BURST_CTRL_ADDR 0x0000000F // bits 35:32 of physical address for Wide mode systems only
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#define LBUF_BURST_CTRL_SIZE 0x000001F0 // burst window size, ranges from (0) 32 bytes to (0x10) 512 bytes
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#define LBUF_BURST_CTRL_R0E REPLICATE_16(0x0200) // Return 0's Enable
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#define LBUF_BURST_CTRL_EOM REPLICATE_16(0x0400) // Even/Odd Nibble ...
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#define LBUF_BURST_CTRL_CME REPLICATE_16(0x0800) // Copy Mode Enable
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#define LBUF_BURST_CTRL_AWE REPLICATE_16(0x1000) // Address field write enable
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#define LBUF_BURST_CTRL_CWE REPLICATE_16(0x2000) // Control fields write enable
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#define LBUF_BURST_CTRL_MASK 0x3E003FFF // Mask of all writeable/readable bits
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//
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// Line buffer address space definitions
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//
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#define LBUF_ADDRESS_BS0 0
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#define LBUF_ADDRESS_BS1 REPLICATE_16(0x0400)
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#define LBUF_ADDRESS_BI0 0
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#define LBUF_ADDRESS_BI1 REPLICATE_16(0x0200)
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#define LBUF_ADDRESS_ALIAS 22
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//
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// External Pmp V1 Control register bit definitions
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//
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#define EPC_ECACHE_RESET 0x01
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#define EPC_POWER_0 0x02
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#define EPC_ECC_SIMM_ENABLE 0x04 // Clear for Parity SIMM enable...
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#define EPC_AUI 0x08
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#define EPC_FLASH_POWER 0x10
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#define EPC_LED_0 0x20
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#define EPC_LED_1 0x40
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#define EPC_LED_2 0x80
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#define EPC_REG_MASK 0xFF
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//
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// External Pmp V2 Control register bit definitions - bucky register 0
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//
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#define EPC_ECACHE_RESET_PMP_V2 0x01
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//#define EPC_ECACHE_TAGCS 0x02
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#define EPC_SCSI_TERMINATION 0x02 // for board revision 02 and later, now used for scsi termination
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#define EPC_POWER 0x04
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#define EPC_WATCHDOG 0x08
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#define EPC_LED_PMP_V2 0x10
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#define EPC_THERM_CLK 0x20
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#define EPC_WDSEL 0x40
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#define EPC_BREAD 0x80
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//
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// External PMP V2 Control additional register bit definitions - bucky register 1
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//
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#define EPC1_THERM_DQ 0x40
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#define EPC1_THERM_RST 0x80
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#define EPC1_DESKTOP 0x08 // 1 == Desktop, 0 == Tower
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#define EPC1_BOARD_ID 0x07 // Board revision
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#define BOARD_REV_00 0x07 // Original MB
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#define BOARD_REV_01 0x06 // Second revision (see falcon.s)
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#define BOARD_REV_02 0x05 // Third Rev, to change scsi termination
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#define IS_DESKTOP ( (*(PUCHAR)EXTERNAL_PMP_CONTROL_1) & EPC1_DESKTOP )
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// Firmware definitions
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//
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#define SECONDARY_CACHE_INVALID 0x0
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#define TAGLO_SSTATE 0xA
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//
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// Firmware Memory definitions
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#define NUMBER_OF_MEMORY_BANKS 8
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#endif // _FALCONREG_
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