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825 lines
24 KiB
825 lines
24 KiB
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/*++
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Copyright (C) 1989-1995 Microsoft Corporation
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All rights reserved.
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Module Name:
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ixpcibrd.c
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Abstract:
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Get PCI-PCI bridge information
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Environment:
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Kernel mode
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--*/
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#include "halp.h"
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#include "stdio.h"
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extern WCHAR rgzMultiFunctionAdapter[];
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extern WCHAR rgzConfigurationData[];
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extern WCHAR rgzIdentifier[];
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extern UCHAR HalpPCIPinToLineTable[];
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extern UCHAR HalpPCIBusToPirqTable[];
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WCHAR rgzReservedResources[] = L"\\Registry\\Machine\\System\\CurrentControlSet\\Control\\SystemResources\\ReservedResources";
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#if DBG
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#define DBGMSG(a) DbgPrint(a)
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#else
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#define DBGMSG(a)
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#endif
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#define IsPciBridge(a) \
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(a->VendorID != PCI_INVALID_VENDORID && \
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PCI_CONFIG_TYPE(a) == PCI_BRIDGE_TYPE && \
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a->SubClass == 4 && a->BaseClass == 6)
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typedef struct {
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ULONG BusNo;
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PBUS_HANDLER BusHandler;
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PPCIPBUSDATA BusData;
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PCI_SLOT_NUMBER SlotNumber;
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PPCI_COMMON_CONFIG PciData;
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ULONG IO, Memory, PFMemory;
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UCHAR Buffer[PCI_COMMON_HDR_LENGTH];
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} CONFIGBRIDGE, *PCONFIGBRIDGE;
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//
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// Internal prototypes
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//
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VOID
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HalpSetPciBridgedVgaCronk (
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IN ULONG BusNumber,
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IN ULONG Base,
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IN ULONG Limit
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);
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BOOLEAN
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HalpGetPciBridgeConfig (
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IN ULONG HwType,
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IN PUCHAR MaxPciBus
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);
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VOID
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HalpGetPciBridgeNeeds (
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IN ULONG HwType,
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IN PUCHAR MaxPciBus,
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IN PCONFIGBRIDGE Current
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);
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#ifdef ALLOC_PRAGMA
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#pragma alloc_text(INIT,HalpGetPciBridgeConfig)
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#pragma alloc_text(INIT,HalpSetPciBridgedVgaCronk)
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#pragma alloc_text(INIT,HalpFixupPciSupportedRanges)
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#endif
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BOOLEAN
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HalpGetPciBridgeConfig (
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IN ULONG HwType,
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IN PUCHAR MaxPciBus
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)
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/*++
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Routine Description:
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Scan the devices on all known pci buses trying to locate any
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pci to pci bridges. Record the hierarchy for the buses, and
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which buses have what addressing limits.
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Arguments:
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HwType - Configuration type.
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MaxPciBus - # of PCI buses reported by the bios
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--*/
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{
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PBUS_HANDLER ChildBus;
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PPCIPBUSDATA ChildBusData;
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ULONG d, f, i, j, BusNo;
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UCHAR Rescan;
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BOOLEAN FoundDisabledBridge;
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CONFIGBRIDGE CB;
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Rescan = 0;
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FoundDisabledBridge = FALSE;
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//
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// Find each bus on a bridge and initialize it's base and limit information
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//
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CB.PciData = (PPCI_COMMON_CONFIG) CB.Buffer;
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CB.SlotNumber.u.bits.Reserved = 0;
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for (BusNo=0; BusNo < *MaxPciBus; BusNo++) {
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CB.BusHandler = HalpHandlerForBus (PCIBus, BusNo);
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CB.BusData = (PPCIPBUSDATA) CB.BusHandler->BusData;
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for (d = 0; d < PCI_MAX_DEVICES; d++) {
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CB.SlotNumber.u.bits.DeviceNumber = d;
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for (f = 0; f < PCI_MAX_FUNCTION; f++) {
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CB.SlotNumber.u.bits.FunctionNumber = f;
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//
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// Read PCI configuration information
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//
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HalpReadPCIConfig (
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CB.BusHandler,
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CB.SlotNumber,
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CB.PciData,
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0,
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PCI_COMMON_HDR_LENGTH
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);
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if (CB.PciData->VendorID == PCI_INVALID_VENDORID) {
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// next device
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break;
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}
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if (!IsPciBridge (CB.PciData)) {
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// not a PCI-PCI bridge, next function
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continue;
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}
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if (!(CB.PciData->Command & PCI_ENABLE_BUS_MASTER)) {
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// this PCI bridge is not enabled - skip it for now
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FoundDisabledBridge = TRUE;
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continue;
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}
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if ((ULONG) CB.PciData->u.type1.PrimaryBus !=
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CB.BusHandler->BusNumber) {
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DBGMSG ("HAL GetPciData: bad primarybus!!!\n");
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// what to do?
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}
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//
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// Found a PCI-PCI brdige. Determine the PIRQ to bus number
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// mappings and store them in the HalpPCIBusToPirqTable[].
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//
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for (i = CB.PciData->u.type1.SecondaryBus;
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i <= CB.PciData->u.type1.SubordinateBus;
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i++) {
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HalpPCIBusToPirqTable[i] = HalpPCIPinToLineTable[d];
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}
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//
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// Found a PCI-PCI bridge. Determine it's parent child
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// relationships
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//
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ChildBus = HalpHandlerForBus (PCIBus, CB.PciData->u.type1.SecondaryBus);
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if (!ChildBus) {
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DBGMSG ("HAL GetPciData: found configured pci bridge\n");
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// up the number of buses
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if (CB.PciData->u.type1.SecondaryBus > Rescan) {
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Rescan = CB.PciData->u.type1.SecondaryBus;
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}
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continue;
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}
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ChildBusData = (PPCIPBUSDATA) ChildBus->BusData;
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if (ChildBusData->BridgeConfigRead) {
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// this child buses releationships already processed
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continue;
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}
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//
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// Remember the limits which are programmed into this bridge
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//
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ChildBusData->BridgeConfigRead = TRUE;
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HalpSetBusHandlerParent (ChildBus, CB.BusHandler);
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ChildBusData->ParentBus = (UCHAR) CB.BusHandler->BusNumber;
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ChildBusData->CommonData.ParentSlot = CB.SlotNumber;
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ChildBus->BusAddresses->IO.Base =
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PciBridgeIO2Base(
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CB.PciData->u.type1.IOBase,
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CB.PciData->u.type1.IOBaseUpper16
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);
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ChildBus->BusAddresses->IO.Limit =
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PciBridgeIO2Limit(
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CB.PciData->u.type1.IOLimit,
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CB.PciData->u.type1.IOLimitUpper16
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);
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//
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// Special VGA address remapping occuring on this bridge?
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//
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if (CB.PciData->u.type1.BridgeControl & PCI_ENABLE_BRIDGE_VGA &&
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ChildBus->BusAddresses->IO.Base < ChildBus->BusAddresses->IO.Limit) {
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DBGMSG("HAL: VGA mode enable in bridge\n");
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HalpSetPciBridgedVgaCronk (
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ChildBus->BusNumber,
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(ULONG) ChildBus->BusAddresses->IO.Base,
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(ULONG) ChildBus->BusAddresses->IO.Limit
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);
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}
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//
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// If supported I/O ranges on this bus are limitied to
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// 256bytes on every 1K aligned boundry within the
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// range, then redo supported IO BusAddresses to match
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//
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if (CB.PciData->u.type1.BridgeControl & PCI_ENABLE_BRIDGE_ISA &&
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ChildBus->BusAddresses->IO.Base < ChildBus->BusAddresses->IO.Limit) {
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DBGMSG("HAL: ISA mode enable in bridge\n");
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// assume Base is 1K aligned
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i = (ULONG) ChildBus->BusAddresses->IO.Base;
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j = (ULONG) ChildBus->BusAddresses->IO.Limit;
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// convert head entry
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ChildBus->BusAddresses->IO.Limit = i + 256;
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i += 1024;
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// add remaining ranges
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while (i < j) {
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HalpAddRange (
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&ChildBus->BusAddresses->IO,
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1, // address space
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0, // system base
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i, // bus address
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i + 256 // bus limit
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);
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// next range
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i += 1024;
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}
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}
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ChildBus->BusAddresses->Memory.Base =
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PciBridgeMemory2Base(CB.PciData->u.type1.MemoryBase);
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ChildBus->BusAddresses->Memory.Limit =
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PciBridgeMemory2Limit(CB.PciData->u.type1.MemoryLimit);
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// On x86 it's ok to clip Prefetch to 32 bits
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if (CB.PciData->u.type1.PrefetchBaseUpper32 == 0) {
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ChildBus->BusAddresses->PrefetchMemory.Base =
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PciBridgeMemory2Base(CB.PciData->u.type1.PrefetchBase);
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ChildBus->BusAddresses->PrefetchMemory.Limit =
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PciBridgeMemory2Limit(CB.PciData->u.type1.PrefetchLimit);
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if (CB.PciData->u.type1.PrefetchLimitUpper32) {
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ChildBus->BusAddresses->PrefetchMemory.Limit = (ULONGLONG)0xffffffff;
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}
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}
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// should call HalpAssignPCISlotResources to assign
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// baseaddresses, etc...
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}
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}
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}
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if (Rescan) {
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*MaxPciBus = Rescan;
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return TRUE;
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}
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if (!FoundDisabledBridge) {
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return FALSE;
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}
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DBGMSG ("HAL GetPciData: found disabled pci bridge\n");
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return FALSE;
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}
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VOID
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HalpFixupPciSupportedRanges (
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IN ULONG MaxBuses
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)
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/*++
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Routine Description:
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PCI-PCI bridged buses only see addresses which their parent
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bueses support. So adjust any PCI SUPPORT_RANGES to be
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a complete subset of all of it's parent buses.
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PCI-PCI briges use postive address decode to forward addresses.
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So, remove any addresses from any PCI bus which are bridged to
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a child PCI bus.
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--*/
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{
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ULONG i;
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PBUS_HANDLER Bus, ParentBus;
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PSUPPORTED_RANGES HRanges;
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//
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// Pass 1 - shrink all PCI supported ranges to be a subset of
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// all of it's parent buses
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//
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for (i = 0; i < MaxBuses; i++) {
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Bus = HalpHandlerForBus (PCIBus, i);
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ParentBus = Bus->ParentHandler;
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while (ParentBus) {
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HRanges = Bus->BusAddresses;
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Bus->BusAddresses = HalpMergeRanges (
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ParentBus->BusAddresses,
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HRanges
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);
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HalpFreeRangeList (HRanges);
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ParentBus = ParentBus->ParentHandler;
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}
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}
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//
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// Pass 2 - remove all child PCI bus ranges from parent PCI buses
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//
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for (i = 0; i < MaxBuses; i++) {
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Bus = HalpHandlerForBus (PCIBus, i);
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ParentBus = Bus->ParentHandler;
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while (ParentBus) {
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if (ParentBus->InterfaceType == PCIBus) {
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HalpRemoveRanges (
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ParentBus->BusAddresses,
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Bus->BusAddresses
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);
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}
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ParentBus = ParentBus->ParentHandler;
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}
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}
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//
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// Cleanup
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//
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for (i = 0; i < MaxBuses; i++) {
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Bus = HalpHandlerForBus (PCIBus, i);
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HalpConsolidateRanges (Bus->BusAddresses);
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}
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}
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VOID
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HalpSetPciBridgedVgaCronk (
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IN ULONG BusNumber,
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IN ULONG BaseAddress,
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IN ULONG LimitAddress
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)
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/*++
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Routine Description: .
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The 'vga compatible addresses' bit is set in the bridge control regiter.
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This causes the bridge to pass any I/O address in the range of: 10bit
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decode 3b0-3bb & 3c0-3df, as TEN bit addresses.
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As far as I can tell this "feature" is an attempt to solve some problem
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which the folks solving it did not fully understand, so instead of doing
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it right we have this fine mess.
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The solution is to take the least of all evils which is to remove any
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I/O port ranges which are getting remapped from any IoAssignResource
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request. (ie, IoAssignResources will never contimplate giving any
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I/O port out in the suspected ranges).
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note: memory allocation error here is fatal so don't bother with the
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return codes.
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Arguments:
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Base - Base of IO address range in question
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Limit - Limit of IO address range in question
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--*/
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{
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UNICODE_STRING unicodeString;
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OBJECT_ATTRIBUTES objectAttributes;
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HANDLE handle;
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ULONG Length;
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PCM_RESOURCE_LIST ResourceList;
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PCM_PARTIAL_RESOURCE_DESCRIPTOR Descriptor;
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ULONG AddressMSBs;
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WCHAR ValueName[80];
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NTSTATUS status;
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//
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// Open reserved resource settings
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//
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RtlInitUnicodeString (&unicodeString, rgzReservedResources);
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InitializeObjectAttributes( &objectAttributes,
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&unicodeString,
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OBJ_CASE_INSENSITIVE,
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NULL,
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(PSECURITY_DESCRIPTOR) NULL
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);
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status = ZwOpenKey( &handle, KEY_READ|KEY_WRITE, &objectAttributes);
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if (!NT_SUCCESS(status)) {
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return;
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}
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//
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// Build resource list of reseved ranges
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//
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Length = ((LimitAddress - BaseAddress) / 1024 + 2) * 2 *
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sizeof (CM_PARTIAL_RESOURCE_DESCRIPTOR) +
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sizeof (CM_RESOURCE_LIST);
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ResourceList = (PCM_RESOURCE_LIST) ExAllocatePool (PagedPool, Length);
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memset (ResourceList, 0, Length);
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ResourceList->Count = 1;
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ResourceList->List[0].InterfaceType = PCIBus;
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ResourceList->List[0].BusNumber = BusNumber;
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Descriptor = ResourceList->List[0].PartialResourceList.PartialDescriptors;
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while (BaseAddress < LimitAddress) {
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AddressMSBs = BaseAddress & ~0x3ff; // get upper 10bits of addr
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//
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// Add xx3b0 through xx3bb
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//
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Descriptor->Type = CmResourceTypePort;
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Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
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Descriptor->Flags = CM_RESOURCE_PORT_IO;
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Descriptor->u.Port.Start.QuadPart = AddressMSBs | 0x3b0;
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Descriptor->u.Port.Length = 0xb;
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Descriptor += 1;
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ResourceList->List[0].PartialResourceList.Count += 1;
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//
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// Add xx3c0 through xx3df
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//
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Descriptor->Type = CmResourceTypePort;
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Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
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Descriptor->Flags = CM_RESOURCE_PORT_IO;
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Descriptor->u.Port.Start.QuadPart = AddressMSBs | 0x3c0;
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Descriptor->u.Port.Length = 0x1f;
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Descriptor += 1;
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ResourceList->List[0].PartialResourceList.Count += 1;
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//
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// Next range
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//
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BaseAddress += 1024;
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}
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//
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// Add the reserved ranges to avoid during IoAssignResource
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//
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swprintf (ValueName, L"HAL_PCI_%d", BusNumber);
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RtlInitUnicodeString (&unicodeString, ValueName);
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ZwSetValueKey (handle,
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&unicodeString,
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0L,
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REG_RESOURCE_LIST,
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ResourceList,
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(ULONG) Descriptor - (ULONG) ResourceList
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);
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ExFreePool (ResourceList);
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ZwClose (handle);
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}
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VOID
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HalpGetPciBridgeNeeds (
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IN ULONG HwType,
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IN PUCHAR MaxPciBus,
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IN PCONFIGBRIDGE Current
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)
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{
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ACCESS_MASK DesiredAccess;
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UNICODE_STRING unicodeString;
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PUCHAR buffer;
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HANDLE handle;
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OBJECT_ATTRIBUTES objectAttributes;
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PCM_FULL_RESOURCE_DESCRIPTOR Descriptor;
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PCONFIGURATION_COMPONENT Component;
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CONFIGBRIDGE CB;
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ULONG mnum, d, f;
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NTSTATUS status;
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buffer = ExAllocatePool (PagedPool, 1024);
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// init
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CB.PciData = (PPCI_COMMON_CONFIG) CB.Buffer;
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CB.SlotNumber.u.bits.Reserved = 0;
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Current->IO = Current->Memory = Current->PFMemory = 0;
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//
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// Assign this bridge an ID, and turn on configuration space
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//
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Current->PciData->u.type1.PrimaryBus = (UCHAR) Current->BusNo;
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Current->PciData->u.type1.SecondaryBus = (UCHAR) *MaxPciBus;
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Current->PciData->u.type1.SubordinateBus = (UCHAR) 0xFF;
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Current->PciData->u.type1.SecondaryStatus = 0xffff;
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Current->PciData->Status = 0xffff;
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Current->PciData->Command = 0;
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Current->PciData->u.type1.BridgeControl = PCI_ASSERT_BRIDGE_RESET;
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HalpWritePCIConfig (
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Current->BusHandler,
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Current->SlotNumber,
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Current->PciData,
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0,
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PCI_COMMON_HDR_LENGTH
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);
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KeStallExecutionProcessor (100);
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Current->PciData->u.type1.BridgeControl = 0;
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HalpWritePCIConfig (
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Current->BusHandler,
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Current->SlotNumber,
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Current->PciData,
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0,
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PCI_COMMON_HDR_LENGTH
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);
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KeStallExecutionProcessor (100);
|
|
|
|
//
|
|
// Allocate new handler for bus
|
|
//
|
|
|
|
CB.BusHandler = HalpAllocateAndInitPciBusHandler (HwType, *MaxPciBus, FALSE);
|
|
CB.BusData = (PPCIPBUSDATA) CB.BusHandler->BusData;
|
|
CB.BusNo = *MaxPciBus;
|
|
*MaxPciBus += 1;
|
|
|
|
//
|
|
// Add another PCI bus in the registry
|
|
//
|
|
|
|
mnum = 0;
|
|
for (; ;) {
|
|
//
|
|
// Find next available MultiFunctionAdapter key
|
|
//
|
|
|
|
DesiredAccess = KEY_READ | KEY_WRITE;
|
|
swprintf ((PWCHAR) buffer, L"%s\\%d", rgzMultiFunctionAdapter, mnum);
|
|
RtlInitUnicodeString (&unicodeString, (PWCHAR) buffer);
|
|
|
|
InitializeObjectAttributes( &objectAttributes,
|
|
&unicodeString,
|
|
OBJ_CASE_INSENSITIVE,
|
|
NULL,
|
|
(PSECURITY_DESCRIPTOR) NULL
|
|
);
|
|
|
|
status = ZwOpenKey( &handle, DesiredAccess, &objectAttributes);
|
|
if (!NT_SUCCESS(status)) {
|
|
break;
|
|
}
|
|
|
|
// already exists, next
|
|
ZwClose (handle);
|
|
mnum += 1;
|
|
}
|
|
|
|
ZwCreateKey (&handle,
|
|
DesiredAccess,
|
|
&objectAttributes,
|
|
0,
|
|
NULL,
|
|
REG_OPTION_VOLATILE,
|
|
&d
|
|
);
|
|
|
|
//
|
|
// Add needed registry values for this MultifucntionAdapter entry
|
|
//
|
|
|
|
RtlInitUnicodeString (&unicodeString, rgzIdentifier);
|
|
ZwSetValueKey (handle,
|
|
&unicodeString,
|
|
0L,
|
|
REG_SZ,
|
|
L"PCI",
|
|
sizeof (L"PCI")
|
|
);
|
|
|
|
RtlInitUnicodeString (&unicodeString, rgzConfigurationData);
|
|
Descriptor = (PCM_FULL_RESOURCE_DESCRIPTOR) buffer;
|
|
Descriptor->InterfaceType = PCIBus;
|
|
Descriptor->BusNumber = CB.BusNo;
|
|
Descriptor->PartialResourceList.Version = 0;
|
|
Descriptor->PartialResourceList.Revision = 0;
|
|
Descriptor->PartialResourceList.Count = 0;
|
|
ZwSetValueKey (handle,
|
|
&unicodeString,
|
|
0L,
|
|
REG_FULL_RESOURCE_DESCRIPTOR,
|
|
Descriptor,
|
|
sizeof (*Descriptor)
|
|
);
|
|
|
|
|
|
RtlInitUnicodeString (&unicodeString, L"Component Information");
|
|
Component = (PCONFIGURATION_COMPONENT) buffer;
|
|
RtlZeroMemory (Component, sizeof (*Component));
|
|
Component->AffinityMask = 0xffffffff;
|
|
ZwSetValueKey (handle,
|
|
&unicodeString,
|
|
0L,
|
|
REG_BINARY,
|
|
Component,
|
|
FIELD_OFFSET (CONFIGURATION_COMPONENT, ConfigurationDataLength)
|
|
);
|
|
|
|
ZwClose (handle);
|
|
|
|
|
|
//
|
|
// Since the firmware didn't configure this bridge we'll assume that
|
|
// the PCI interrupts are bridged.
|
|
//
|
|
|
|
for (d = 0; d < PCI_MAX_DEVICES; d++) {
|
|
CB.SlotNumber.u.bits.DeviceNumber = d;
|
|
|
|
for (f = 0; f < PCI_MAX_FUNCTION; f++) {
|
|
CB.SlotNumber.u.bits.FunctionNumber = f;
|
|
|
|
HalpReadPCIConfig (
|
|
Current->BusHandler,
|
|
CB.SlotNumber,
|
|
CB.PciData,
|
|
0,
|
|
PCI_COMMON_HDR_LENGTH
|
|
);
|
|
|
|
if (CB.PciData->VendorID == PCI_INVALID_VENDORID) {
|
|
break;
|
|
}
|
|
|
|
if (CB.PciData->u.type0.InterruptPin &&
|
|
(PCI_CONFIG_TYPE (CB.PciData) == PCI_DEVICE_TYPE ||
|
|
PCI_CONFIG_TYPE (CB.PciData) == PCI_BRIDGE_TYPE)) {
|
|
|
|
//
|
|
// Get IRQ value from table since firmware
|
|
// did not initialize the bridge.
|
|
//
|
|
|
|
Current->PciData->u.type1.InterruptPin =
|
|
CB.PciData->u.type0.InterruptPin + (UCHAR)d % 4;
|
|
|
|
Current->PciData->u.type1.InterruptLine =
|
|
HalpPCIPinToLineTable[(CB.BusNo*8) + CB.SlotNumber.u.bits.DeviceNumber];
|
|
}
|
|
}
|
|
}
|
|
|
|
//
|
|
// Look at each device on the bus and determine it's resource needs
|
|
//
|
|
|
|
for (d = 0; d < PCI_MAX_DEVICES; d++) {
|
|
CB.SlotNumber.u.bits.DeviceNumber = d;
|
|
|
|
for (f = 0; f < PCI_MAX_FUNCTION; f++) {
|
|
CB.SlotNumber.u.bits.FunctionNumber = f;
|
|
|
|
HalpReadPCIConfig (
|
|
CB.BusHandler,
|
|
CB.SlotNumber,
|
|
CB.PciData,
|
|
0,
|
|
PCI_COMMON_HDR_LENGTH
|
|
);
|
|
|
|
if (CB.PciData->VendorID == PCI_INVALID_VENDORID) {
|
|
break;
|
|
}
|
|
|
|
if (IsPciBridge (CB.PciData)) {
|
|
// oh look - another bridge ...
|
|
HalpGetPciBridgeNeeds (HwType, MaxPciBus, &CB);
|
|
continue;
|
|
}
|
|
|
|
if (PCI_CONFIG_TYPE (CB.PciData) != PCI_DEVICE_TYPE) {
|
|
continue;
|
|
}
|
|
|
|
// found a device - figure out the resources it needs
|
|
}
|
|
}
|
|
|
|
//
|
|
// Found all sub-buses set SubordinateBus accordingly
|
|
//
|
|
|
|
Current->PciData->u.type1.SubordinateBus = (UCHAR) *MaxPciBus - 1;
|
|
|
|
HalpWritePCIConfig (
|
|
Current->BusHandler,
|
|
Current->SlotNumber,
|
|
Current->PciData,
|
|
0,
|
|
PCI_COMMON_HDR_LENGTH
|
|
);
|
|
|
|
|
|
//
|
|
// Set the bridges IO, Memory, and Prefetch Memory windows
|
|
//
|
|
|
|
// For now just pick some numbers & set everyone the same
|
|
// IO 0x6000 - 0xFFFF
|
|
// MEM 0x40000000 - 0x4FFFFFFF
|
|
// PFMEM 0x50000000 - 0x5FFFFFFF
|
|
|
|
Current->PciData->u.type1.IOBase = 0xD000 >> 12 << 4;
|
|
Current->PciData->u.type1.IOLimit = 0xffff >> 12 << 4;
|
|
Current->PciData->u.type1.MemoryBase = 0x0 >> 20 << 4;
|
|
Current->PciData->u.type1.MemoryLimit = 0x0 >> 20 << 4;
|
|
Current->PciData->u.type1.PrefetchBase = 0 >> 20 << 4;
|
|
Current->PciData->u.type1.PrefetchLimit = 0 >> 20 << 4;
|
|
|
|
Current->PciData->u.type1.PrefetchBaseUpper32 = 0;
|
|
Current->PciData->u.type1.PrefetchLimitUpper32 = 0;
|
|
Current->PciData->u.type1.IOBaseUpper16 = 0;
|
|
Current->PciData->u.type1.IOLimitUpper16 = 0;
|
|
Current->PciData->u.type1.BridgeControl =
|
|
PCI_ENABLE_BRIDGE_ISA;
|
|
|
|
HalpWritePCIConfig (
|
|
Current->BusHandler,
|
|
Current->SlotNumber,
|
|
Current->PciData,
|
|
0,
|
|
PCI_COMMON_HDR_LENGTH
|
|
);
|
|
|
|
HalpReadPCIConfig (
|
|
Current->BusHandler,
|
|
Current->SlotNumber,
|
|
Current->PciData,
|
|
0,
|
|
PCI_COMMON_HDR_LENGTH
|
|
);
|
|
|
|
// enable memory & io decodes
|
|
|
|
Current->PciData->Command =
|
|
PCI_ENABLE_IO_SPACE | PCI_ENABLE_MEMORY_SPACE | PCI_ENABLE_BUS_MASTER;
|
|
|
|
HalpWritePCIConfig (
|
|
Current->BusHandler,
|
|
Current->SlotNumber,
|
|
&Current->PciData->Command,
|
|
FIELD_OFFSET (PCI_COMMON_CONFIG, Command),
|
|
sizeof (Current->PciData->Command)
|
|
);
|
|
|
|
ExFreePool (buffer);
|
|
}
|
|
|
|
|
|
|