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326 lines
13 KiB
326 lines
13 KiB
/*++
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Copyright (c) 1993 NeTpower Incorporated
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Module Name:
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pcieisa.h
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Abstract:
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This module is the header file that describes virtual
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register address used by the EISA System Component (ESC)
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device (82374EB).
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Author:
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Hector R. Briones (hector) 29-Nov-1993
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Revision History:
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--*/
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#ifndef _PCIEISA_
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#define _PCIEISA_
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#define ESC_DMA0_ADDRESS (EISA_CONTROL_VIRTUAL_BASE)
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#define ESC_DMA0_COUNTER (EISA_CONTROL_VIRTUAL_BASE + 0x1)
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#define ESC_DMA1_ADDRESS (EISA_CONTROL_VIRTUAL_BASE + 0x2)
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#define ESC_DMA1_COUNTER (EISA_CONTROL_VIRTUAL_BASE + 0x3)
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#define ESC_DMA2_ADDRESS (EISA_CONTROL_VIRTUAL_BASE + 0x4)
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#define ESC_DMA2_COUNTER (EISA_CONTROL_VIRTUAL_BASE + 0x5)
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#define ESC_DMA3_ADDRESS (EISA_CONTROL_VIRTUAL_BASE + 0x6)
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#define ESC_DMA3_COUNTER (EISA_CONTROL_VIRTUAL_BASE + 0x7)
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#define ESC_DMA0_3_CMD (EISA_CONTROL_VIRTUAL_BASE + 0x8)
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#define ESC_DMA0_3_STATUS (EISA_CONTROL_VIRTUAL_BASE + 0x8)
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#define ESC_DMA0_3_REQ (EISA_CONTROL_VIRTUAL_BASE + 0x9)
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#define ESC_DMA0_3_MASKSB (EISA_CONTROL_VIRTUAL_BASE + 0xa)
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#define ESC_DMA0_3_MODE (EISA_CONTROL_VIRTUAL_BASE + 0xb)
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#define ESC_DMA0_3_CLRBP (EISA_CONTROL_VIRTUAL_BASE + 0xc)
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#define ESC_DMA0_3_MASTER_CLR (EISA_CONTROL_VIRTUAL_BASE + 0xd)
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#define ESC_DMA0_3_CLRMASK (EISA_CONTROL_VIRTUAL_BASE + 0xe)
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#define ESC_DMA0_3_ALLBITMASK (EISA_CONTROL_VIRTUAL_BASE + 0xf)
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#define ESC_INT_CONTROL1 (EISA_CONTROL_VIRTUAL_BASE + 0x20)
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#define ESC_INT_MASK1 (EISA_CONTROL_VIRTUAL_BASE + 0x21)
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#define ESC_TC1_COUNTER0 (EISA_CONTROL_VIRTUAL_BASE + 0x40)
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#define ESC_TC1_COUNTER1 (EISA_CONTROL_VIRTUAL_BASE + 0x41)
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#define ESC_TC1_COUNTER2 (EISA_CONTROL_VIRTUAL_BASE + 0x42)
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#define ESC_TC1_CONTROL (EISA_CONTROL_VIRTUAL_BASE + 0x43)
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#define ESC_TC1_RBCMD (EISA_CONTROL_VIRTUAL_BASE + 0x43)
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#define ESC_TC1_LATCH_CMD (EISA_CONTROL_VIRTUAL_BASE + 0x43)
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#define ESC_TC2_COUNTER0 (EISA_CONTROL_VIRTUAL_BASE + 0x48)
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#define ESC_TC2_COUNTER2 (EISA_CONTROL_VIRTUAL_BASE + 0x4a)
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#define ESC_TC2_CONTROL (EISA_CONTROL_VIRTUAL_BASE + 0x4b)
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#define ESC_TC2_RBCMD (EISA_CONTROL_VIRTUAL_BASE + 0x4b)
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#define ESC_TC2_LATCH_CMD (EISA_CONTROL_VIRTUAL_BASE + 0x4b)
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#define ESC_RST_UBUS_IRQ12 (EISA_CONTROL_VIRTUAL_BASE + 0x60)
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#define ESC_NMI_CONTROL_STATUS (EISA_CONTROL_VIRTUAL_BASE + 0x61)
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#define ESC_NMI_RTC (EISA_CONTROL_VIRTUAL_BASE + 0x70)
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#define ESC_CMOS_RAM_ADDRESS (EISA_CONTROL_VIRTUAL_BASE + 0x70)
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#define ESC_CMOS_RAM_DATA (EISA_CONTROL_VIRTUAL_BASE + 0x71)
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#define ESC_BIOS_TIMER (EISA_CONTROL_VIRTUAL_BASE + 0x78)
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#define ESC_DMA0_PAGE (EISA_CONTROL_VIRTUAL_BASE + 0x87)
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#define ESC_DMA1_PAGE (EISA_CONTROL_VIRTUAL_BASE + 0x83)
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#define ESC_DMA2_PAGE (EISA_CONTROL_VIRTUAL_BASE + 0x81)
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#define ESC_DMA3_PAGE (EISA_CONTROL_VIRTUAL_BASE + 0x82)
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#define ESC_DMA5_PAGE (EISA_CONTROL_VIRTUAL_BASE + 0x8b)
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#define ESC_DMA6_PAGE (EISA_CONTROL_VIRTUAL_BASE + 0x89)
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#define ESC_DMA7_PAGE (EISA_CONTROL_VIRTUAL_BASE + 0x8a)
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#define ESC_DMA_LPAGE_REF (EISA_CONTROL_VIRTUAL_BASE + 0x8f)
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#define ESC_PORT_92 (EISA_CONTROL_VIRTUAL_BASE + 0x8f)
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#define ESC_INT_CONTROL2 (EISA_CONTROL_VIRTUAL_BASE + 0xa0)
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#define ESC_INT_MASK2 (EISA_CONTROL_VIRTUAL_BASE + 0xa1)
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#define ESC_DMA4_ADDRESS (EISA_CONTROL_VIRTUAL_BASE + 0xc0)
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#define ESC_DMA4_COUNTER (EISA_CONTROL_VIRTUAL_BASE + 0xc2)
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#define ESC_DMA5_ADDRESS (EISA_CONTROL_VIRTUAL_BASE + 0xc4)
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#define ESC_DMA5_COUNTER (EISA_CONTROL_VIRTUAL_BASE + 0xc6)
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#define ESC_DMA6_ADDRESS (EISA_CONTROL_VIRTUAL_BASE + 0xc8)
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#define ESC_DMA6_COUNTER (EISA_CONTROL_VIRTUAL_BASE + 0xca)
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#define ESC_DMA7_ADDRESS (EISA_CONTROL_VIRTUAL_BASE + 0xcc)
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#define ESC_DMA7_COUNTER (EISA_CONTROL_VIRTUAL_BASE + 0xce)
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#define ESC_DMA4_7_CMD (EISA_CONTROL_VIRTUAL_BASE + 0xd0)
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#define ESC_DMA4_7_STATUS (EISA_CONTROL_VIRTUAL_BASE + 0xd0)
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#define ESC_DMA4_7_REQ (EISA_CONTROL_VIRTUAL_BASE + 0xd2)
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#define ESC_DMA4_7_MASKSB (EISA_CONTROL_VIRTUAL_BASE + 0xd4)
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#define ESC_DMA4_7_MODE (EISA_CONTROL_VIRTUAL_BASE + 0xd6)
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#define ESC_DMA4_7_CLRBP (EISA_CONTROL_VIRTUAL_BASE + 0xd8)
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#define ESC_DMA4_7_MASTER_CLR (EISA_CONTROL_VIRTUAL_BASE + 0xda)
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#define ESC_DMA4_7_CLRMASK (EISA_CONTROL_VIRTUAL_BASE + 0xdc)
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#define ESC_DMA4_7_ALLBITMASK (EISA_CONTROL_VIRTUAL_BASE + 0xde)
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#define ESC_FLOP2_DOR (EISA_CONTROL_VIRTUAL_BASE + 0x372)
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#define ESC_FLOP1_DOR (EISA_CONTROL_VIRTUAL_BASE + 0x3f2)
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#define ESC_DMA_SGINT_STAT (EISA_CONTROL_VIRTUAL_BASE + 0x40a)
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#define ESC_DMA0_SGCMD (EISA_CONTROL_VIRTUAL_BASE + 0x410)
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#define ESC_DMA1_SGCMD (EISA_CONTROL_VIRTUAL_BASE + 0x411)
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#define ESC_DMA2_SGCMD (EISA_CONTROL_VIRTUAL_BASE + 0x412)
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#define ESC_DMA3_SGCMD (EISA_CONTROL_VIRTUAL_BASE + 0x413)
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#define ESC_DMA5_SGCMD (EISA_CONTROL_VIRTUAL_BASE + 0x415)
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#define ESC_DMA6_SGCMD (EISA_CONTROL_VIRTUAL_BASE + 0x416)
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#define ESC_DMA7_SGCMD (EISA_CONTROL_VIRTUAL_BASE + 0x417)
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#define ESC_DMA0_SGSTAT (EISA_CONTROL_VIRTUAL_BASE + 0x418)
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#define ESC_DMA1_SGSTAT (EISA_CONTROL_VIRTUAL_BASE + 0x419)
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#define ESC_DMA2_SGSTAT (EISA_CONTROL_VIRTUAL_BASE + 0x41a)
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#define ESC_DMA3_SGSTAT (EISA_CONTROL_VIRTUAL_BASE + 0x41b)
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#define ESC_DMA5_SGSTAT (EISA_CONTROL_VIRTUAL_BASE + 0x41d)
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#define ESC_DMA6_SGSTAT (EISA_CONTROL_VIRTUAL_BASE + 0x41e)
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#define ESC_DMA7_SGSTAT (EISA_CONTROL_VIRTUAL_BASE + 0x41f)
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#define ESC_DMA0_SGDPTR (EISA_CONTROL_VIRTUAL_BASE + 0x420)
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#define ESC_DMA1_SGDPTR (EISA_CONTROL_VIRTUAL_BASE + 0x424)
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#define ESC_DMA2_SGDPTR (EISA_CONTROL_VIRTUAL_BASE + 0x428)
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#define ESC_DMA3_SGDPTR (EISA_CONTROL_VIRTUAL_BASE + 0x42c)
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#define ESC_DMA5_SGDPTR (EISA_CONTROL_VIRTUAL_BASE + 0x434)
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#define ESC_DMA6_SGDPTR (EISA_CONTROL_VIRTUAL_BASE + 0x438)
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#define ESC_DMA7_SGDPTR (EISA_CONTROL_VIRTUAL_BASE + 0x43c)
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#define ESC_NMI_EXT (EISA_CONTROL_VIRTUAL_BASE + 0x461)
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#define ESC_SW_NMI (EISA_CONTROL_VIRTUAL_BASE + 0x462)
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#define ESC_DMA0_HIPAGE (EISA_CONTROL_VIRTUAL_BASE + 0x487)
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#define ESC_DMA1_HIPAGE (EISA_CONTROL_VIRTUAL_BASE + 0x483)
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#define ESC_DMA2_HIPAGE (EISA_CONTROL_VIRTUAL_BASE + 0x481)
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#define ESC_DMA3_HIPAGE (EISA_CONTROL_VIRTUAL_BASE + 0x482)
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#define ESC_DMA5_HIPAGE (EISA_CONTROL_VIRTUAL_BASE + 0x48b)
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#define ESC_DMA6_HIPAGE (EISA_CONTROL_VIRTUAL_BASE + 0x489)
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#define ESC_DMA7_HIPAGE (EISA_CONTROL_VIRTUAL_BASE + 0x48a)
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#define ESC_EDGE_LEVEL1 (EISA_CONTROL_VIRTUAL_BASE + 0x4d0)
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#define ESC_EDGE_LEVEL2 (EISA_CONTROL_VIRTUAL_BASE + 0x4d1)
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#define ESC_DMA_EXT_MODE (EISA_CONTROL_VIRTUAL_BASE + 0x4d6)
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//
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// Timer/Counter Control Word definitions
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//
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#define ESC_TC_CNTRLW_RB_CMD 0xc0 // Read Back command
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#define ESC_TC_CNTRLW_SC(x) (x<<6) // Select counter (0-2)
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#define ESC_TC_CNTRLW_SC2 0x80 // Select counter 2
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#define ESC_TC_CNTRLW_SC1 0x40 // Select counter 1
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#define ESC_TC_CNTRLW_SC0 0x00 // Select counter 0
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#define ESC_TC_CNTRLW_CLC 0x00 // Counter Latch command
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#define ESC_TC_CNTRLW_16B 0x30 // R/W LSB then MSB
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#define ESC_TC_CNTRLW_MSB 0x20 // R/W Most sig. byte (MSB)
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#define ESC_TC_CNTRLW_LSB 0x10 // R/W Least sig. byte (LSB)
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#define ESC_TC_CNTRLW_MODE(x) (x<<1) // Select mode (0-5)
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#define ESC_TC_CNTRLW_BCD 0x01 // Binary/BCD countdown type
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//
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// Timer/Counter Modes
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//
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#define ESC_TC_MODE_ITC 0 // Sel mode0 (int. on term count)
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#define ESC_TC_MODE_HROS 1 // Sel mode1 (hw retrig. 1 shot)
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#define ESC_TC_MODE_RGEN 2 // Sel mode2 (rate generator)
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#define ESC_TC_MODE_SQW 3 // Sel mode3 (square wave mode)
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#define ESC_TC_MODE_STS 4 // Sel mode4 (sw triggerable strobe)
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#define ESC_TC_MODE_HTS 5 // Sel mode5 (hw triggerable strobe)
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//
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// Timer/Counter Read Back Command register
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//
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#define ESC_TC_NOLATCH_STATUS 0x20 // Do not Latch status - selected cntrs
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#define ESC_TC_NOLATCH_CNTR 0x10 // Do not Latch count of selected cntrs
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#define ESC_TC_LATCH_CNTR 0x00 // Latch count of selected cntrs
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#define ESC_TC_LATCH_STATUS 0x00 // Latch status - selected cntrs
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#define ESC_TC_RBCMD_SEL_CNT2 0x08 // Read Back Cmd, select counter2
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#define ESC_TC_RBCMD_SEL_CNT1 0x04 // Read Back Cmd, select counter1
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#define ESC_TC_RBCMD_SEL_CNT0 0x02 // Read Back Cmd, select counter0
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//
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// With a divisor of 11930 (0x2e9a), counter0 will produces a square
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// wave with a period of 10ms. If clock frequency (1.193MHz) is divided
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// by the divisor(11930), it gives a result of 100. If the recipricol of
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// the result (100) is done, it equals 10ms.
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//
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#define NANOSECONDS 1
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#define MICROSECONDS ( 1000 * NANOSECONDS )
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#define MILLISECONDS ( 1000 * MICROSECONDS )
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#define SECONDS ( 1000 * MILLISECONDS )
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#define COUNTER_PERIOD ( 838 * NANOSECONDS )
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#define COUNTER_10MS ( ( ( 10 * MILLISECONDS ) / COUNTER_PERIOD ) )
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#define COUNTER_1MS ( ( ( 1 * MILLISECONDS ) / COUNTER_PERIOD ) )
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//
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// NMI Status and Control Register
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//
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#define ESC_NCS_T1C2_OUT 0x20 // Output of Timer 1, Counter 2
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#define ESC_NCS_SPEAKER_ENABLE 0x02 // Enable Speaker, used for Interval Timer PMP v2
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#define ESC_NCS_T1C2_ENABLE 0x01 // Enable Timer 1, Counter 2
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//
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// The ESC Configuration registers are accessed through
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// and indexing scheme. The Index address register is
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// located at I/O address 0x22 and the index data register
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// is located at I/O address 0x23. The register data
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// written into the index address register selects the
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// desired configuration register. Data for the selected
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// configuration register can be read from or written to,
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// by performing a read or write to the index data register.
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//
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#define ESC_CONFIG_INDEX_ADDRESS (EISA_CONTROL_VIRTUAL_BASE + 0x22)
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#define ESC_CONFIG_INDEX_DATA (EISA_CONTROL_VIRTUAL_BASE + 0x23)
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#define ESC_CONFIG_ID 0x2
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#define ESC_CONFIG_REVID 0x8
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#define ESC_CONFIG_MODE_SEL 0x40
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#define ESC_CONFIG_BIOS_CSA 0x42
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#define ESC_CONFIG_BIOS_CSB 0x43
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#define ESC_CONFIG_EISA_CLK_DIV 0x4d
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#define ESC_CONFIG_PERIPH_CSA 0x4e
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#define ESC_CONFIG_PERIPH_CSB 0x4f
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#define ESC_CONFIG_EISA_ID0 0x50
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#define ESC_CONFIG_EISA_ID1 0x51
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#define ESC_CONFIG_EISA_ID2 0x52
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#define ESC_CONFIG_EISA_ID3 0x53
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#define ESC_CONFIG_SGRBA 0x57
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#define ESC_CONFIG_PIRQ0 0x60
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#define ESC_CONFIG_PIRQ1 0x61
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#define ESC_CONFIG_PIRQ2 0x62
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#define ESC_CONFIG_PIRQ3 0x63
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#define ESC_CONFIG_GPCSLA0 0x64
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#define ESC_CONFIG_GPCSHA0 0x65
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#define ESC_CONFIG_GPCSMASK0 0x66
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#define ESC_CONFIG_GPCSLA1 0x68
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#define ESC_CONFIG_GPCSHA1 0x69
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#define ESC_CONFIG_GPCSMASK1 0x6a
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#define ESC_CONFIG_GPCSLA2 0x6c
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#define ESC_CONFIG_GPCSHA2 0x6d
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#define ESC_CONFIG_GPCSMASK2 0x6e
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#define ESC_CONFIG_GPXBC 0x6f
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#define ESC_CONFIG_TEST_CNTRL 0x88
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//
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// Bit definitions for ESC configuration registers.
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//
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#define ESC_CONFIG_IDEN_BYTE 0x0f // Enable access to config registers
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#define ESC_BIOS_CSA_LOWBIOS1 0x01 // Addrs range 0xfffe0000 - 0xfffe3fff
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#define ESC_BIOS_CSA_LOWBIOS2 0x02 // Addrs range 0xfffe4000 - 0xfffe7fff
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#define ESC_BIOS_CSA_LOWBIOS3 0x04 // Addrs range 0xfffe8000 - 0xfffebfff
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#define ESC_BIOS_CSA_LOWBIOS4 0x08 // Addrs range 0xfffec000 - 0xfffeffff
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#define ESC_BIOS_CSA_HIGHBIOS 0x10 // Addrs range 0xffff0000 - 0xffffffff
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#define ESC_BIOS_CSA_ENLBIOS 0x20 // Addrs range 0xfff80000 - 0xfffdffff
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#define ESC_BIOS_CSA_ALLBIOS 0x3f // 512Kbytes 0xfff80000 - 0xffffffff
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#define ESC_BIOS_CSB_BIOSWREN 0x08 // Bios Write Enable
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#define ESC_PCI_EISA_CLK_33MHZ 0x00 // PCI Clk div of 33MHz for BCLK 8.33Mhz
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#define ESC_PCI_EISA_CLK_25MHZ 0x01 // PCI Clk div of 25MHz for BLCK 8.33Mhz
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#define ESC_PCI_EISA_MOUSE_INT 0x10 // Mouse interrupt
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#define ESC_PCI_EISA_PROC_ERR 0x20 // Co-Processor Error
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#define ESC_PERIPH_CSA_RTC 0x01 // Decode for Real Time Clock
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#define ESC_PERIPH_CSA_KBD 0x02 // Decode for Keyboard Controller
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#define ESC_PERIPH_CSA_FDC1 0x04 // Decode for Floppy Disk Controller
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#define ESC_PERIPH_CSA_FDC2 0x08 // Decode for Floppy Disk Controller
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#define ESC_PERIPH_CSA_SECNDARY 0x20 // Decode for Secondary addrs space
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#define ESC_PERIPH_CSB_SERA1 0x00 // Decode for Serial PortA - COM1
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#define ESC_PERIPH_CSB_SERA2 0x01 // Decode for Serial PortA - COM2
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#define ESC_PERIPH_CSB_SERA_DIS 0x03 // Decode for Serial PortA Disable
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#define ESC_PERIPH_CSB_SERB1 0x00 // Decode for Serial PortB - COM1
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#define ESC_PERIPH_CSB_SERB2 0x04 // Decode for Serial PortB - COM2
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#define ESC_PERIPH_CSB_SERB_DIS 0x0c // Decode for Serial PortB Disable
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#define ESC_PERIPH_CSB_LPT1 0x00 // Decode for Parallel Port1
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#define ESC_PERIPH_CSB_LPT2 0x10 // Decode for Parallel Port2
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#define ESC_PERIPH_CSB_LPT3 0x20 // Decode for Parallel Port3
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#define ESC_PERIPH_CSB_LPT_DIS 0x30 // Decode for Parallel Port Disable
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#define ESC_PERIPH_CSB_PORT92 0x40 // Decode for Port 92
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#define ESC_PERIPH_CSB_CRAM 0x80 // Decode for Cram
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#define ESC_MODE_SEL_EISAMSUPP0 0x00 // 4 EISA Masters, 4 slots, 4 PCI IRQ's
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#define ESC_MODE_SEL_EISAMSUPP1 0x01 // 6 EISA Masters, 2 slots, 2 PCI IRQ's
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#define ESC_MODE_SEL_EISAMSUPP2 0x02 // 7 EISA Masters, 1 slots, 1 PCI IRQ's
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#define ESC_MODE_SEL_EISAMSUPP3 0x03 // 8 EISA Masters, 0 slots, 0 PCI IRQ's
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#define ESC_MODE_SEL_SERR_NMIEN 0x08 // SERR# generated NMI enable
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#define ESC_MODE_SEL_GEN_CS 0x10 // General Purpose Chip selects
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#define ESC_MODE_SEL_CONFIG_RAD 0x20 // Configuration Ram Address
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#define ESC_GPXBC_XBUSOE0 0x01 // XBUSOE# Generation for GPCS0
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#define ESC_GPXBC_XBUSOE1 0x02 // XBUSOE# Generation for GPCS1
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#define ESC_GPXBC_XBUSOE2 0x04 // XBUSOE# Generation for GPCS2
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//
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// IRQ defines for PCI/EISA - PCI/ISA bridge devices.
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//
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#define IO_IRQ0 0
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#define IO_IRQ1 1
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#define IO_IRQ2 2
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#define IO_IRQ3 3
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#define IO_IRQ4 4
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#define IO_IRQ5 5
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#define IO_IRQ6 6
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#define IO_IRQ7 7
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#define IO_IRQ8 8
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#define IO_IRQ9 9
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#define IO_IRQ10 10
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#define IO_IRQ11 11
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#define IO_IRQ12 12
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#define IO_IRQ13 13
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#define IO_IRQ14 14
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#define IO_IRQ15 15
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#endif // _PCIEISA_
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