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140 lines
3.2 KiB
140 lines
3.2 KiB
//
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// Hal specific PCI bus structures
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//
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#define PCI_MAX_LOCAL_DEVICE 7
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#define PCI_MAX_BUS_NUMBER 31
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#define PCI_MAX_IO_ADDRESS 0x1FFFFFFF // (PCI_IO_PHYSICAL_BASE + 0x1FFFFFFF)
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#define PCI_MAX_MEMORY_ADDRESS 0x1FFFFFFF //(PCI_MEMORY_PHYSICAL_BASE + 0x1FFFFFFF)
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#define PCI_MAX_SPARSE_MEMORY_ADDRESS PCI_MAX_MEMORY_ADDRESS
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#define PCI_MIN_DENSE_MEMORY_ADDRESS PCI_MEMORY_PHYSICAL_BASE
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#define PCI_MAX_DENSE_MEMORY_ADDRESS PCI_MAX_MEMORY_ADDRESS
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#define PCI_MAX_INTERRUPT_VECTOR 0xF
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//
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// Values used to index both the
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// HalpPciConfigSelectDecodeTable[]
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// and HalpPCIPinToLineTable[].
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//
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#define PCI_ISA_DEVICE_NUMBER 0
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#define PCI_OBENET_DEVICE_NUMBER 1
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#define PCI_OBSCSI_DEVICE_NUMBER 2
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#define PCI_VID_DEVICE_NUMBER 3
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#define PCI_SLOT0_DEVICE_NUMBER 4
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#define PCI_SLOT1_DEVICE_NUMBER 5
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#define PCI_SLOT2_DEVICE_NUMBER 6
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#define PCI_PMP_DEVICE_NUMBER 7
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//
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// Define PCI slot validity
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//
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typedef enum _VALID_SLOT {
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InvalidBus = 0,
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InvalidSlot,
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ValidSlot
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} VALID_SLOT;
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//
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// New data structures for Hal Bus Extender API
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//
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typedef NTSTATUS
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(*PciIrqRange) (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER PciSlot,
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OUT PSUPPORTED_RANGE *Interrupt
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);
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typedef struct tagPCIPBUSDATA {
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//
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// Defined PCI data
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//
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PCIBUSDATA CommonData;
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//
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// Implementation specific data
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//
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union {
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struct {
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PULONG Address;
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ULONG Data;
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} Type1;
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struct {
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PUCHAR CSE;
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PUCHAR Forward;
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ULONG Base;
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} Type2;
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} Config;
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ULONG MaxDevice;
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PciIrqRange GetIrqRange;
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BOOLEAN BridgeConfigRead;
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UCHAR ParentBus;
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UCHAR reserved[2];
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UCHAR SwizzleIn[4];
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RTL_BITMAP DeviceConfigured;
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ULONG ConfiguredBits[PCI_MAX_DEVICES * PCI_MAX_FUNCTION / 32];
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} PCIPBUSDATA, *PPCIPBUSDATA;
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//
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// Macro used to determin if Type 0 or Type 1
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// device
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//
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#define PCI_CONFIG_TYPE(PciData) ((PciData)->HeaderType & ~PCI_MULTIFUNCTION)
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//
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// Define PciConfigAddr register structure
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//
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typedef struct _PCI_CONFIG_ADDR {
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ULONG Type : 1;
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ULONG Reserved2 : 7;
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ULONG FunctionNumber : 3;
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ULONG DeviceNumber : 5;
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ULONG BusNumber : 8;
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ULONG Reserved1 : 8;
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} PCI_CONFIG_ADDR, *PPCI_CONFIG_ADDR;
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//
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// Define PCI configuration cycle types.
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//
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typedef enum _PCI_CONFIGURATION_TYPES {
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PciConfigTypeInvalid = -1,
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PciConfigType0 = 0,
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PciConfigType1 = 1
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} PCI_CONFIGURATION_TYPES, *PPCI_CONFIGURATION_TYPES;
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//
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// Define PCI cycle/command types.
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//
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typedef enum _PCI_COMMAND_TYPES{
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PciCommandInterruptAcknowledge = 0x0,
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PciCommandSpecialCycle = 0x1,
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PciCommandIoRead = 0x2,
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PciCommandIoWrite = 0x3,
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PciCommandMemoryRead = 0x6,
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PciCommandMemoryWrite = 0x7,
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PciCommandConfigurationRead = 0xa,
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PciCommandConfigurationWrite = 0xb,
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PciCommandMemoryReadMultiple = 0xc,
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PciCommandDualAddressCycle = 0xd,
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PciCommandMemoryReadLine = 0xe,
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PciCommandMemoryWriteAndInvalidate = 0xf,
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MaximumPciCommand
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} PCI_COMMAND_TYPES, *PPCI_COMMAND_TYPES;
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//
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// PCI platform-specific functions
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//
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