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447 lines
11 KiB
447 lines
11 KiB
/*++
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Copyright (c) 1993 NeTpower Incorporated
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Module Name:
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sidewinder.h
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Abstract:
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This module is the header file that describes hardware
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structure for sections of the SideWinder device. The
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contents of this device includes the realtime clock,
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keyboard controller, serial ports, parallel port,
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floppy controller and nvram.
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Author:
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Hector R. Briones 15-Dec-93
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Revision History:
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--*/
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#ifndef _SIDEWINDER_
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#define _SIDEWINDER_
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//
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//------------REALTIME CLOCK - (RTC)-----------------------------------
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//
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// Define Realtime Clock register numbers.
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//
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#define RTC_SECOND 0 // second of minute [0..59]
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#define RTC_SECOND_ALARM 1 // seconds to alarm
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#define RTC_MINUTE 2 // minute of hour [0..59]
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#define RTC_MINUTE_ALARM 3 // minutes to alarm
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#define RTC_HOUR 4 // hour of day [0..23]
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#define RTC_HOUR_ALARM 5 // hours to alarm
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#define RTC_DAY_OF_WEEK 6 // day of week [1..7]
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#define RTC_DAY_OF_MONTH 7 // day of month [1..31]
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#define RTC_MONTH 8 // month of year [1..12]
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#define RTC_YEAR 9 // year [00..99]
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#define RTC_CONTROL_REGISTERA 10 // control register A
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#define RTC_CONTROL_REGISTERB 11 // control register B
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#define RTC_CONTROL_REGISTERC 12 // control register C
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#define RTC_CONTROL_REGISTERD 13 // control register D
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#define RTC_BATTERY_BACKED_UP_RAM 14 // battery backed up RAM [0..49]
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#ifndef _LANGUAGE_ASSEMBLY
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//
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// Define Control Register A structure.
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//
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typedef struct _RTC_CONTROL_REGISTER_A {
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UCHAR RateSelect : 4;
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UCHAR TimebaseDivisor : 3;
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UCHAR UpdateInProgress : 1;
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} RTC_CONTROL_REGISTER_A, *PRTC_CONTROL_REGISTER_A;
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//
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// Define Control Register B structure.
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//
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typedef struct _RTC_CONTROL_REGISTER_B {
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UCHAR DayLightSavingsEnable : 1;
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UCHAR HoursFormat : 1;
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UCHAR DataMode : 1;
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UCHAR SquareWaveEnable : 1;
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UCHAR UpdateInterruptEnable : 1;
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UCHAR AlarmInterruptEnable : 1;
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UCHAR TimerInterruptEnable : 1;
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UCHAR SetTime : 1;
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} RTC_CONTROL_REGISTER_B, *PRTC_CONTROL_REGISTER_B;
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//
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// Define Control Register C structure.
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//
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typedef struct _RTC_CONTROL_REGISTER_C {
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UCHAR Fill : 4;
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UCHAR UpdateInterruptFlag : 1;
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UCHAR AlarmInterruptFlag : 1;
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UCHAR TimeInterruptFlag : 1;
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UCHAR InterruptRequest : 1;
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} RTC_CONTROL_REGISTER_C, *PRTC_CONTROL_REGISTER_C;
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//
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// Define Control Register D structure.
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//
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typedef struct _RTC_CONTROL_REGISTER_D {
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UCHAR Fill : 7;
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UCHAR ValidTime : 1;
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} RTC_CONTROL_REGISTER_D, *PRTC_CONTROL_REGISTER_D;
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//
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//------------SERIAL PORTS - (DUAL UART's)----------------------
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//
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// Define serial port read registers structure.
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//
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typedef struct _SP_READ_REGISTERS {
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UCHAR ReceiveBuffer;
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UCHAR InterruptEnable;
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UCHAR InterruptId;
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UCHAR LineControl;
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UCHAR ModemControl;
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UCHAR LineStatus;
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UCHAR ModemStatus;
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UCHAR ScratchPad;
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} SP_READ_REGISTERS, *PSP_READ_REGISTERS;
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//
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// Define define serial port write registers structure.
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//
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typedef struct _SP_WRITE_REGISTERS {
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UCHAR TransmitBuffer;
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UCHAR InterruptEnable;
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UCHAR FifoControl;
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UCHAR LineControl;
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UCHAR ModemControl;
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UCHAR Reserved1;
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UCHAR ModemStatus;
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UCHAR ScratchPad;
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} SP_WRITE_REGISTERS, *PSP_WRITE_REGISTERS;
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//
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// Define serial port interrupt enable register structure.
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//
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typedef struct _SP_INTERRUPT_ENABLE {
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UCHAR ReceiveEnable : 1;
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UCHAR TransmitEnable : 1;
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UCHAR LineStatusEnable : 1;
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UCHAR ModemStatusEnable : 1;
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UCHAR Reserved1 : 4;
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} SP_INTERRUPT_ENABLE, *PSP_INTERRUPT_ENABLE;
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//
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// Define serial port interrupt id register structure.
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//
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typedef struct _SP_INTERRUPT_ID {
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UCHAR InterruptPending : 1;
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UCHAR Identification : 3;
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UCHAR Reserved1 : 2;
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UCHAR FifoEnabled : 2;
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} SP_INTERRUPT_ID, *PSP_INTERRUPT_ID;
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//
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// Define serial port fifo control register structure.
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//
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typedef struct _SP_FIFO_CONTROL {
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UCHAR FifoEnable : 1;
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UCHAR ReceiveFifoReset : 1;
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UCHAR TransmitFifoReset : 1;
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UCHAR DmaModeSelect : 1;
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UCHAR Reserved1 : 2;
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UCHAR ReceiveFifoLevel : 2;
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} SP_FIFO_CONTROL, *PSP_FIFO_CONTROL;
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//
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// Define serial port line control register structure.
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//
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typedef struct _SP_LINE_CONTROL {
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UCHAR CharacterSize : 2;
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UCHAR StopBits : 1;
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UCHAR ParityEnable : 1;
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UCHAR EvenParity : 1;
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UCHAR StickParity : 1;
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UCHAR SetBreak : 1;
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UCHAR DivisorLatch : 1;
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} SP_LINE_CONTROL, *PSP_LINE_CONTROL;
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#endif // _LANGUAGE_ASSEMBLY
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//
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// Line status register character size definitions.
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//
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#define FIVE_BITS 0x0 // five bits per character
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#define SIX_BITS 0x1 // six bits per character
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#define SEVEN_BITS 0x2 // seven bits per character
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#define EIGHT_BITS 0x3 // eight bits per character
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//
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// Line speed divisor definition.
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//
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#define BAUD_RATE_9600 12 // divisor for 9600 baud
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#define BAUD_RATE_19200 6 // divisor for 19200 baud
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#ifndef _LANGUAGE_ASSEMBLY
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//
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// Define serial port modem control register structure.
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//
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typedef struct _SP_MODEM_CONTROL {
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UCHAR DataTerminalReady : 1;
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UCHAR RequestToSend : 1;
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UCHAR Reserved1 : 1;
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UCHAR Interrupt : 1;
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UCHAR loopBack : 1;
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UCHAR Reserved2 : 3;
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} SP_MODEM_CONTROL, *PSP_MODEM_CONTROL;
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//
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// Define serial port line status register structure.
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//
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typedef struct _SP_LINE_STATUS {
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UCHAR DataReady : 1;
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UCHAR OverrunError : 1;
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UCHAR ParityError : 1;
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UCHAR FramingError : 1;
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UCHAR BreakIndicator : 1;
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UCHAR TransmitHoldingEmpty : 1;
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UCHAR TransmitEmpty : 1;
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UCHAR ReceiveFifoError : 1;
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} SP_LINE_STATUS, *PSP_LINE_STATUS;
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//
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// Define serial port modem status register structure.
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//
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typedef struct _SP_MODEM_STATUS {
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UCHAR DeltaClearToSend : 1;
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UCHAR DeltaDataSetReady : 1;
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UCHAR TrailingRingIndicator : 1;
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UCHAR DeltaReceiveDetect : 1;
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UCHAR ClearToSend : 1;
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UCHAR DataSetReady : 1;
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UCHAR RingIndicator : 1;
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UCHAR ReceiveDetect : 1;
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} SP_MODEM_STATUS, *PSP_MODEM_STATUS;
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//
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//-------------------SUPER IO control----------------------------
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//
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//
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// SIDEWINDER Index and Data Registers
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//
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typedef struct _SUPERIO_CONFIG_REGISTERS {
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UCHAR Index;
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UCHAR Data;
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} SUPERIO_CONFIG_REGISTERS, *PSUPERIO_CONFIG_REGISTERS;
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#endif // LANGUAGE_ASSEMBLY
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#define SUPERIO_INDEX_REG (SIDEWINDER_VIRTUAL_BASE + 0x398)
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#define SUPERIO_DATA_REG (SIDEWINDER_VIRTUAL_BASE + 0x399)
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//
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// SideWinder Configuration registers
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//
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#define SUPERIO_FER_INDEX 0x0
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#define SUPERIO_FAR_INDEX 0x1
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#define SUPERIO_PTR_INDEX 0x2
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#define SUPERIO_FCR_INDEX 0x3
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#define SUPERIO_PCR_INDEX 0x4
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#define SIO_INDEX_REG 0x398
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#define SIO_DATA_REG 0x399
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//
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// KRR register index and
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// bit definitions
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//
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#define SUPERIO_KRR_INDEX 0x05
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#define SUPERIO_KRR_KBCE 0x01
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#define SUPERIO_KRR_PAE 0x04
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#define SUPERIO_KRR_RTCTEST 0x10
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#define SUPERIO_KRR_RAMU128B 0x20
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#define SUPERIO_KRR_ADE 0x40
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#define SUPERIO_KRR_RTCE 0x08
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//
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// New register definitions in the latest spec
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// from NATIONAL - February 1994
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//
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#define SUPERIO_PMC_INDEX 0x06
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#define SUPERIO_TUPP_INDEX 0x07
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#define SUPERIO_SIOID_INDEX 0x08
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#define SUPERIO_ASIOC_INDEX 0x09
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#define SUPERIO_CS0R0_INDEX 0x0a
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#define SUPERIO_CS0R1_INDEX 0x0b
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#define SUPERIO_CS1R0_INDEX 0x0c
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#define SUPERIO_CS1R1_INDEX 0x0d
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//
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// Real-time clock (RTC) index
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// and data register definitions
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//
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#define RTC_INDEX_REG 0x70
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#define RTC_DATA_REG 0x71
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//
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// RTC register A index and
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// bit definitions
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//
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#define RTC_REGA_INDEX 0x0A
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#define RTC_REGA_UIP 0x80
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#define RTC_REGA_DV2 0x40
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#define RTC_REGA_DV1 0x20
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#define RTC_REGA_DV0 0x10
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#define RTC_REGA_RS3 0x08
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#define RTC_REGA_RS2 0x04
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#define RTC_REGA_RS1 0x02
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#define RTC_REGA_RS0 0x01
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//
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// RTC register B index and
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// bit definitions
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//
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#define RTC_REGB_INDEX 0x0B
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#define RTC_REGB_SET 0x80
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#define RTC_REGB_PIE 0x40
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#define RTC_REGB_AIE 0x20
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#define RTC_REGB_UIE 0x10
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#define RTC_REGB_SWE 0x08
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#define RTC_REGB_DM 0x04
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#define RTC_REGB_24_12 0x02
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#define RTC_REGB_DSE 0x01
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//
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// RTC register C index and
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// bit definitions
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//
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#define RTC_REGC_INDEX 0x0C
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#define RTC_REGC_IRQF 0x80
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#define RTC_REGC_PF 0x40
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#define RTC_REGB_AF 0x20
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#define RTC_REGB_UF 0x10
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//
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// RTC register D index and
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// bit definitions
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//
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#define RTC_REGD_INDEX 0x0D
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#define RTC_REGD_VRT 0x80
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//
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// SideWinder Function Enable Register (FER) bit definitions
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//
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#define SUPERIO_FER_LPT_EN 0x1
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#define SUPERIO_FER_UART1_EN 0x2
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#define SUPERIO_FER_UART2_EN 0x4
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#define SUPERIO_FER_FDC_EN 0x8
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#define SUPERIO_FER_ENABLEALL 0xf // Enable LPT, UART1, UART2 & FDC Primary address= 0x3F0-0x3F7
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//
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// SideWinder Function Address Register (FAR) bit definitions
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//
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#define SUPERIO_FAR_LPT1_ADDR 0x1 // LPT1 Address: 0x3BC - 0x3BE
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#define SUPERIO_FAR_LPT2_ADDR 0x0
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#define SUPERIO_FAR_LPT3_ADDR 0x2
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#define SUPERIO_FAR_UART_PRI_ADDR 0x10 // UART1 Address: 0x3F8-0x3FF/UART2 Address: 0x2F8-0x2FF
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#define SUPERIO_FAR_UART1_MASK 0x0C
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#define SUPERIO_FAR_UART1_COM1 0x00
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#define SUPERIO_FAR_UART1_COM2 0x04
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#define SUPERIO_FAR_UART1_COM3 0x08
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#define SUPERIO_FAR_UART1_COM4 0x0C
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#define SUPERIO_FAR_UART2_MASK 0x30
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#define SUPERIO_FAR_UART2_COM1 0x00
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#define SUPERIO_FAR_UART2_COM2 0x10
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#define SUPERIO_FAR_UART2_COM3 0x20
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#define SUPERIO_FAR_UART2_COM4 0x30
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#define SUPERIO_FAR_COM34_ADDR_MASK 0xC0
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//
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// Sidewinder Function Enable Register (PTR) bit definitions
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//
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#define SUPERIO_PTR_ENABLE_OSC 0x4
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//
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//---------------SERIAL PORT 1 -- (UART)-----------------------
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//
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// Define serial port register addresses
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//
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#define SP0_RECEIVEBUFFER COMPORT1_VIRTUAL_BASE
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#define SP0_TRANSMITBUFFER COMPORT1_VIRTUAL_BASE
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#define SP0_INTERRUPTENABLE (COMPORT1_VIRTUAL_BASE + 1)
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#define SP0_INTERRUPTID (COMPORT1_VIRTUAL_BASE + 2)
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#define SP0_FIFOCONTROL (COMPORT1_VIRTUAL_BASE + 2)
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#define SP0_LINECONTROL (COMPORT1_VIRTUAL_BASE + 3)
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#define SP0_MODEMCONTROL (COMPORT1_VIRTUAL_BASE + 4)
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#define SP0_LINESTATUS (COMPORT1_VIRTUAL_BASE + 5)
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#define SP0_MODEMSTATUS (COMPORT1_VIRTUAL_BASE + 6)
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#define SP0_SCRATCHPAD (COMPORT1_VIRTUAL_BASE + 7)
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#define SP0_DIVLATCHLSB (COMPORT1_VIRTUAL_BASE + 8)
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#define SP0_DIVLATCHMSB (COMPORT1_VIRTUAL_BASE + 9)
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//
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//---------------SERIAL PORT 2 -- (UART)-----------------------
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//
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// Define serial port register addresses
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//
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#define SP1_RECEIVEBUFFER COMPORT2_VIRTUAL_BASE
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#define SP1_TRANSMITBUFFER COMPORT2_VIRTUAL_BASE
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#define SP1_INTERRUPTENABLE (COMPORT2_VIRTUAL_BASE + 1)
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#define SP1_INTERRUPTID (COMPORT2_VIRTUAL_BASE + 2)
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#define SP1_FIFOCONTROL (COMPORT2_VIRTUAL_BASE + 2)
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#define SP1_LINECONTROL (COMPORT2_VIRTUAL_BASE + 3)
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#define SP1_MODEMCONTROL (COMPORT2_VIRTUAL_BASE + 4)
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#define SP1_LINESTATUS (COMPORT2_VIRTUAL_BASE + 5)
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#define SP1_MODEMSTATUS (COMPORT2_VIRTUAL_BASE + 6)
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#define SP1_SCRATCHPAD (COMPORT2_VIRTUAL_BASE + 7)
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#define SP1_DIVLATCHLSB COMPORT2_VIRTUAL_BASE
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#define SP1_DIVLATCHMSB (COMPORT2_VIRTUAL_BASE + 1)
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#define SP_LINECNTRL_DIVLAT_EN 0x80 // Divisor Latch bit
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#define SP_LINESTATUS_RXRDY 0x01 // Rx Ready (Rx Buffer full)
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#define SP_LINESTATUS_TXRDY 0x40 // Tx Ready (Tx buffer empty)
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#define SP_FIFOCNTRL_ENABLE 0x01 // Enable Rx and Tx Fifo
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#define SP_FIFOCNTRL_RXRST 0x02 // Rx Fifo reset
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#define SP_FIFOCNTRL_TXRST 0x04 // Tx Fifo reset
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#define SP_MODEMCNTRL_DTR 0x01 // DataTerminalReady
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#define SP_MODEMCNTRL_RTS 0x02 // RequestToSend
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//
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// Temporary defines (Don't know where to put them yet...)
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//
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#define ASCLF 0xa
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#define ASCCR 0xd
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#define ASCNUL 0x0
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#endif //_SIDEWINDER_
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