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166 lines
3.8 KiB
166 lines
3.8 KiB
;++
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; Copyright (c) 1989 Microsoft Corporation
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;
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; Module Name:
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;
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; olimp.inc
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;
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; Abstract:
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;
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; LSX5030 MP include file
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;
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; Author:
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;
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; Bruno Sartirana (o-obruno) 3-Mar-92
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;
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;--
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;*****************************
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; Olivetti LSX5030 defines
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;
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MAX_NUMBER_PROCESSORS_MASK equ 0fh ; Maximum number of processors
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; bitmask
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MAX_NUMBER_PROCESSORS equ 4 ; Maximum number of processors
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RESET_WO_EOI equ 00ah ; Reset with out EOI
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WarmResetVector equ 467h ; warm reset vector in ROM data segment
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; Multi-Processor Control and Configuration Registers I/O Locations:
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PCR_Px equ 0c6ah ; control register offset
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;LEV2_CACHE_REG equ 0c94h ; level 2 cache register offset
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P0_SLOT equ 00000h
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P1_SLOT equ 0c000h
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P2_SLOT equ 0d000h
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P3_SLOT equ 0e000h
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Px_SLOT_MASK equ 0f000h
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PCR_P0 equ P0_SLOT + PCR_Px
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PCR_P1 equ P1_SLOT + PCR_Px
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PCR_P2 equ P2_SLOT + PCR_Px
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PCR_P3 equ P3_SLOT + PCR_Px
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; WHO AM I Register
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PROC_ID_PORT equ 0c70h ; who am I
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; Multi-Processor Control Register Bit Definitions:
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IPI_EN equ 080h ; Inter-Processor Interrupt Enable bit
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PINT equ 040h ; Inter-Processor Interrupt bit
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IPI_IRQ10 equ 008h ; Inter-processor-interrupt vectors
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IPI_IRQ11 equ 004h
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IPI_IRQ13 equ 00ch
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IPI_IRQ15 equ 000h
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RESET equ 001h ; RESET processor bit (1-0 transition
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; Multi-Processor 2nd Level Cache Policy Registers Bit Definitions
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;LEV2_CACHE_ON equ 80h ; 2nd level cache enable bit
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;
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; The kernel leaves some space (64 byte) of the PCR for the HAL to use
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; as it needs. Currently this space is used for some efficiency in
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; some of the MP specific code and is highly implementation
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; dependant.
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;
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PcrE struc
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PcrControlPort dw 0 ; Processor's control port
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PcrNumber db 0 ; Processor's number
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PcrE ends
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cr equ 0ah
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lf equ 0dh
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;
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; Constants used to initialize CMOS/Real Time Clock
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;
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CMOS_CONTROL_PORT equ 70h ; command port for cmos
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CMOS_DATA_PORT equ 71h ; cmos data port
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CMOS_GET_MP_STATUS equ 36h ; offset for MP status
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;
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; Macros to Read/Write/Reset CMOS
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;
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; CMOS_READ
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;
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; Description: This macro read a byte from the CMOS register specified
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; in (AL).
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;
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; Parameter: (AL) = address/register to read
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; Return: (AL) = data
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;
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CMOS_READ macro
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out CMOS_CONTROL_PORT, al ; ADDRESS LOCATION AND DISABLE NMI
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IODelay ; I/O DELAY
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in al, CMOS_DATA_PORT ; READ IN REQUESTED CMOS DATA
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IODelay ; I/O DELAY
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endm
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;++
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;
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; DBG_DISPLAY DisplayCode
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;
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; Macro Description:
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;
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; This macro writes 'DisplayCode' to the parallel port, where a LED
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; display can be plugged in to show such a code.
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; In order to allow the user to read the code on the LED display,
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; after writing, a delay is introduced.
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;
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; Arguments:
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; DisplayCode - Byte to write to the parallel port
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;
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;
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;--
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DBG_DISPLAY macro DisplayCode
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ifdef HALOLI_DBG
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push eax
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push edx
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; signal something on the parallel port
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mov dx, 378h
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mov al, DisplayCode
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out dx, al
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mov eax, DbgDelay
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@@:
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dec eax
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cmp eax, 0
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jne @b
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pop edx
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pop eax
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endif ; HALOLI_DBG
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endm
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;*****************************
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; end of list
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