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386 lines
10 KiB
386 lines
10 KiB
;++
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;
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;Copyright (c) 1991 Microsoft Corporation
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;
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;Module Name:
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;
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; olisyint.asm
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;
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;Abstract:
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;
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; This module implements the HAL routines to enable/disable system
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; interrupts, for the MP systempro implementation
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;
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;Author:
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;
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; John Vert (jvert) 22-Jul-1991
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;
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;Environment:
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;
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; Kernel Mode
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;
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;Revision History:
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;
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; Bruno Sartirana (o-obruno) 3-Mar-92
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; Added support for the Olivetti LSX5030.
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;
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;--
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.386p
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.xlist
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include hal386.inc
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include callconv.inc
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include i386\ix8259.inc
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include i386\kimacro.inc
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include mac386.inc
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;LSX5030 start
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include i386\olimp.inc
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;LSX5030 end
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.list
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extrn KiI8259MaskTable:DWORD
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EXTRNP _KeBugCheck,1,IMPORT
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;
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; Constants used to initialize CMOS/Real Time Clock
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;
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CMOS_CONTROL_PORT EQU 70h ; command port for cmos
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CMOS_DATA_PORT EQU 71h ; cmos data port
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;
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; Macros to Read/Write/Reset CMOS to initialize RTC
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;
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; CMOS_READ
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;
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; Description: This macro read a byte from the CMOS register specified
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; in (AL).
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;
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; Parameter: (AL) = address/register to read
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; Return: (AL) = data
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;
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CMOS_READ MACRO
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OUT CMOS_CONTROL_PORT,al ; ADDRESS LOCATION AND DISABLE NMI
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IODelay ; I/O DELAY
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IN AL,CMOS_DATA_PORT ; READ IN REQUESTED CMOS DATA
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IODelay ; I/O DELAY
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ENDM
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_DATA SEGMENT DWORD PUBLIC 'DATA'
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align dword
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;
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; HalDismissSystemInterrupt does an indirect jump through this table so it
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; can quickly execute specific code for different interrupts.
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;
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public HalpSpecialDismissTable
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HalpSpecialDismissTable label dword
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dd offset FLAT:HalpDismissNormal ; irq 0
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dd offset FLAT:HalpDismissNormal ; irq 1
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dd offset FLAT:HalpDismissNormal ; irq 2
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dd offset FLAT:HalpDismissNormal ; irq 3
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dd offset FLAT:HalpDismissNormal ; irq 4
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dd offset FLAT:HalpDismissNormal ; irq 5
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dd offset FLAT:HalpDismissNormal ; irq 6
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dd offset FLAT:HalpDismissIrq07 ; irq 7
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dd offset FLAT:HalpDismissNormal ; irq 8
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dd offset FLAT:HalpDismissNormal ; irq 9
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dd offset FLAT:HalpDismissNormal ; irq A
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dd offset FLAT:HalpDismissNormal ; irq B
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dd offset FLAT:HalpDismissNormal ; irq C
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dd offset FLAT:HalpDismissNormal ; irq D
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dd offset FLAT:HalpDismissNormal ; irq E
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dd offset FLAT:HalpDismissIrq0f ; irq F
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dd offset FLAT:HalpDismissNormal ; irq 10
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dd offset FLAT:HalpDismissNormal ; irq 11
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dd offset FLAT:HalpDismissNormal ; irq 12
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dd offset FLAT:HalpDismissNormal ; irq 13
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dd offset FLAT:HalpDismissNormal ; irq 14
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dd offset FLAT:HalpDismissNormal ; irq 15
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dd offset FLAT:HalpDismissNormal ; irq 16
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dd offset FLAT:HalpDismissNormal ; irq 17
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dd offset FLAT:HalpDismissNormal ; irq 18
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dd offset FLAT:HalpDismissNormal ; irq 19
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dd offset FLAT:HalpDismissNormal ; irq 1A
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dd offset FLAT:HalpDismissNormal ; irq 1B
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dd offset FLAT:HalpDismissNormal ; irq 1C
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dd offset FLAT:HalpDismissNormal ; irq 1D
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dd offset FLAT:HalpDismissNormal ; irq 1E
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dd offset FLAT:HalpDismissNormal ; irq 1F
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dd offset FLAT:HalpDismissNormal ; irq 20
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dd offset FLAT:HalpDismissNormal ; irq 21
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dd offset FLAT:HalpDismissNormal ; irq 22
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dd offset FLAT:HalpDismissNormal ; irq 23
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_DATA ENDS
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_TEXT SEGMENT DWORD PUBLIC 'CODE'
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ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
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;++
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;BOOLEAN
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;HalBeginSystemInterrupt(
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; IN KIRQL Irql
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; IN CCHAR Vector,
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; OUT PKIRQL OldIrql
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; )
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;
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;
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;
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;Routine Description:
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;
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; This routine is used to dismiss the specified vector number. It is called
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; before any interrupt service routine code is executed.
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;
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; N.B. This routine does NOT preserve EAX or EBX
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;
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;
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;Arguments:
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;
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; Irql - Supplies the IRQL to raise to
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;
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; Vector - Supplies the vector of the interrupt to be dismissed
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;
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; OldIrql- Location to return OldIrql
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;
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;
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;Return Value:
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;
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; FALSE - Interrupt is spurious and should be ignored
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;
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; TRUE - Interrupt successfully dismissed and Irql raised.
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;
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;--
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align dword
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HbsiIrql equ byte ptr [esp+4]
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HbsiVector equ byte ptr [esp+8]
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HbsiOldIrql equ dword ptr [esp+12]
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cPublicProc _HalBeginSystemInterrupt,3
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movzx ebx,HbsiVector ; (ebx) = System Vector
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sub ebx, PRIMARY_VECTOR_BASE ; (ebx) = 8259 IRQ #
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cmp ebx, 24h ; Interrupt in table?
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jnc hbsi00 ; no go handle
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jmp HalpSpecialDismissTable[ebx*4]
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hbsi00:
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;
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; Interrupt is out of range. There's no EOI here since it wouldn't
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; have been out of range if it occured on either interrupt controller
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; which is known about.
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;
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mov eax,0 ; return FALSE
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stdRET _HalBeginSystemInterrupt
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HalpDismissIrq0f:
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;
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; Check to see if this is a spurious interrupt
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;
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mov al, OCW3_READ_ISR ; tell 8259 we want to read ISR
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out PIC2_PORT0, al
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IODelay ; delay
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in al, PIC2_PORT0 ; (al) = content of PIC 1 ISR
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test al, 10000000B ; Is In-Service register set?
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jnz short HalpDismissNormal ; No, this is NOT a spurious int,
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; go do the normal interrupt stuff
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;
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; This is a spurious interrupt.
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; Because the slave PIC is cascaded to irq2 of master PIC, we need to
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; dismiss the interupt on master PIC's irq2.
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;
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mov al, PIC2_EOI ; Specific eoi to master for pic2 eoi
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out PIC1_PORT0, al ; send irq2 specific eoi to master
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mov eax,0 ; return FALSE
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stdRET _HalBeginSystemInterrupt
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HalpDismissIrq07:
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;
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; Check to see if this is a spurious interrupt
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;
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mov al, OCW3_READ_ISR ; tell 8259 we want to read ISR
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out PIC1_PORT0, al
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IODelay ; delay
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in al, PIC1_PORT0 ; (al) = content of PIC 1 ISR
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test al, 10000000B ; Is In-Service register set?
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jnz short HalpDismissNormal ; No, so this is NOT a spurious int
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mov eax, 0 ; return FALSE
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stdRET _HalBeginSystemInterrupt
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HalpDismissNormal:
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;
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; Store OldIrql
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;
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mov eax, HbsiOldIrql
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movzx ecx, byte ptr fs:PcIrql
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mov byte ptr [eax], cl
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;
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; Raise IRQL to requested level
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;
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movzx eax, HbsiIrql ; (eax) = irql
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; (ebx) = IRQ #
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mov fs:PcIrql, al ; set new Irql
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mov eax, KiI8259MaskTable[eax*4] ; get 8259's masks
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or eax, fs:PcIDR ; mask disabled irqs
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SET_8259_MASK ; send mask to 8259s
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;
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; Dismiss interrupt. Current interrupt is already masked off.
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;
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mov eax, ebx ; (eax) = IRQ #
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cmp eax, 8 ; EOI to master or slave?
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jae short Hbsi100 ; EIO to both master and slave
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or al, PIC1_EOI_MASK ; create specific eoi mask for master
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out PIC1_PORT0, al ; dismiss the interrupt
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jmp short Hbsi200 ; IO delay
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Hbsi100:
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mov al, OCW2_NON_SPECIFIC_EOI ; send non specific eoi to slave
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out PIC2_PORT0, al
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mov al, PIC2_EOI ; specific eoi to master for pic2 eoi
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out PIC1_PORT0, al ; send irq2 specific eoi to master
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Hbsi200:
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PIC1DELAY
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sti
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mov eax, 1 ; return TRUE, interrupt dismissed
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stdRET _HalBeginSystemInterrupt
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stdENDP _HalBeginSystemInterrupt
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;++
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;VOID
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;HalDisableSystemInterrupt(
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; IN CCHAR Vector,
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; IN KIRQL Irql
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; )
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;
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;
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;
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;Routine Description:
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;
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; Disables a system interrupt.
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;
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;Arguments:
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;
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; Vector - Supplies the vector of the interrupt to be disabled
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;
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; Irql - Supplies the interrupt level of the interrupt to be disabled
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;
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;Return Value:
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;
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; None.
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;
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;--
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cPublicProc _HalDisableSystemInterrupt,2
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;
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movzx ecx, byte ptr [esp+4] ; (ecx) = Vector
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sub ecx, PRIMARY_VECTOR_BASE ; (ecx) = 8259 irq #
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mov edx, 1
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shl edx, cl ; (ebx) = bit in IMR to disable
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cli
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or fs:PcIDR, edx
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xor eax, eax
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;
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; Get the current interrupt mask register from the 8259
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;
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in al, PIC2_PORT1
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shl eax, 8
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in al, PIC1_PORT1
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;
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; Mask off the interrupt to be disabled
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;
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or eax, edx
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;
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; Write the new interrupt mask register back to the 8259
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;
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out PIC1_PORT1, al
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shr eax, 8
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out PIC2_PORT1, al
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PIC2DELAY
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sti
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stdRET _HalDisableSystemInterrupt
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stdENDP _HalDisableSystemInterrupt
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;++
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;
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;BOOLEAN
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;HalEnableSystemInterrupt(
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; IN ULONG Vector,
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; IN KIRQL Irql,
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; IN KINTERRUPT_MODE InterruptMode
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; )
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;
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;
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;Routine Description:
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;
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; Enables a system interrupt
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;
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;Arguments:
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;
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; Vector - Supplies the vector of the interrupt to be enabled
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;
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; Irql - Supplies the interrupt level of the interrupt to be enabled.
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;
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;Return Value:
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;
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; None.
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;
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;--
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cPublicProc _HalEnableSystemInterrupt,3
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movzx ecx, byte ptr [esp+4] ; (ecx) = vector
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sub ecx, PRIMARY_VECTOR_BASE
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jc hes_error
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cmp ecx, CLOCK2_LEVEL
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jnc hes_error
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mov eax, 1
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shl eax, cl ; (ebx) = bit in IMR to enable
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not eax
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cli
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and fs:PcIDR, eax
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;
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; Get the PIC masks for the current Irql
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;
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movzx eax, byte ptr fs:PcIrql
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mov eax, KiI8259MaskTable[eax*4]
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or eax, fs:PcIDR
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;
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; Write the new interrupt mask register back to the 8259
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;
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SET_8259_MASK
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sti
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mov eax, 1 ; return TRUE
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stdRET _HalEnableSystemInterrupt
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hes_error:
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if DBG
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int 3
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endif
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xor eax, eax ; FALSE
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stdRET _HalEnableSystemInterrupt
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stdENDP _HalEnableSystemInterrupt
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_TEXT ENDS
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END
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