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121 lines
5.2 KiB
121 lines
5.2 KiB
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#ifndef _H_BLFW
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#define _H_BLFW
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extern VOID Eieio ( VOID );
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#define BL_EIEIO __builtin_eieio()
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#define HIGH(a) (UCHAR)(((a)>>8) & 0xff)
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#define LOW(a) (UCHAR)((a) & 0xff)
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/******************************************************************************
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* *
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* The following identifies the monitor structures and definitions *
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* *
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******************************************************************************/
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//
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// Operating modes (8bit only for ARC and HAL)
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//
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typedef enum _BL_MODES
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{
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m640_480_8_60, // Not used
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m800_600_8_60, // Default for 1010 ID (SS)
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m1024_768_8_60, // Not used
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m1024_768_8_70, // Default for H010 ID (SS)
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m1280_1024_8_60, // Default for 0100 ID (SOG)
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m1280_1024_8_67, // Default for 0111 ID (SS)
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m1280_1024_8_72 // Default for V111 ID (SOG)
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} BL_MODES;
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#define BL_NUM_CRT_CTRL_REC_STRUCTS 7
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//
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// Monitor ID (cable) values
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//
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#define BL_MT_04 0x04 // 0100
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#define BL_MT_07 0x07 // 0111
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#define BL_MT_0A 0x0A // 1010
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#define BL_MT_0F 0x0F // 1111
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#define BL_MT_1A 0x1A // H010
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#define BL_MT_17 0x17 // V111
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#define BL_MT_MASK 0x1F // Monitor ID mask
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// CRT information structure
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typedef struct _bl_crt_ctrl_rec_t {
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ULONG mode; // Mode for this crt ctrl rec
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USHORT MonID; // Monitor ID
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USHORT width; // Number of pixels along the X axis
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USHORT height; // Number of pixels along the Y axis
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ULONG refresh; // Refresh rate
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UCHAR pll_ref_divide; // RAMDAC video PLL ref divide
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UCHAR pll_mult; // RAMDAC video PLL multiplier
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UCHAR pll_output_divide; // RAMDAC video PLL output divide
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UCHAR pll_ctrl; // RAMDAC video PLL control
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UCHAR sync_ctrl; // RAMDAC sync control
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ULONG crt_cntl_reg; // PRISM DTG control reg
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ULONG hrz_total_reg; // PRISM he reg (pixels)
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ULONG hrz_dsp_end_reg; // PRISM hde reg (pixels)
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ULONG hsync_start_reg; // PRISM hss reg (pixels)
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ULONG hsync_end1_reg; // PRISM hse1 reg (pixels)
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ULONG hsync_end2_reg; // PRISM hse2 reg (pixels)
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ULONG vrt_total_reg; // PRISM ve reg (scan lines)
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ULONG vrt_dsp_end_reg; // PRISM vde reg (scan lines)
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ULONG vsync_start_reg; // PRISM vss reg (scan lines)
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ULONG vsync_end_reg; // PRISM vse reg (scan lines)
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} bl_crt_ctrl_rec_t;
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// Adapter control record structure
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typedef struct _bl_adapter_ctrl_rec_t {
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USHORT vram; // Amount of VRAM for frame buffer
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USHORT width; // Number of pixels along the X axis
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USHORT height; // Number of pixels along the Y axis
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// PRISM registers
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ULONG PRISM_cfg; // cfg reg
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ULONG mem_cfg; // memory cfg reg
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ULONG DTG_ctrl; // DTG control reg
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// RAMDAC registers
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UCHAR pix_ctrl0; // 07:00 pix ctrl
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UCHAR pix_ctrl1; // 15:08 pix ctrl
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UCHAR pix_ctrl2; // 23:16 pix ctrl
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UCHAR pix_ctrl3; // 31:24 pix ctrl
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UCHAR wid_ctrl0; // 3:0 WID ctrl
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UCHAR wid_ctrl1; // 7:4 WID ctrl
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UCHAR serial_mode_ctrl; // serial mode
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UCHAR pix_interleave; // pixel interleave
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UCHAR misc_cfg; // misc ctrl
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UCHAR vram_mask_0; // vram mask reg 0
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UCHAR vram_mask_1; // vram mask reg 1
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UCHAR vram_mask_2; // vram mask reg 2
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} bl_adapter_ctrl_rec_t;
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// Adapter model record structure
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typedef struct bl_adapter_model_rec_t {
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ULONG devvend_id; // PCI device id
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ULONG strapping; // configuration strapping
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UCHAR prism_rev; // prism chip revision ID
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UCHAR num_adp_ctrl_recs; // number of adp_ctrl_rec's in array
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bl_adapter_ctrl_rec_t *adp_ctrl_rec; // pointer to adapter ctrl rec array
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} bl_adapter_model_rec_t;
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// Config flag defines
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// System sourced/color reg. pixel depth for DFA apeture 1 and commands
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#define BL_ENABLE_SOURCE_1_BPP (1L << 0)
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#define BL_ENABLE_SOURCE_8_BPP (1L << 1)
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#define BL_ENABLE_SOURCE_16_BPP (1L << 2)
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#define BL_ENABLE_SOURCE_24_BPP (1L << 3)
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// frame buffer pixel depth from DFA apeture 1 and commands
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#define BL_ENABLE_8_BPP (1L << 3)
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#define BL_ENABLE_16_BPP (1L << 4)
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#define BL_ENABLE_24_BPP (1L << 5)
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#define BL_ENABLE_OVERLAY (1L << 0)
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#define BL_ENABLE_DOUBLE_BUFFER (1L << 1)
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#define BL_OVERLAY_AVAILABLE (1L << 0)
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#define BL_8_BPP_DB_AVAILABLE (1L << 1)
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#define BL_16_BPP_DB_AVAILABLE (1L << 2)
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#define BL_8_BPP_AVAILABLE (1L << 3)
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#define BL_16_BPP_AVAILABLE (1L << 4)
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#define BL_24_BPP_AVAILABLE (1L << 5)
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#endif // _H_BLFW
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