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706 lines
35 KiB
706 lines
35 KiB
/*++
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Copyright (c) 1994 IBM Corporation
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Module Name:
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wdvga.h
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Abstract:
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This header file defines the WD90C24A2 GUI accelerator registers.
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Author:
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Hiroshi Itoh 25-Feb-1994
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Revision History:
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Peter Johnston Adapted to Woodfield HAL. Apr-1994
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--*/
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#include "pxvgaequ.h"
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extern UCHAR CRTC_800x600x60_Text[];
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extern UCHAR CRTC_640x480x60_Text[];
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//-----------------------------------------------------------------------
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// WD 90C24 PR register
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//-----------------------------------------------------------------------
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#define pr0a 0x09 // Address Offset A Reg
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#define pr0b 0x0a // Alternate Address Offset B Reg
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#define pr1 0x0b // Memory Size Reg
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#define pr2 0x0c // Video Select Reg
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#define pr3 0x0d // CRT Lock Control Reg
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#define pr4 0x0e // Video Control Reg
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#define pr5 0x0f // Unlock graphic Controller Extended
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// Paradise Reg
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#define pr10 0x29 // Unlock (PR11-PR17) Reg
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#define pr11 0x2a // Configuraiton Bits Reg
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#define pr12 0x2b // Scratch Pad Reg
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#define pr13 0x2c // Interlace H/2 Start Reg
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#define pr14 0x2d // Interlace H/2 End Reg
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#define pr15 0x2e // Miscellaneous Control 1 Reg
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#define pr16 0x2f // Miscellaneous Control 2 Reg
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#define pr17 0x30 // Miscellaneous Control 3 Reg
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#define pr18 0x31 // Flat Panel Status Reg
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#define pr19 0x32 // Flat Panel Control I Reg
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#define pr1a 0x33 // Flat Panel Control II Reg
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#define pr1b 0x34 // Flat Panel Unlock Reg
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#define pr20 0x06 // Unlock Sequencer Extended Reg
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#define pr21 0x07 // Display Configuraiton Status &
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// Scratch Pad Reg
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#define pr22 0x08 // Scratch Pad Reg
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#define pr23 0x09 // Scratch Pad Reg
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#define pr30 0x35 // Mapping RAM Unlock Reg
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#define pr30a 0x10 // Memory Interface & FIFO Control Reg
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#define pr31 0x11 // System Interface Control Reg
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#define pr32 0x12 // Miscellaneous Control 4 Reg
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#define pr33 0x38 // Mapping RAM Address Counter Reg
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#define pr34 0x39 // Mapping RAM Data Reg
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#define pr33a 0x13 // DRAM Timing and 0 wait state control
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#define pr34a 0x14 // Video Memory Mapping Reg
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#define pr35a 0x15 // USR0, USR1 output select
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#define pr35 0x3a // Mapping RAM Control Reg
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#define pr36 0x3b // LCD Panel Height Select Reg
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#define pr37 0x3c // Flat Panel Height Select Reg
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#define pr39 0x3e // Color LCD Control Reg
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#define pr41 0x37 // Vertical Expansion Initial Value Reg
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#define pr44 0x3f // Power Down Memory Refresh Control Reg
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#define pr45 0x16 // Signal Analyzer Control Reg
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#define pr45a 0x17 // Signal Analyzer Data I
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#define pr45b 0x18 // Signal Analyzer Data II
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#define pr18a 0x3d // CRTC Vertical Timing Overflow
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#define pr57 0x19 // WD90C24 Feature Reg I
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#define pr58 0x20 // WD90C24 Feature Reg II
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#define pr59 0x21 // WD90C24 Memory Arbitration Cycle Setup
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#define pr60 0x22 // Reserved
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#define pr61 0x23 // Reserved
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#define pr62 0x24 // FR Timing Reg
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#define pr63 0x25 //
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#define pr58a 0x26 //
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#define pr64 0x27 //
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#define pr65 0x28 //
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#define pr66 0x29 //
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#define pr68 0x31 //
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#define pr69 0x32 //
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#define pr70 0x33 //
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#define pr71 0x34 //
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#define pr72 0x35 //
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#define pr73 0x36 //
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//-----------------------------------------------------------------------
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// pr register lock/unlock pattern
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//-----------------------------------------------------------------------
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#define pr5_lock 0x00 //
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#define pr5_unlock 0x05 //
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#define pr10_lock 0x00 //
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#define pr10_unlock 0x85 //
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#define pr11_unlock 0x80 //
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#define pr11_lock 0x85 //
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#define pr1b_lock 0x00 //
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#define pr1b_unlock_shadow 0x06 //
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#define pr1b_unlock_pr 0xa0 //
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#define pr1b_unlock 0xa6 //
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#define pr20_lock 0x00 //
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#define pr20_unlock 0x48 //
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#define pr30_lock 0x00 //
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#define pr30_unlock 0x30 //
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#define pr72_lock 0x00 //
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#define pr72_unlock 0x50 //
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//-----------------------------------------------------------------------
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// WD 90C24 PR register < Initital Value >
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//-----------------------------------------------------------------------
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// CRT TFT Sim STN Sim STNC STNC //
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// all only only 32 only 16 sim only //
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// ---- ---- ---- ---- ---- ---- ---- ---- //
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#define pr0a_all 0x00 //
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#define pr0b_all 0x00 //
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#define pr1_all 0xc5 //
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#define pr2_crt 0x00 //
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#define pr2_tft 0x01 //
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#define pr2_s32 0x01 //
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#define pr2_stn 0x01 //
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#define pr2_s16 0x01 //
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#define pr2_stnc 0x01 //
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#define pr3_all 0x00 //
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#define pr4_all 0x40 //
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#define pr12_all 0x00 //
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#define pr12_244LP 0xe8 //
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#define pr13_all 0x00 //
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#define pr14_all 0x00 //
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#define pr15_all 0x00 //
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#define pr16_all 0x42 //
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#define pr17_all 0x00 //
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#define pr17_244LP 0x40 //
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#define pr18_crt_tft 0x43 //single panel
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#define pr18_crt_stn 0x00 //dual panel
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#define pr18_tft 0xc7 // old d7h
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#define pr18_s32 0x47 // old 57h
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#define pr18_stn 0x80 //
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#define pr18_s16 0x00 //
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#define pr18_stnc 0x00 //
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#define pr19_disable 0x40 //
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#define pr19_crt 0x64 //
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#define pr19_tft 0x54 //
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#define pr19_s32 0x74 //
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#define pr19_stn 0x54 //
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#define pr19_s16 0x74 //
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#define pr19_stnc 0x74 //
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#define pr19_stnc_only 0x54 //
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#define pr39_crt 0x04 //
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#define pr39_tft 0x20 //
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#define pr39_s32 0x24 //
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#define pr39_stn 0x00 //
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#define pr39_s16 0x04 //
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#define pr39_stnc 0x24 //
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#define pr1a_all 0x00 // except STNC
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#define pr1a_stnc 0x60 // STNC
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#define pr36_all 0xef //
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#define pr37_crt 0x9a //
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#define pr37_tft 0x9a //
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#define pr37_s32 0x9a //
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#define pr37_stn 0x9a //
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#define pr37_s16 0x1a //
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#define pr37_stnc 0x9a //
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#define pr18a_all 0x00 //
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#define pr41_all 0x00 //
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#define pr44_all 0x00 //
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#define pr33_all 0x00 //
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#define pr34_all 0x00 //
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#define pr35_all 0x22 // old 0a2h
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#define pr35_suspend 0xa2 //
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#define pr21_all 0x00 //
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#define pr22_all 0x00 //
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#define pr23_all 0x00 //
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#define pr30a_crt 0xc1 //
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#define pr30a_tft 0xc1 //
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#define pr30a_s32 0xc1 //
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#define pr30a_stn 0xc1 //
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#define pr30a_s16 0xe1 //
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#define pr30a_stnc 0xe1 //
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#define pr31_all 0x25 //
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#define pr32_all 0x00 //
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#define pr33a_all 0x80 //
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#define pr33a_stnc 0x83 //
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#define pr34a_all 0x00 //
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#define pr35a_all 0x00 //
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#define pr45_all 0x00 //
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#define pr45a_all 0x00 //
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#define pr45b_all 0x00 //
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#define pr57_all 0x31 //
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#define pr58_all 0x00 //
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#define pr58a_all 0x00 //
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#define pr59_all_sivA 0x35 //
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#define pr59_crt 0x15 // for SIV-B
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#define pr59_tft 0x15 //
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#define pr59_s32 0x15 //
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#define pr59_stn 0x35 //
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#define pr59_s16 0x35 //
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#define pr59_stnc 0x03 //
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#define pr60_all 0x00 //
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#define pr61_all 0x00 //
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#define pr62_all 0x3c //
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#define pr63_all 0x00 //
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#define pr64_all 0x03 //enhncd v-exp
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#define pr65_all 0x00 //
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#define pr66_crt 0x40 //
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#define pr66_tft 0x40 //
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#define pr66_s32 0x40 //
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#define pr66_stn 0x40 //
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#define pr66_s16 0x40 //
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#define pr66_stnc 0x40 //
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#define pr68_crt 0x0d //
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#define pr68_tft 0x0d //
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#define pr68_s32 0x0d // old 0bh
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#define pr68_stn 0x1d //
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#define pr68_s16 0x0d //
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#define pr68_stnc 0x0d //
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#define pr68_stnc_only 0x07 //
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#define pr69_all 0x00 //
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#define pr69_stnc_only 0x53 // old 3fh
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#define pr70_all 0x00 //
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#define pr71_all 0x00 //
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#define pr73_all 0x01 //
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//--------------------------------------------------------------------------
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// WD 90C24 Shadow Register < Initial Value >
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//--------------------------------------------------------------------------
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// For TFT color Only Mode
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#define crtc00_tft 0x5f //
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#define crtc02_tft 0x50 //
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#define crtc03_tft 0x82 //
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#define crtc04_tft 0x54 //
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#define crtc05_tft 0x80 //
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#define crtc06_tft 0x0b //
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#define crtc07_tft 0x3e //
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#define crtc10_tft 0xea //
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#define crtc11_tft 0x8c //
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#define crtc15_tft 0xe7 //
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#define crtc16_tft 0x04 //
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// For TFT color Simultaneos Mode
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#define crtc00_s32 0x5f //
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#define crtc02_s32 0x50 //
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#define crtc03_s32 0x82 //
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#define crtc04_s32 0x54 //
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#define crtc05_s32 0x80 //
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#define crtc06_s32 0x0b //
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#define crtc07_s32 0x3e //
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#define crtc10_s32 0xea //
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#define crtc11_s32 0x8c //
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#define crtc15_s32 0xe7 //
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#define crtc16_s32 0x04 //
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// For STN mono Only Mode
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#define crtc00_stn 0x5f //
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#define crtc02_stn 0x50 //
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#define crtc03_stn 0x82 //
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#define crtc04_stn 0x54 //
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#define crtc05_stn 0x80 //
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#define crtc06_stn 0xf2 //
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#define crtc07_stn 0x12 //
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#define crtc10_stn 0xf0 //
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#define crtc11_stn 0x82 //
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#define crtc15_stn 0xf0 //
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#define crtc16_stn 0xf2 //
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// For STN mono Simultaneos Mode
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#define crtc00_s16 0x5f //
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#define crtc02_s16 0x50 //
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#define crtc03_s16 0x82 //
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#define crtc04_s16 0x54 //
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#define crtc05_s16 0x80 //
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#define crtc06_s16 0x12 //
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#define crtc07_s16 0x3e //
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#define crtc10_s16 0xea //
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#define crtc11_s16 0x8c //
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#define crtc15_s16 0xe7 //
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#define crtc16_s16 0x04 //
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// For STN Color Simultaneos Mode //new old
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#define crtc00_stnc 0x61 // 60h
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#define crtc02_stnc 0x50 // 51h
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#define crtc03_stnc 0x84 // 82h
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#define crtc04_stnc 0x56 // 54h
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#define crtc05_stnc 0x80 //
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#define crtc06_stnc 0x0e // 0ah
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#define crtc07_stnc 0x3e //
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#define crtc10_stnc 0xea //
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#define crtc11_stnc 0x8e //
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#define crtc15_stnc 0xe7 //
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#define crtc16_stnc 0x04 //
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// For STN Color LCD only Mode //new old
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#define crtc00_stnc_only 0x67 // 60h
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#define crtc02_stnc_only 0x50 // 50h
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#define crtc03_stnc_only 0x82 // 82h
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#define crtc04_stnc_only 0x55 // 54h
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#define crtc05_stnc_only 0x81 // 80h
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#define crtc06_stnc_only 0xe6 // 0e6h
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#define crtc07_stnc_only 0x1f // 1fh
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#define crtc10_stnc_only 0xe0 // 0d9h
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#define crtc11_stnc_only 0x82 // 82h
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#define crtc15_stnc_only 0xe0 // 0f0h
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#define crtc16_stnc_only 0xe2 // 00h
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//-----------------------------------------------------------------------
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// WD 90C24 Mapping RAM Data
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//-----------------------------------------------------------------------
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#define map_00 0x00
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#define map_01 0x05
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#define map_02 0x05
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#define map_03 0x06
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#define map_04 0x06
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#define map_05 0x07
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#define map_06 0x07
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#define map_07 0x08
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#define map_08 0x08
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#define map_09 0x0a
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#define map_0a 0x0a
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#define map_0b 0x0b
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#define map_0c 0x0c
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#define map_0d 0x0d
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#define map_0e 0x0d
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#define map_0f 0x0f
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#define map_10 0x0f
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#define map_11 0x11
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#define map_12 0x12 // old 11h
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#define map_13 0x12 // old 13h
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#define map_14 0x15 // old 13h
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#define map_15 0x15
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#define map_16 0x17 // old 15h
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#define map_17 0x17
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#define map_18 0x19 // old 17h
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#define map_19 0x19
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#define map_1a 0x1b
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#define map_1b 0x1b
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#define map_1c 0x1d
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#define map_1d 0x1d
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#define map_1e 0x1f
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#define map_1f 0x1f
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#define map_20 0x20
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#define map_21 0x21
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#define map_22 0x21
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#define map_23 0x23
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#define map_24 0x25 // old 24h
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#define map_25 0x27
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#define map_26 0x27
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#define map_27 0x29
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#define map_28 0x29
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#define map_29 0x2a
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#define map_2a 0x2b
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#define map_2b 0x2b // old 2ch
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#define map_2c 0x2e
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#define map_2d 0x2e
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#define map_2e 0x2f
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#define map_2f 0x2f
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#define map_30 0x31
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#define map_31 0x33
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#define map_32 0x33
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#define map_33 0x34
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#define map_34 0x34
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#define map_35 0x35 // old 36h
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#define map_36 0x36
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#define map_37 0x38
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#define map_38 0x39
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#define map_39 0x39
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#define map_3a 0x3a
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#define map_3b 0x3a
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#define map_3c 0x3b
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#define map_3d 0x3b
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#define map_3e 0x3f
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#define map_3f 0x3f
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//-----------------------------------------------------------------------
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// Paradise register bit flag definitions
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//-----------------------------------------------------------------------
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// pr19 display position definition
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#define pr19_CENTER 0x04 // display position is CENTER
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#define pr19_TOP 0x00 // display position is TOP
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#define pr19_BOTTOM 0x04 // display position is BOTTOM (N/A)
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#define pr19_VEXP 0x0C // Vertical Expansion
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//-----------------------------------------------------------------------
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// Extended Paradise Regs definitions
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//-----------------------------------------------------------------------
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// Global port definitions
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#define EPR_INDEX 0x23c0 // Index Control Reg
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#define EPR_DATA 0x23c2 // Register access port
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//
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// Define paradise registers setting variation
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//
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#define pr72_alt (pr72 | 0x8000) // avoid pr30 index conflict
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#define pr1b_ual (pr1b) // pr1b unlock variation
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#define pr1b_ush (pr1b | 0x4000) // pr1b unlock variation
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#define pr1b_upr (pr1b | 0x8000) // pr1b unlock variation
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//
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// Define WD register I/O Macros
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//
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#define WRITE_WD_UCHAR(port,data) \
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*(volatile unsigned char *)((ULONG)HalpIoControlBase + (port)) = (UCHAR)(data), \
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KeFlushWriteBuffer()
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#define WRITE_WD_USHORT(port,data) \
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*(volatile PUSHORT)((ULONG)HalpIoControlBase + (port)) = (USHORT)(data), \
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KeFlushWriteBuffer()
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#define READ_WD_UCHAR(port) \
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*(volatile unsigned char *)((ULONG)HalpIoControlBase + (port))
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#define READ_WD_USHORT(port) \
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*(volatile unsigned short *)((ULONG)HalpIoControlBase + (port))
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#define READ_WD_VRAM(port) \
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*(HalpVideoMemoryBase + (port))
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#define WRITE_WD_VRAM(port,data) \
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*(HalpVideoMemoryBase + (port)) = (data), \
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KeFlushWriteBuffer()
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//
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// Define video register format.
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//
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#define WD_3D4_Index 0x3D4 // R/W
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#define WD_3D5_Data 0x3D5 // R/W
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#define SUBSYS_ENB 0x46E8 // R/W
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//
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// WD90C24A2 LCD/CRT both screen table
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//
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enum { W_SEQ, W_GCR, W_ACR, W_CRTC, R_SEQ, R_GCR, R_ACR, R_CRTC, END_PVGA } pvga_service;
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static
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UCHAR
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wd90c24a_both_800[] = {
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W_CRTC , pr10, pr10_unlock , // Disable CRT/LCD by PR19
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W_CRTC , pr11, pr11_unlock , // Disable CRT/LCD by PR19
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W_CRTC , pr1b, pr1b_unlock , // Disable CRT/LCD by PR19
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W_CRTC , pr19, pr19_disable ,
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//---------------------> start SEQ
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W_SEQ , pr20 , pr20_unlock , // PVGA Sequencer Regs
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// W_SEQ , pr21 , pr21_all , // read only
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W_SEQ , pr30a, pr30a_s32 ,
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W_SEQ , pr31 , (pr31_all & ~0x24) ,
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W_SEQ , pr32 , pr32_all ,
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W_SEQ , pr33a, pr33a_all ,
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W_SEQ , pr34a, pr34a_all ,
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W_SEQ , pr35a, pr35a_all ,
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// W_SEQ , pr45 , pr45_all ,
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// W_SEQ , pr45a, pr45a_all ,
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// W_SEQ , pr45b, pr45b_all ,
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W_SEQ , pr57 , pr57_all ,
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W_SEQ , pr58 , pr58_all ,
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W_SEQ , pr58a, pr58a_all ,
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W_SEQ , pr59 , pr59_s32 ,
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// W_SEQ , pr60 , pr60_all ,
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// W_SEQ , pr61 , pr61_all ,
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W_SEQ , pr62 , pr62_all ,
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// W_SEQ , pr63 , pr63_all ,
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W_SEQ , pr64 , pr64_all ,
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// W_SEQ , pr65 , pr65_all ,
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W_SEQ , pr66 , pr66_s32 , // old 00h
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W_SEQ , pr72 , pr72_unlock , // unlock clock select
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W_SEQ , pr68 , pr68_s32 , // 0d
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// W_SEQ , pr72 , pr72_lock , // lock clock select
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// W_SEQ , pr72 , pr72_lock , // lock is default
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// W_SEQ , pr69 , pr69_all ,
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// W_SEQ , pr70 , pr70_all ,
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W_SEQ , pr70 , 0x24 ,
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// W_SEQ , pr71 , pr71_all , // disabled by PR57(1)
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// W_SEQ , pr73 , pr73_all ,
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// W_SEQ , pr20 , pr20_lock ,
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//---------------------> start GRAPH
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W_GCR , pr5 , pr5_unlock , // PR0(A), PR0(B), PR1, PR2, PR3, PR4
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// W_GCR , pr0a , pr0a_all ,
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// W_GCR , pr0b , pr0b_all ,
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W_GCR , pr1 , pr1_all ,
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W_GCR , pr2 , pr2_s32 ,
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W_GCR , pr3 , pr3_all ,
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W_GCR , pr4 , pr4_all ,
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// W_GCR , pr5 , pr5_lock ,
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//---------------------> start CRTC
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W_CRTC , pr10 , pr10_unlock , // PR11, PR13, PR14, PR15, PR16, PR17
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// W_CRTC , pr11 , pr11_lock , // default is lock
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// W_CRTC , pr12 , pr12_all ,
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W_CRTC , pr13 , pr13_all ,
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W_CRTC , pr14 , pr14_all ,
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W_CRTC , pr15 , pr15_all ,
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W_CRTC , pr16 , pr16_all ,
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W_CRTC , pr17 , pr17_all ,
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// W_CRTC , pr10 , pr10_lock ,
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W_CRTC , pr1b , pr1b_unlock , // PR18, PR19, PR1A, PR36, PR37, PR39, PR41, PR44
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W_CRTC , pr18 , pr18_s32 ,
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// W_CRTC , pr19 , pr19_s32 ,
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W_CRTC , pr19 , pr19_tft & ~0x04 ,
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W_CRTC , pr39 , pr39_s32 ,
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W_CRTC , pr1a , 0x90 ,
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W_CRTC , pr36 , pr36_all ,
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W_CRTC , pr37 , pr37_s32 ,
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W_CRTC , pr18a, pr18a_all ,
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// W_CRTC , pr41 , pr41_all ,
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W_CRTC , pr44 , pr44_all ,
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// W_CRTC , pr1b , pr1b_lock ,
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W_CRTC , pr30 , pr30_unlock , // PR35 (Mapping RAM not initialized)
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// W_CRTC , pr33 , pr33_all ,
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// W_CRTC , pr34 , pr34_all ,
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W_CRTC , pr35 , pr35_all ,
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// W_CRTC , pr30 , pr30_lock ,
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// Shadow Regs
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// CRTC shadows
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W_CRTC , pr1b , pr1b_unlock_shadow ,// Unlock shadow
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W_CRTC , 0x11 , crtc11_s32 & 0x7f , // unlock CRTC 0-7
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W_CRTC , 0x00 , 0x7f ,
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W_CRTC , 0x01 , 0x63 ,
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W_CRTC , 0x02 , 0x64 ,
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W_CRTC , 0x03 , 0x82 ,
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W_CRTC , 0x04 , 0x6b ,
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W_CRTC , 0x05 , 0x1b ,
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W_CRTC , 0x06 , 0x72 ,
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W_CRTC , 0x07 , 0xf0 ,
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W_CRTC , 0x09 , 0x20 ,
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W_CRTC , 0x10 , 0x58 ,
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W_CRTC , 0x11 , 0x8c , // lock CRTC 0-7
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W_CRTC , 0x15 , 0x58 ,
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W_CRTC , 0x16 , 0x71 ,
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// W_CRTC , pr17 , 0xe3 , // Lock shadow
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// W_CRTC , pr18 , 0xff , // Lock shadow
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//---------------------> start CRTC
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W_CRTC , pr1b, pr1b_unlock_pr ,
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W_CRTC , pr19 ,(pr19_s32 & ~0x04), // Lock shadow
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END_PVGA
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};
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static
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UCHAR
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wd90c24a_both_640[] = {
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W_CRTC , pr1b, pr1b_unlock , // Disable CRT/LCD by PR19
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W_CRTC , pr19, pr19_disable ,
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W_CRTC , pr1b, pr1b_lock ,
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W_SEQ , pr20 , pr20_unlock , // PVGA Sequencer Regs
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// W_SEQ , pr21 , pr21_all , // read only
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W_SEQ , pr30a, pr30a_s32 ,
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W_SEQ , pr31 , pr31_all ,
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W_SEQ , pr32 , pr32_all ,
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W_SEQ , pr33a, pr33a_all ,
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W_SEQ , pr34a, pr34a_all ,
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W_SEQ , pr35a, pr35a_all ,
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// W_SEQ , pr45 , pr45_all ,
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// W_SEQ , pr45a, pr45a_all ,
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// W_SEQ , pr45b, pr45b_all ,
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W_SEQ , pr57 , pr57_all ,
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W_SEQ , pr58 , pr58_all ,
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W_SEQ , pr58a, pr58a_all ,
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W_SEQ , pr59 , pr59_s32 ,
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// W_SEQ , pr60 , pr60_all ,
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// W_SEQ , pr61 , pr61_all ,
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W_SEQ , pr62 , pr62_all ,
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// W_SEQ , pr63 , pr63_all ,
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W_SEQ , pr64 , pr64_all ,
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// W_SEQ , pr65 , pr65_all ,
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W_SEQ , pr66 , pr66_s32 , // old 00h
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W_SEQ , pr72 , pr72_unlock , // unlock clock select
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W_SEQ , pr68 , pr68_s32 , // 0d
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// W_SEQ , pr72 , pr72_lock , // lock clock select
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W_SEQ , pr72 , pr72_lock , // lock is default
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// W_SEQ , pr69 , pr69_all ,
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// W_SEQ , pr70 , pr70_all ,
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// W_SEQ , pr71 , pr71_all , // disabled by PR57(1)
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// W_SEQ , pr73 , pr73_all ,
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W_SEQ , pr20 , pr20_lock ,
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W_GCR , pr5 , pr5_unlock , // PR0(A), PR0(B), PR1, PR2, PR3, PR4
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// W_GCR , pr0a , pr0a_all ,
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// W_GCR , pr0b , pr0b_all ,
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W_GCR , pr1 , pr1_all ,
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W_GCR , pr2 , pr2_s32 ,
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W_GCR , pr3 , pr3_all ,
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W_GCR , pr4 , pr4_all ,
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W_GCR , pr5 , pr5_lock ,
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W_CRTC , pr10 , pr10_unlock , // PR11, PR13, PR14, PR15, PR16, PR17
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W_CRTC , pr11 , pr11_lock , // default is lock
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// W_CRTC , pr12 , pr12_all ,
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W_CRTC , pr13 , pr13_all ,
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W_CRTC , pr14 , pr14_all ,
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W_CRTC , pr15 , pr15_all ,
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W_CRTC , pr16 , pr16_all ,
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W_CRTC , pr17 , pr17_all ,
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W_CRTC , pr10 , pr10_lock ,
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W_CRTC , pr1b , pr1b_unlock , // PR18, PR19, PR1A, PR36, PR37, PR39, PR41, PR44
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W_CRTC , pr18 , pr18_s32 ,
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W_CRTC , pr19 , pr19_s32 ,
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W_CRTC , pr39 , pr39_s32 ,
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W_CRTC , pr1a , pr1a_all ,
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W_CRTC , pr36 , pr36_all ,
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W_CRTC , pr37 , pr37_s32 ,
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W_CRTC , pr18a, pr18a_all ,
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// W_CRTC , pr41 , pr41_all ,
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W_CRTC , pr44 , pr44_all ,
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W_CRTC , pr1b , pr1b_lock ,
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W_CRTC , pr30 , pr30_unlock , // PR35 (Mapping RAM not initialized)
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// W_CRTC , pr33 , pr33_all ,
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// W_CRTC , pr34 , pr34_all ,
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W_CRTC , pr35 , pr35_all ,
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W_CRTC , pr30 , pr30_lock ,
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// Shadow Regs
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W_CRTC , pr1b , pr1b_unlock_shadow ,// Unlock shadow
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W_CRTC , 0x11 , crtc11_s32 & 0x7f , // unlock CRTC 0-7
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W_CRTC , 0x00 , crtc00_s32 ,
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W_CRTC , 0x02 , crtc02_s32 ,
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W_CRTC , 0x03 , crtc03_s32 ,
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W_CRTC , 0x04 , crtc04_s32 ,
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W_CRTC , 0x05 , crtc05_s32 ,
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W_CRTC , 0x06 , crtc06_s32 ,
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W_CRTC , 0x07 , crtc07_s32 ,
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W_CRTC , 0x09 , 0x00 ,
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W_CRTC , 0x10 , crtc10_s32 ,
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W_CRTC , 0x11 , crtc11_s32 , // lock CRTC 0-7
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W_CRTC , 0x15 , crtc15_s32 ,
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W_CRTC , 0x16 , crtc16_s32 ,
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W_CRTC , pr1b , pr1b_lock , // Lock shadow
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END_PVGA
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};
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