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266 lines
9.1 KiB
266 lines
9.1 KiB
// #pragma comment(exestr, "@(#) r94adef.h 1.1 95/09/28 15:47:51 nec")
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/*++ BUILD Version: 0005 // Increment this if a change has global effects
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Copyright (c) 1994 NEC Corporation
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Module Name:
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r94adef.h
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Abstract:
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This module is the header file that describes hardware addresses
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for the R94A system.
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Author:
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Akitoshi Kuriyama 23-Aug-1994
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Revision History:
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M001 1994.8.23 A. Kuriyama
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- Modify for R94A MIPS R4400 (original duodef.h)
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M002 1994.9.24 A. Kuriyama
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- Modify PCI A-D Vector Value
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H000 Sat Sep 24 23:11:51 JST 1994 kbnes!kishimoto
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- Add the number of PCI slots
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ADD001 [email protected] Mon Oct 17 17:10:13 JST 1994
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- Add
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#define PCI_CONTROL_PHYSICAL_BASE (EISA_CONTROL_PHYSICAL_BASE+64*1024)
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#define PCI_MEMORY_PHYSICAL_BASE_LOW (EISA_MEMORY_VERSION2_LOW + 64*1024*1024)
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#define PCI_MEMORY_PHYSICAL_BASE_HIGH 0x00000001
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M003 Mon Oct 17 17:26:12 JST 1994 kbnes!kuriyama
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name change MAXIMUN_PCI_SLOT -> R94A_PCI_SLOT
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ADD002 [email protected] Mon Oct 17 19:30:00 JST 1994
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- change PCI_CONTROL_PHYSICAL_BASE, PCI_MEMORY_PHYSICAL_BASE_LOW
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64*1024 -> 10000 64*1024*1024 -> 4000000
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D001 [email protected] Sat Nov 05 16:06:26 JST 1994
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- reduce DMA_TRANSLATION_LIMIT to 4 only for BBM DMA
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S0004 Thu Dec 22 11:55:04 JST 1994 kbnes!A.Kuriyama
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-add beta machine limit
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S0005 Thu Jan 05 17:17:09 JST 1995 kbnes!A.Kuriyama
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- warning clear
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S0006 Thu Jan 05 18:52:51 JST 1995 kbnes!A.Kuriyama
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- dma_limit change
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M0007 Tue Mar 07 14:34:55 JST 1995 kbnes!kuriyama (A)
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- expand dma logical address
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M0008 Fri Mar 10 15:34:25 JST 1995 kbnes!kuriyama (A)
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- expand dma logical address bug fix
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M0009 Tue Mar 21 02:45:16 1995 kbnes!kishimoto
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- physical base of PCI memory set to 64M
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M0010 Tue Mar 21 03:06:05 1995 kbnes!kishimoto
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- M0009 could not allocate memory
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set base to zero.
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M0011 Tue Apr 25 16:34:35 1995 kbnes!kishimoto
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- add MRC registers
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S0012 [email protected] Mon Jun 05 01:55:08 JST 1995
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- add NVRAM_VIRTUAL_BASE
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M0011 Sat Aug 12 16:51:50 1995 kbnes!kishimoto
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- rearrange the comments.
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--*/
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#ifndef _R94ADEF_
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#define _R94ADEF_
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//
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// ADD001,ADD002
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// Define physical base addresses for system mapping.
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//
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#define VIDEO_MEMORY_PHYSICAL_BASE 0x40000000 // physical base of video memory
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#define VIDEO_CONTROL_PHYSICAL_BASE 0x60000000 // physical base of video control
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#define CURSOR_CONTROL_PHYSICAL_BASE 0x60008000 // physical base of cursor control
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#define VIDEO_ID_PHYSICAL_BASE 0x60010000 // physical base of video id register
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#define VIDEO_RESET_PHYSICAL_BASE 0x60020000 // physical base of reset register
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#define DEVICE_PHYSICAL_BASE 0x80000000 // physical base of device space
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#define NET_PHYSICAL_BASE 0x80001000 // physical base of ethernet control
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#define SCSI1_PHYSICAL_BASE 0x80002000 // physical base of SCSI1 control
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#define SCSI2_PHYSICAL_BASE 0x80003000 // physical base of SCSI2 control
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#define RTCLOCK_PHYSICAL_BASE 0x80004000 // physical base of realtime clock
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#define KEYBOARD_PHYSICAL_BASE 0x80005000 // physical base of keyboard control
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#define MOUSE_PHYSICAL_BASE 0x80005000 // physical base of mouse control
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#define SERIAL0_PHYSICAL_BASE 0x80006000 // physical base of serial port 0
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#define SERIAL1_PHYSICAL_BASE 0x80007000 // physical base of serial port 1
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#define PARALLEL_PHYSICAL_BASE 0x80008000 // physical base of parallel port
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#define EISA_CONTROL_PHYSICAL_BASE 0x90000000 // physical base of EISA control
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#define EISA_MEMORY_PHYSICAL_BASE 0x91000000 // physical base of EISA memory
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#define EISA_MEMORY_VERSION2_LOW 0x00000000 // physical base of EISA memory
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#define EISA_MEMORY_VERSION2_HIGH 0x00000001 // with version 2 address chip
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#define PROM_PHYSICAL_BASE 0xfff00000 // physical base of boot PROM
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#define EEPROM_PHYSICAL_BASE 0xfff40000 // physical base of FLASH PROM
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#define PCI_CONTROL_PHYSICAL_BASE (EISA_CONTROL_PHYSICAL_BASE) // physical base of PCI control
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#define PCI_MEMORY_PHYSICAL_BASE_LOW (EISA_MEMORY_VERSION2_LOW) // physical base of PCI memory
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#define PCI_MEMORY_PHYSICAL_BASE_HIGH 0x00000001 // physical base of PCI memory
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//
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// S0012
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// Define virtual/physical base addresses for system mapping.
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//
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#define NVRAM_VIRTUAL_BASE 0xffff8000 // virtual base of nonvolatile RAM
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#define NVRAM_PHYSICAL_BASE 0x80009000 // physical base of nonvolatile RAM
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#define SP_VIRTUAL_BASE 0xffffa000 // virtual base of serial port 0
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#define SP_PHYSICAL_BASE SERIAL0_PHYSICAL_BASE // physical base of serial port 0
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#define DMA_VIRTUAL_BASE 0xffffc000 // virtual base of DMA control
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#define DMA_PHYSICAL_BASE DEVICE_PHYSICAL_BASE // physical base of DMA control
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#define INTERRUPT_VIRTUAL_BASE 0xffffd000 // virtual base of interrupt source
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#define INTERRUPT_PHYSICAL_BASE 0x8000f000 // physical base of interrupt source
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//
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// Define the size of the DMA translation table.
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//
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#if defined (_BBM_DMA_) // D001,S0004,S0005,S0006
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#define DMA_TRANSLATION_LIMIT (sizeof(TRANSLATION_ENTRY) * 8 * 4) // translation table limit
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#else
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#if defined(_DMA_EXPAND_) // M0007,M0008
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#define ISA_MAX_ADR 0x400000L // ISA MAX Logical Address
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#define EISA_MIN_ADR 0x1000000L // EISA/PCI MIN Logical Address
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#define EISA_MAX_ADR 0x2000000L // EISA/PCI MAX Logical Address
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#define DMA_TRANSLATION_LIMIT (EISA_MAX_ADR / PAGE_SIZE * sizeof(TRANSLATION_ENTRY) )
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// translation table limit
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#else // _DMA_EXPAND_
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#define DMA_TRANSLATION_LIMIT 0x2000 // translation table limit
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#endif // _DMA_EXPAND_
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#endif // (_BBM_DMA_)
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//
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// Define the maximum number of map registers allowed per allocation.
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//
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#define DMA_REQUEST_LIMIT (DMA_TRANSLATION_LIMIT/(sizeof(TRANSLATION_ENTRY) * 8))
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//
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// Define pointer to DMA control registers.
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//
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#define DMA_CONTROL ((volatile PDMA_REGISTERS)(DMA_VIRTUAL_BASE))
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//
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// Define DMA channel interrupt level.
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//
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#define DMA_LEVEL 3
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//
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// Define the minimum and maximum system time increment values in 100ns units.
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//
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#define MAXIMUM_INCREMENT (10 * 1000 * 10)
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#define MINIMUM_INCREMENT (1 * 1000 * 10)
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//
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// Define Duo clock level.
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//
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#define CLOCK_LEVEL 6 // Interval clock level
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#define CLOCK_INTERVAL ((MAXIMUM_INCREMENT / (10 * 1000)) - 1) // Ms minus 1
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#define CLOCK2_LEVEL CLOCK_LEVEL //
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//
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// Define EISA device level.
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//
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#define EISA_DEVICE_LEVEL 5 // EISA bus interrupt level
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//
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// Define EISA device interrupt vectors.
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//
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#define EISA_VECTORS 32
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#define IRQL10_VECTOR (10 + EISA_VECTORS) // Eisa interrupt request level 10
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#define IRQL11_VECTOR (11 + EISA_VECTORS) // Eisa interrupt request level 11
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#define IRQL12_VECTOR (12 + EISA_VECTORS) // Eisa interrupt request level 12
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#define IRQL13_VECTOR (13 + EISA_VECTORS) // Eisa interrupt request level 13
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#define MAXIMUM_EISA_VECTOR (15 + EISA_VECTORS) // maximum EISA vector
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//
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// Define I/O device interrupt level.
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//
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#define DEVICE_LEVEL 4 // I/O device interrupt level
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//
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// Define device interrupt vectors.
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//
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#define DEVICE_VECTORS 16 // starting builtin device vector
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#define PARALLEL_VECTOR (1 + DEVICE_VECTORS) // Parallel device interrupt vector
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//#define VIDEO_VECTOR (3 + DEVICE_VECTORS) // video device interrupt vector
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#define AUDIO_VECTOR (3 + DEVICE_VECTORS) // audio device interrupt vector
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#define NET_VECTOR (4 + DEVICE_VECTORS) // ethernet device interrupt vector
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#define SCSI1_VECTOR (5 + DEVICE_VECTORS) // SCSI device interrupt vector
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#define SCSI2_VECTOR (6 + DEVICE_VECTORS) // SCSI device interrupt vector
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#define KEYBOARD_VECTOR (7 + DEVICE_VECTORS) // Keyboard device interrupt vector
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#define MOUSE_VECTOR (8 + DEVICE_VECTORS) // Mouse device interrupt vector
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#define SERIAL0_VECTOR (9 + DEVICE_VECTORS) // Serial device 0 interrupt vector
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#define SERIAL1_VECTOR (10 + DEVICE_VECTORS) // Serial device 1 interrupt vector
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#define TYPHOON_ERROR_INTERRUPT_VECTOR (15 + DEVICE_VECTORS) // TYPHOON error vector
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//#define MAXIMUM_BUILTIN_VECTOR SERIAL1_VECTOR // maximum builtin vector
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#define MAXIMUM_BUILTIN_VECTOR TYPHOON_ERROR_INTERRUPT_VECTOR // maximum builtin vector
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//
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// M0001,M0002
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// Define PCI device interrupt vectors.
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//
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#define PCI_VECTORS 80
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//#define INTERRUPT_D_VECTOR (0 + PCI_VECTORS)
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//#define INTERRUPT_C_VECTOR (1 + PCI_VECTORS)
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//#define INTERRUPT_B_VECTOR (2 + PCI_VECTORS)
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//#define INTERRUPT_A_VECTOR (3 + PCI_VECTORS)
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//#define MAXIMUM_PCI_VECTOR INTERRUPT_A_VECTOR
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//
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// Define the clock speed in megahetz for the SCSI protocol chips.
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//
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#define NCR_SCSI_CLOCK_SPEED 24
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//
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// PROM entry point definitions.
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//
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// Define base address of prom entry vector and prom entry macro.
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//
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#define PROM_BASE (KSEG1_BASE | 0x1fc00000)
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#define PROM_ENTRY(x) (PROM_BASE + ((x) * 8))
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//
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// H000,M003
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// the number of lines which PCI interrupts.
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//
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#define R94A_PCI_SLOT 3
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//
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// M0011
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// Define pointer to MRC control registers.
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//
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#define MRC_CONTROL ((volatile PMRC_REGISTERS)(DMA_VIRTUAL_BASE))
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//
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// M0011
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// Define physical base addresses for system mapping.
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//
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#define MRC_TEMP_PHYSICAL_BASE 0x80012000 // physical base of MRC and TEMP sensor
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#endif // _R94ADEF_
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