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471 lines
13 KiB
471 lines
13 KiB
// "@(#) NEC r98clock.s 1.10 95/02/20 17:04:37"
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// TITLE("Interval and Profile Clock Interrupts")
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//++
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//
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// Copyright (c) 1991-1994 Microsoft Corporation
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//
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// Module Name:
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//
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// r98clock.s
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//
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// Abstract:
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//
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// This module implements the code necessary to field and process the
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// interval and profile clock interrupts on a MIPS R4000 system.
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//
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//--
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//
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// Original source: Build Number 1.612
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//
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// Modify for R98(MIPS/R4400)
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//
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//***********************************************************************
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//
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// M001 94.03/16-5/31 T.Samezima
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//
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// change header file from duo to r98
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// change value of use to update of parformance counter
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// initial value of count register
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//
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// del clear interrupt
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//
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//***********************************************************************
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//
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// S002 94.6/13 T.Samezima
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//
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// Del Compile err
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//
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//
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//***********************************************************************
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//
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// S003 94.7/19 T.Samezima
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//
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// Chg Function interface change
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//
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//***********************************************************************
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//
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// S004 94.7/19 T.Samezima
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//
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// Bug PMC register address is not change of KSEG1_BASE
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//
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//***********************************************************************
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//
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// S005 94.10/12 T.Samezima
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//
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// Fix Version Up at build807
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//
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// S006 '94.10/14 T.Samezima
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// Chg Logic of set interval count
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//
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// S007 '94.01/11 T.Samezima
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// Del delete 'if NT_UP'.
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//
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// S008 '94.01/16 T.Samezima
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// Add Check ECC 1bit err flag and enable ECC 1bit err.
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//
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//
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#include "halmips.h"
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// Start M001
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#if defined(_R98_)
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#include "r98def.h"
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// #include "r98reg.h" // S002
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#else // if defined(_R98_)
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#if defined(_DUO_)
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#include "duodef.h"
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#endif
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#if defined(_JAZZ_)
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#include "jazzdef.h"
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#endif
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#endif // #if !defined(_R98_)
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// End M001
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#define ECC_ERROR_COUNT_LIMIT 1 // S008
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SBTTL("System Clock Interrupt - Processor 0")
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//++
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//
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// Routine Description:
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//
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// This routine is entered as the result of an interrupt generated by
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// the interval timer. Its function is to acknowledge the interrupt and
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// transfer control to the standard system routine to update the system
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// time and the execution time of the current thread and process.
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//
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// Arguments:
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//
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// a0 - Supplies a pointer to a trap frame. // S003
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//
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// Return Value:
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//
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// None.
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//
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//--
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.struct 0
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CiArgs: .space 4 * 4 // saved arguments
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.space 3 * 4 // fill
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CiRa: .space 4 // saved return address
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CiFrameLength: //
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NESTED_ENTRY(HalpClockInterrupt0, CiFrameLength, zero)
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subu sp,sp,CiFrameLength // allocate stack frame
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sw ra,CiRa(sp) // save return address
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PROLOGUE_END
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// Start M001
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#if !defined(_R98_)
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.set noreorder
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#if defined(_DUO_)
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lw t0,DMA_VIRTUAL_BASE + 0x58 // acknowledge timer interrupt
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#endif
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#if defined(_JAZZ_)
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lw t0,DMA_VIRTUAL_BASE + 0x230 // acknowledge timer interrupt
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#endif
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.set reorder
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#endif // #if !defined(_R98_)
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// End M001
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// S003
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// move a0,s8 // set address of trap frame
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lw a1,HalpCurrentTimeIncrement // set current time increment
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lw t0,__imp_KeUpdateSystemTime // update system time // S005
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jal t0 // // S005
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//
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// The following code is a work around for a bug in the Fusion machines
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// where the clock interrupt is not dismissed by reading the acknowledge
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// register.
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//
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// Start M001
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#if !defined(_R98_)
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#if defined(_JAZZ_)
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.set noreorder
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.set noat
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mfc0 t0,cause // read the cause register
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lw t1,HalpEisaControlBase // get EISA control base address
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sll t0,t0,31 - (CAUSE_INTPEND + CLOCK_LEVEL - 1) // isolate clock bit
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bgez t0,10f // if gez, no clock interrupt pending
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li t2,0x2 // get NMI port enable bit
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lb t3,0x70(t1) // save EISA NMI interrupt disable
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lb t4,0x461(t1) // save EISA extended NMI status
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sb zero,0x70(t1) // clear EISA NMI interrupt disable
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sb t2,0x461(t1) // set EISA NMI port enable
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sb zero,0x462(t1) // generate EISA NMI interrupt
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sb zero,0x461(t1) // clear EISA extended NMI status
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sb t2,0x461(t1) //
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lb zero,0x461(t1) // synchronize clear operatin
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sb t3,0x70(t1) // restore EISA NMI interupt disable
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sb t4,0x461(t1) // restore EISA exteneed NMI status
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lb zero,0x461(t1) // synchronize restore operation
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.set at
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.set reorder
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10: //
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#endif
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#endif // #if !defined(_R98_)
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// End M001
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// S008 vvv
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//
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// Check ECC 1bit error flag.
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//
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lw t0,HalpECC1bitDisableTime // get value of disable time
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beq zero,t0,10f // if ne, check ecc 1bit
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lw t1,HalpCurrentTimeIncrement // get current time increment
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subu t0,t0,t1 // declement disable time
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sw t0,HalpECC1bitDisableTime //
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blez t0,5f // if lez, enable ecc 1bit
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beq zero,zero,10f // not lez,
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5: sw zero,HalpECC1bitDisableTime // clear disable time
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li t0,ECC_ERROR_COUNT_LIMIT // set new flag
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sw t0,HalpECC1bitDisableFlag //
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la t1,KSEG1_BASE+SIC_PHYSICAL_BASE+SIC_DATA_OFFSET+SIC_SET0_OFFSET
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sw zero,0x0(t1) // enable ECC 1bit error
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lw t0,HalpECC1bitScfrBuffer // check connect to SIC1
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andi t0,SCFR_SIC_SET1_CONNECT //
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bne t0,zero,10f //
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la t1,KSEG1_BASE+SIC_PHYSICAL_BASE+SIC_DATA_OFFSET+SIC_SET1_OFFSET
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sw zero,0x0(t1) // enable ECC 1bit error
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// S008 ^^^
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//
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// At each clock interrupt the next time increment is moved to the current
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// time increment to "pipeline" the update of the current increment at the
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// correct time. If the next interval count is nonzero, then the new time
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// increment is moved to the next time increment and the next interval count
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// register is loaded with the specified interval count minus one (i.e., ms).
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//
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10: lw t0,KdDebuggerEnabled // get address of debugger enable // S008
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lw t1,HalpNextIntervalCount // get next interval count
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lw t2,HalpNextTimeIncrement // get the next increment value
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lbu t0,0(t0) // get debugger enable flag
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lw t3,HalpNewTimeIncrement // get new new time increment value
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lw ra,CiRa(sp) // restore return address
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or t4,t1,t0 // set interval count or debugger?
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sw t2,HalpCurrentTimeIncrement // set current increment value
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bne zero,t4,20f // if ne, interval change or debugger
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addu sp,sp,CiFrameLength // deallocate stack frame
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j ra // return
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//
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// The interval count must be changed or the debugger is enabled.
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//
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20: sw zero,HalpNextIntervalCount // clear next interval count
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beq zero,t1,30f // if eq, not interval count change
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subu t1,t1,1 // compute millisecond interval count
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// Start M001
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.set noreorder
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#if !defined(_R98_)
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#if defined(_DUO_)
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sw t1,DMA_VIRTUAL_BASE + 0x1a8 // set next interval count
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#endif
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#if defined(_JAZZ_)
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sw t1,DMA_VIRTUAL_BASE + 0x228 // set next interval count
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#endif
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# else // #if !defined(_R98_)
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sw t1,KSEG1_BASE+PMC_PHYSICAL_BASE1+PMC_LOCAL_OFFSET+0x40(zero) // S004
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#endif // #if !defined(_R98_)
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.set reorder
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// End M001
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sw t3,HalpNextTimeIncrement // set next time increment value
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30: beq zero,t0,40f // if eq, debugger not enabled
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jal KdPollBreakIn // check if breakin is requested
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beq zero,v0,40f // if eq, no breakin requested
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li a0,DBG_STATUS_CONTROL_C // break in and send
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jal DbgBreakPointWithStatus // status to debugger
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40: lw ra,CiRa(sp) // restore return address
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addu sp,sp,CiFrameLength // deallocate stack frame
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j ra // return
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.end HalpClockInterrupt0
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SBTTL("System Clock Interrupt - Processor N")
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//++
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//
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// Routine Description:
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//
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// This routine is entered as the result of an interrupt generated by
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// the interval timer. Its function is to acknowledge the interrupt
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// and transfer control to the standard system routine to update the
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// execution time of the current thread and process.
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//
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// Arguments:
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//
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// a0 - Supplies a pointer to a trap frame. // S003
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalpClockInterrupt1)
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#if !defined(_R98_)
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#if defined(_DUO_)
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lw t0,DMA_VIRTUAL_BASE + 0x58 // acknowledge timer interrupt
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move a0,s8 // set address of trap frame
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j KeUpdateRunTime // update system time
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#endif
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#else // #if !defined(_R98_)
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lw t1,KiPcr + PcPrcb(zero) // get current processor block address
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// S006 vvv
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la t2,HalpChangeIntervalFlg // get change flag of timer interval
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lbu t1,PbNumber(t1) // get processor number
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add t2,t1,t2 // check flag
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lb t1,0x0(t2) // get change flag of this CPU
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beq t1,zero,10f // if eq, no change timer interval
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sb zero,0x0(t2) // clear change flag of timer interval
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// S006 ^^^
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lw t1,HalpChangeIntervalCount // get next interval count
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sw t1,KSEG1_BASE+PMC_PHYSICAL_BASE1+PMC_LOCAL_OFFSET+0x40(zero) // S004
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// Start S003, S005
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//10: move a0,s8 // set address of trap frame
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10: lw t1,__imp_KeUpdateRunTime // update system runtime
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j t1 //
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// End S003, S005
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#endif // #if !defined(_R98_)
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.end HalpClockInterrupt1
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SBTTL("Profile Clock Interrupt")
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//++
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//
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// Routine Description:
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//
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// This routine is entered as the result of an interrupt generated by the
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// profile clock. Its function is to acknowledge the profile interrupt,
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// compute the next compare value, update the performance counter, and
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// transfer control to the standard system routine to process any active
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// profiles.
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//
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// Arguments:
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//
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// a0 - Supplies a pointer to a trap frame. // S003
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalpProfileInterrupt)
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.set noreorder
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.set noat
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// Start M001
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mfc0 t0,count // get current count value
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addu t1,zero,3 // set initial count value
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mtc0 t1,count // set new count register value
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// End M001
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.set at
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.set reorder
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#if 0 // S007
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//#if defined(NT_UP)
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la t1,HalpPerformanceCounter // get performance counter address
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//#else
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#endif
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lw t1,KiPcr + PcPrcb(zero) // get current processor block address
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la t2,HalpPerformanceCounter // get performance counter address
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lbu t1,PbNumber(t1) // get processor number
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sll t1,t1,3 // compute address of performance count
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addu t1,t1,t2 //
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// #endif // S007
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lw t2,LiLowPart(t1) // get low part of performance count
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lw t3,LiHighPart(t1) // get high part of performance count
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addu t2,t2,t0 // update low part of performance count
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sw t2,LiLowPart(t1) // store low part of performance count
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sltu t4,t2,t0 // generate carry into high part
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addu t3,t3,t4 // update high part of performance count
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sw t3,LiHighPart(t1) // store high part of performance count
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// move a0,s8 // set address of trap frame // S003
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lw t4,__imp_KeProfileInterrupt // process profile interrupt // S005
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j t4 // // S005
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.end HalpProfileInterrupt
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SBTTL("Read Count Register")
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//++
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//
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// ULONG
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// HalpReadCountRegister (
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// VOID
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// );
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//
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// Routine Description:
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//
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// This routine reads the current value of the count register and
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// returns the value.
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//
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// Arguments:
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//
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// None.
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//
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// Return Value:
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//
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// Current value of the count register.
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//
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//--
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LEAF_ENTRY(HalpReadCountRegister)
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.set noreorder
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.set noat
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mfc0 v0,count // get count register value
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.set at
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.set reorder
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j ra // return
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.end HalpReadCountRegister
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SBTTL("Write Compare Register And Clear")
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//++
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//
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// ULONG
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// HalpWriteCompareRegisterAndClear (
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// IN ULONG Value
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// );
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//
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// Routine Description:
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//
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// This routine reads the current value of the count register, writes
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// the value of the compare register, clears the count register, and
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// returns the previous value of the count register.
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//
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// Arguments:
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//
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// Value - Supplies the value written to the compare register.
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//
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// Return Value:
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//
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// Previous value of the count register.
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//
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//--
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LEAF_ENTRY(HalpWriteCompareRegisterAndClear)
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.set noreorder
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.set noat
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mfc0 v0,count // get count register value
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mtc0 a0,compare // set compare register value
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li t0,7 // set lost cycle count
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mtc0 t0,count // set count register to zero
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.set at
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.set reorder
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j ra // return
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.end HalpWriteCompareRegisterAndClear
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