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475 lines
13 KiB
475 lines
13 KiB
#ident "@(#) NEC r98reg.h 1.8 95/02/20 17:25:49"
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/*++
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Copyright (c) 1991-1993 Microsoft Corporation
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Module Name:
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r98reg.h
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Abstract:
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This module is the header file that structure I/O registers for the r98.
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Author:
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Revision History:
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--*/
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/*
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***********************************************************************
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*
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* S001 6/10 T.Samezima
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*
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* Del Compile err
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*
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***********************************************************************
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*
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* S002 6/10 T.Samezima
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*
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* Add I/O access macro
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*
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***********************************************************************
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*
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* S003 7/5 T.Samezima
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*
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* Chg define miss
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* structure define miss
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***********************************************************************
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*
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* S004 7/12 T.Samezima
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*
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* Chg structure define change
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*
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***********************************************************************
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*
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* S005 7/14 T.Samezima
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*
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* Chg structure define change
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*
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***********************************************************************
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*
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* S006 7/22 T.Samezima
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*
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* Add define IOB and SIC register dummy read macro
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* (correspondence PMC3 bug)
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*
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* S007 12/24 T.Samezima
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* Add define EIFR register define.
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*
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* S008 '95.1/7 T.Samezima
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* Add define EIF0,STS2 register define.
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*
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* S009 '95.1/11 T.Samezima
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* Del miss define
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*
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*
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*/
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#ifndef _R98REG_
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#define _R98REG_
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//
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// Define PMC register structure.
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//
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typedef struct _PMC_REGISTER {
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ULONG Long;
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ULONG Fill;
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} PMC_REGISTER, *PPMC_REGISTER;
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typedef struct _PMC_LARGE_REGISTER {
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// Start S005
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ULONG High;
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ULONG Low;
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// End S005
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} PMC_LARGE_REGISTER, *PPMC_LARGE_REGISTER;
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typedef volatile struct _PMC_REGISTERS1 {
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// offset(H)
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PMC_LARGE_REGISTER IPR; // 0
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PMC_LARGE_REGISTER MKR; // 8
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PMC_LARGE_REGISTER IPRR; // 10
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PMC_REGISTER IPSR; // 18
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PMC_REGISTER MKRR; // 20
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PMC_REGISTER MKSR; // 28
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PMC_REGISTER NMIR; // 30
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PMC_REGISTER NMIRST; // 38
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PMC_REGISTER TMSR1; // 40
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PMC_REGISTER TMR1; // 48
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PMC_REGISTER TOVCT1; // 50
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PMC_REGISTER TMCR1; // 58
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PMC_REGISTER TMSR2; // 60
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PMC_REGISTER TMR2; // 68
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PMC_REGISTER TOVCT2; // 70
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PMC_REGISTER TMCR2; // 78
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PMC_REGISTER WDTSR; // 80
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PMC_REGISTER WDT; // 88
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PMC_REGISTER WDTCR; // 90
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PMC_REGISTER Reserved1[13]; // 98-F8
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PMC_REGISTER IntIR; // 100
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PMC_REGISTER Reserved2; // 108
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PMC_REGISTER TCIR; // 110
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PMC_REGISTER Reserved3[29]; // 118-1F8
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PMC_REGISTER CTAddr; // 200
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PMC_REGISTER CTData; // 208
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PMC_REGISTER CTCTL; // 210
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PMC_REGISTER EVCNT1H; // 218
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PMC_REGISTER EVCNT1L; // 220
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PMC_REGISTER EVCNTCR1; // 228
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PMC_REGISTER Reserved4[26]; // 230-2F8
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PMC_REGISTER CNFG; // 300
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PMC_REGISTER STSR; // 308
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PMC_REGISTER ERRRST; // 310
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PMC_REGISTER ERR; // 318
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PMC_REGISTER AERR; // 320
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PMC_REGISTER ERRMK; // 328
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PMC_REGISTER TOSR; // 330
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PMC_REGISTER EVCNT0H; // 338
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PMC_REGISTER EVCNT0L; // 340
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PMC_REGISTER EVCNTCR0; // 348
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} PMC_REGISTERS1, *PPMC_REGISTERS1;
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typedef volatile struct _PMC_REGISTERS2 {
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// offset(H)
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PMC_REGISTER RRMT0H; // 0
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PMC_REGISTER RRMT0L; // 8
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PMC_REGISTER RRMT1H; // 10
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PMC_REGISTER RRMT1L; // 18
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PMC_REGISTER RRMT2H; // 20
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PMC_REGISTER RRMT2L; // 28
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PMC_REGISTER RRMT3H; // 30
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PMC_REGISTER RRMT3L; // 38
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PMC_REGISTER RRMT4H; // 40
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PMC_REGISTER RRMT4L; // 48
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PMC_REGISTER RRMT5H; // 50
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PMC_REGISTER RRMT5L; // 58
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PMC_REGISTER RRMT6H; // 60
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PMC_REGISTER RRMT6L; // 68
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PMC_REGISTER RRMT7H; // 70
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PMC_REGISTER RRMT7L; // 78
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PMC_REGISTER Reserved1[2]; // 80-88
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PMC_REGISTER DISCON; // 90
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PMC_REGISTER Reserved2[3]; // 98-a8
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PMC_REGISTER EADRH; // b0
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PMC_REGISTER EADRL; // b8
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PMC_REGISTER Reserved3[2]; // c0-c8
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PMC_REGISTER RTYCNT; // d0
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} PMC_REGISTERS2, *PPMC_REGISTERS2;
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//
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// Define pointer to PMC registers.
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//
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#define PMC_GLOBAL_CONTROL1 ((volatile PPMC_REGISTERS1)(KSEG1_BASE | PMC_PHYSICAL_BASE1))
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#define PMC_GLOBAL_CONTROL2 ((volatile PPMC_REGISTERS2)(KSEG1_BASE | PMC_PHYSICAL_BASE2))
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/* Start S002 */
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#define PMC_GLOBAL_CONTROL1_OR(x) ((volatile PPMC_REGISTERS1)(KSEG1_BASE | PMC_PHYSICAL_BASE1 | (x) ))
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#define PMC_GLOBAL_CONTROL2_OR(x) ((volatile PPMC_REGISTERS2)(KSEG1_BASE | PMC_PHYSICAL_BASE2 | (x) ))
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/* End S002 */
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/* Start S001 */
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#define PMC_CONTROL1 ((volatile PPMC_REGISTERS1)((ULONG)PMC_GLOBAL_CONTROL1 | PMC_LOCAL_OFFSET))
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#define PMC_CONTROL2 ((volatile PPMC_REGISTERS2)((ULONG)PMC_GLOBAL_CONTROL2 | PMC_LOCAL_OFFSET))
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/* End S001 */
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/* Start S002 */
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#define PMC_CONTROL1_OR(x) ((volatile PPMC_REGISTERS1)((ULONG)PMC_GLOBAL_CONTROL1 | PMC_LOCAL_OFFSET | (x) ))
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#define PMC_CONTROL2_OR(x) ((volatile PPMC_REGISTERS2)((ULONG)PMC_GLOBAL_CONTROL2 | PMC_LOCAL_OFFSET | (x) ))
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/* End S002 */
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/* Start S006 */
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//
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// Define dummy read macro. This macro use to not lead to time out of PMC
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//
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#define IOB_DUMMY_READ READ_REGISTER_ULONG(PMC_DUMMY_READ_ADDR)
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#define SIC_DUMMY_READ READ_REGISTER_ULONG(PMC_DUMMY_READ_ADDR)
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/* End S006 */
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//
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// Define IOB register structure.
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//
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typedef struct _IOB_REGISTER {
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ULONG Long;
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ULONG Fill;
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} IOB_REGISTER, *PIOB_REGISTER;
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typedef volatile struct _IOB_REGISTERS {
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// offset(H)
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IOB_REGISTER AIMR; // 0
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IOB_REGISTER AII0; // 8
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IOB_REGISTER AII1; // 10
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IOB_REGISTER AII2; // 18
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IOB_REGISTER AII3; // 20
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IOB_REGISTER AISR; // 28
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IOB_REGISTER ITRR; // 30
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IOB_REGISTER ADC0; // 38
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IOB_REGISTER ADC1; // 40
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IOB_REGISTER ADC2; // 48
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IOB_REGISTER ADC3; // 50
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IOB_REGISTER AMMD; // 58
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IOB_REGISTER ANMD; // 60
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IOB_REGISTER IERR; // 68
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IOB_REGISTER IEMR; // 70
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IOB_REGISTER IEER; // 78
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IOB_REGISTER AMAL; // 80
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IOB_REGISTER AMAH; // 88
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IOB_REGISTER ANAL; // 90
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IOB_REGISTER ANAH; // 98
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IOB_REGISTER AMRC; // a0
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IOB_REGISTER ANRC; // a8
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IOB_REGISTER AMRT; // b0
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IOB_REGISTER ANMT; // b8
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IOB_REGISTER ANST; // c0
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IOB_REGISTER Reserved1[7]; // c8-f8
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IOB_REGISTER ADG0; // 100
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IOB_REGISTER ADG1; // 108
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IOB_REGISTER CNTD; // 110
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IOB_REGISTER CNTE; // 118
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IOB_REGISTER CABS; // 120
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IOB_REGISTER CAWS; // 128
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IOB_REGISTER CTGL; // 130
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IOB_REGISTER CTGH; // 138
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IOB_REGISTER ARMS; // 140
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IOB_REGISTER ARML; // 148
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IOB_REGISTER ARMH; // 150
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IOB_REGISTER Reserved2[21]; // 158-1f8
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IOB_REGISTER SCFR; // 200
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IOB_REGISTER MPER; // 208
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IOB_REGISTER EIMR; // 210
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IOB_REGISTER EIFR; // 218
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IOB_REGISTER Reserved3[28]; // 220-2f8
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// DCDW; // 300
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// IOB_REGISTER ATCNF; // 400
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} IOB_REGISTERS, *PIOB_REGISTERS;
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// S007 vvv
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//
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// Define EIFR register
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//
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typedef struct _EIFR_REGISTER {
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ULONG Reserved : 21;
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ULONG MPDISCN : 1;
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ULONG IOBERR : 1;
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ULONG Reserved2 : 1;
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ULONG EISANMI : 1;
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ULONG LRERR : 1;
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ULONG SIC1ERR : 1;
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ULONG SIC0ERR : 1;
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ULONG PMC3ERR : 1;
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ULONG PMC2ERR : 1;
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ULONG PMC1ERR : 1;
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ULONG PMC0ERR : 1;
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} EIFR_REGISTER, *PEIFR_REGISTER;
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// S007 ^^^
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//
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// Define pointer to IOB registers.
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//
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#define IOB_CONTROL ((volatile PIOB_REGISTERS)(KSEG1_BASE | IOB_PHYSICAL_BASE))
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//
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// Define SIC register structure.
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//
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typedef struct _SIC_REGISTER {
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ULONG Long;
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ULONG Fill;
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} SIC_REGISTER, *PSIC_REGISTER;
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typedef volatile struct _SIC_ERR_REGISTERS {
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// offset(H)
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SIC_REGISTER EIF0; // 0
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SIC_REGISTER EIF1; // 8
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SIC_REGISTER CKE0; // 10
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SIC_REGISTER CKE1; // 18
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SIC_REGISTER SECT; // 20
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SIC_REGISTER Reserved; // 28
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SIC_REGISTER STS1; // 30
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SIC_REGISTER STS2; // 38
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SIC_REGISTER RSRG; // 40
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} SIC_ERR_REGISTERS, *PSIC_ERR_REGISTERS;
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typedef volatile struct _SIC_DATA_REGISTERS {
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// offset(H)
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SIC_REGISTER DPCM; // 0
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SIC_REGISTER DSRG; // 8
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SIC_REGISTER SDLM; // 10
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// SIC_REGISTER Reserved[3]; // 18-28 // S009
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// SIC_REGISTER SDCR; // 30 // S009
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} SIC_DATA_REGISTERS, *PSIC_DATA_REGISTERS;
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// S008 vvv
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//
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// Define EIF0 register
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//
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typedef struct _EIF0_REGISTER {
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ULONG Reserved : 2;
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ULONG EXTD0MBE : 1;
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ULONG EXTD0SBE : 1;
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ULONG Reserved1 : 1;
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ULONG INTD0PTE : 1;
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ULONG INTD0MBE : 1;
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ULONG INTD0SBE : 1;
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ULONG ICEC : 1;
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ULONG CPEC : 1;
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ULONG APEC : 1;
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ULONG RE1C : 1;
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ULONG RE0C : 1;
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ULONG SREC : 1;
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ULONG RSEC : 1;
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ULONG DTEJ : 1;
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ULONG RSEJ : 1;
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ULONG USYC : 1;
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ULONG Reserved2 : 4;
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ULONG IRMC : 1;
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ULONG IRRC : 1;
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ULONG Reserved3 : 3;
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ULONG SBE : 1;
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ULONG DPCG : 1;
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ULONG APCG : 1;
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ULONG MPRG : 1;
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ULONG SWRG : 1;
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} EIF0_REGISTER, *PEIF0_REGISTER;
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//
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// Define STS2 register
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//
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typedef struct _STS2_REGISTER {
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ULONG COL0_9 : 10;
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ULONG COL10 : 1;
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ULONG LOW0_9 : 10;
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ULONG LOW10 : 1;
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ULONG Reserved : 2;
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ULONG RW : 1;
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ULONG EXTMBE0 : 1;
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ULONG EXTSBE0 : 1;
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ULONG MBE0 : 1;
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ULONG SBE0 : 1;
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ULONG SIMN : 1;
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ULONG ARE : 2;
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} STS2_REGISTER, *PSTS2_REGISTER;
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// S008 ^^^
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//
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// Define pointer to SIC registers.
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//
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#define SIC_ERR_CONTROL ((volatile PSIC_ERR_REGISTERS)(KSEG1_BASE | SIC_PHYSICAL_BASE | SIC_ERR_OFFSET))
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#define SIC_DATA_CONTROL ((volatile PSIC_DATA_REGISTERS)(KSEG1_BASE | SIC_PHYSICAL_BASE | SIC_DATA_OFFSET))
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/* Start S002 */
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#define SIC_ERR_CONTROL_OR(x) ((volatile PSIC_ERR_REGISTERS)(KSEG1_BASE | SIC_PHYSICAL_BASE | SIC_ERR_OFFSET | (x) ))
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#define SIC_DATA_CONTROL_OR(x) ((volatile PSIC_DATA_REGISTERS)(KSEG1_BASE | SIC_PHYSICAL_BASE | SIC_DATA_OFFSET | (x) ))
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/* End S002 */
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//
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// Define LR4360 register structure.
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//
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typedef volatile struct _LR_REGISTERS1 {
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/* Start S004 */
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// offset(H)
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ULONG RSTC; // 0x0
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ULONG DPRC; // 0x4
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ULONG Reserved[1024]; // 0x8-0x1004
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ULONG ERRS; // 0x1008
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/* End S004 */
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} LR_REGISTERS1, *PLR_REGISTERS1;
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typedef volatile struct _LR_REGISTERS2 {
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// offset(H)
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ULONG iRPo; // 0
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ULONG iRED; // 4
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ULONG iRRE; // 8
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ULONG iREN; // c
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ULONG iRSF; // 10
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ULONG iPoE; // 14
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ULONG Reserved0[2]; // 18-1c
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ULONG iFGE; // 20
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ULONG iFGi; // 24
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ULONG iRCS0; // 28
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ULONG iRCS1; // 2c
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} LR_REGISTERS2, *PLR_REGISTERS2;
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typedef volatile struct _LR_PCI_DEVICE_REGISTERS {
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// offset(H)
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ULONG PTBAR0; // 0
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ULONG PTBAR1; // 4
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ULONG PTBAR2; // 8
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ULONG PTBAR3; // c
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ULONG PTBAR4; // 10
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ULONG PTBAR5; // 14
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ULONG PTBAR6; // 18
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ULONG PTBAR7; // 1c
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ULONG PTSZR; // 20
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ULONG TPASZR; // 24
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ULONG TFLR; // 28
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ULONG PABAR; // 2c
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ULONG AEAR; // 30
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ULONG PEAR; // 34
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} LR_PCI_DEVICE_REGISTERS, *PLR_PCI_DEVICE_REGISTERS;
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//
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// Define Bbus LR4360 DMA channel register structure.
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//
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typedef struct _DMA_CHANNEL { // offset(H)
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ULONG CnCF; // 0
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ULONG CnDF; // 4
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ULONG CnDC; // 8
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ULONG Reserved1; // c
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ULONG CnMA; // 10
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ULONG CnBC; // 14
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ULONG CnAK; // 18
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ULONG CnFA; // 1c
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ULONG CnCA; // 20
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} DMA_CHANNEL, *PDMA_CHANNEL;
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//
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// Define Device Channel # DMA Configuration register (CnDF register)
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//
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typedef struct _LR_DMA_CONFIG {
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ULONG SWAP :1;
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ULONG ASET :1;
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ULONG ACKP :1;
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ULONG REQP :1;
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ULONG EOPCF :2;
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ULONG EOPHO :1;
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ULONG BUOFF :1;
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ULONG EDEDE :1;
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ULONG EXEDi :1;
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ULONG iNEDE :1;
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ULONG iNEDi :1;
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ULONG CPUTi :1;
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ULONG Reserved1 :3;
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ULONG TMODE :2;
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ULONG Reserved2 :14;
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} LR_DMA_CONFIG,*PLR_DMA_CONFIG;
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//
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// Define Device Channel # DMA Control register (CnDC register)
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//
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typedef struct _LR_DMA_CONTROL {
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ULONG REQiE :1;
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ULONG REQii :1;
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ULONG REQWE :1;
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ULONG REQiS :1;
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ULONG MEMWT :1;
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ULONG MEMWE :1;
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ULONG Reserved1:2;
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ULONG EXEDS :1;
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ULONG iNEDS :1;
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ULONG CREQS :1;
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ULONG CERRS :1;
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ULONG BFiFo :4;
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ULONG FiFoV :1;
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ULONG FiFoD :1;
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ULONG FiFoF :1;
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ULONG CHACOM :1;
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ULONG Reserved2 :12;
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} LR_DMA_CONTROL,*PLR_DMA_CONTROL;
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//
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// Define pointer to LR4360 registers.
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//
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#define LR_CONTROL1 ((volatile PLR_REGISTERS1)(KSEG1_BASE | LR_PHYSICAL_CMNBASE1))
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#define LR_CONTROL2 ((volatile PLR_REGISTERS2)(KSEG1_BASE | LR_PHYSICAL_CMNBASE2))
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#define LR_PCI_DEV_REG_CONTROL ((volatile PLR_PCI_DEVICE_REGISTERS)(KSEG1_BASE | LR_PHYSICAL_PCI_DEV_REG_BASE))
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#endif // _R98REG_
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