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556 lines
16 KiB
556 lines
16 KiB
#ident "@(#) NEC xxinitnt.c 1.18 95/03/17 11:59:37"
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/*++
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Copyright (c) 1991-1994 Microsoft Corporation
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Module Name:
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xxinitnt.c
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Abstract:
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This module implements the interrupt initialization for a MIPS R3000
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or R4000 system.
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--*/
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/*
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* Original source: Build Number 1.612
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*
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* Modify for R98(MIPS/R4400)
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*
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***********************************************************************
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*
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* L001 94.03/22-5/13 T.Samezima
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*
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* add control of Eif interrupt.
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* make table of change from iRRE bit number to NABus code.
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* make table of arbitration table and arbitration pointer.
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* make variable for access of registers.
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* connect the timer interrupt service routine.
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* clear unknown interrupt counter
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*
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* del only '#if defined(_DUO_)'
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* '#if defined(_JAZZ_)' with content
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* HalpCountInterrupt()
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*
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* change interrupt control
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* various vector of interrupt service routine
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*
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***********************************************************************
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*
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* S002 94.5/17 T.Samezima
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*
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* del Arbitration table
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*
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***********************************************************************
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*
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* S003 94.6/10-14 T.Samezima
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*
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* del Compile err
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*
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***********************************************************************
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*
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* S004 94.7/7 T.Samezima
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*
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* Chg Use UNKNOWN_COUNT_BUF_LEN to max
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* for HalpUnknownInterruptCount
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*
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***********************************************************************
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*
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* S005 94.7/7 T.Samezima
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*
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* Del move interrupt arbitration pointer to r98dspt.c
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*
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***********************************************************************
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*
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* S006 94.7/23 T.Samezima
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*
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* Add Enable EIF interrupt on SIC.
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*
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***********************************************************************
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*
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* S007 94.8/22 T.Samezima on SNES
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*
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* Chg Register buffer size from USHORT to ULONG
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* Value of set to MKSR register
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* Condition change
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*
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* Add Clear interrupt pending bit on edge level interrupt
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*
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* Del Move EISA NMI enable logic to HalpCreateEisaStructure()
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*
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***********************************************************************
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*
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* S008 94.9/5 T.Samezima
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*
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* Add Institute number of repeat for interrupt clear loop
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*
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***********************************************************************
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*
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* S009 94.9/16 T.Samezima
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*
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* Chg Only CPU#0 on I/O Initerrupt clear
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*
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***********************************************************************
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*
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* S00a 94.10/14 T.Samezima
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*
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* Fix Version Up at build807
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* -Move Int1 interrupt enable to allstart.c
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*
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* S00b 94.10/18 T.Samezima
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* Chg Enable interrupt on MKR register only exist device,
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*
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* S00c 94.12/06 T.Samezima
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* Bug Disable ECC 1bit error interrupt.
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*
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* S00d 94.12/06 T.Samezima
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* Add Disable NMI
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*
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* S00e 95.01/10 T.Samezima
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* Add Enable ECC 1bit error interrupt
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* Rewrite cycle start on ecc 1bit error
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*
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* S00f 95.01/24 T.Samezima
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* Add Disable rewrite cycle on ecc 1bit error
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*
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* S010 95.03/13 T.Samezima
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* Add Enable HW cache flush.
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*
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*/
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#include "halp.h"
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#include "eisa.h" // S003
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//
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// Put all code for HAL initialization in the INIT section. It will be
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// deallocated by memory management when phase 1 initialization is
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// completed.
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//
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#if defined(ALLOC_PRAGMA)
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#pragma alloc_text(INIT, HalpInitializeInterrupts)
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#endif
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//
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// Define global data for builtin device interrupt enables.
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//
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ULONG HalpBuiltinInterruptEnable; // S007
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//
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// Define the IRQL mask and level mapping table.
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//
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// These tables are transfered to the PCR and determine the priority of
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// interrupts.
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//
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// N.B. The two software interrupt levels MUST be the lowest levels.
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//
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UCHAR HalpIrqlMask[] = {4, 5, 6, 6, 7, 7, 7, 7, // 0000 - 0111 high 4-bits
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8, 8, 8, 8, 8, 8, 8, 8, // 1000 - 1111 high 4-bits
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0, 1, 2, 2, 3, 3, 3, 3, // 0000 - 0111 low 4-bits
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4, 4, 4, 4, 4, 4, 4, 4}; // 1000 - 1111 low 4-bits
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UCHAR HalpIrqlTable[] = {0xff, // IRQL 0
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0xfe, // IRQL 1
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0xfc, // IRQL 2
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0xf8, // IRQL 3
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0xf0, // IRQL 4
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0xe0, // IRQL 5
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0xc0, // IRQL 6
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0x80, // IRQL 7
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0x00}; // IRQL 8
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/* Start L001 */
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//
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// Define table of change from iRRE bit number to NABus code
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//
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ULONG HalpNaBusCodeTable[] = {0x8000, 0x0010, // iRRE bit0,1
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0x0006, 0x0000, // iRRE bit2,3
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0x0002, 0x0002, // iRRE bit4,5
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0x000a, 0x000a, // iRRE bit6,7
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0x0008, 0x000c, // iRRE bit8,9
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0x8000, 0x8000, // iRRE bit10,11
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0x8000, 0x8000, // iRRE bit12,13
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0x8000, 0x8000, // iRRE bit14,15
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0x8000, 0x0004, // iRRE bit16,17
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0x8000, 0x8000, // iRRE bit18,19
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0x8000, 0x8000, // iRRE bit20,21
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0x000c, 0x8000, // iRRE bit22,23
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0x8000, 0x8000, // iRRE bit24,25
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0x8000, 0x8000, // iRRE bit26,27
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0x8000, 0x8000, // iRRE bit28,29
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0x8000, 0x8000 }; // iRRE bit30,31
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//
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// Define table of order of interrupt arbitration
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//
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ULONG HalpUnknownInterruptCount[UNKNOWN_COUNT_BUF_LEN]; // S004
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/* End L001*/
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BOOLEAN
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HalpInitializeInterrupts (
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VOID
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)
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/*++
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Routine Description:
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This function initializes interrupts for a Jazz or Duo MIPS system.
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N.B. This function is only called during phase 0 initialization.
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Arguments:
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None.
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Return Value:
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A value of TRUE is returned if the initialization is successfully
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completed. Otherwise a value of FALSE is returned.
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--*/
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{
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USHORT DataShort;
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ULONG DataLong;
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ULONG Index;
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PKPRCB Prcb;
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/* Start L001 */
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ULONG pmcRegisterAddr;
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ULONG pmcRegisterUpperPart;
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ULONG pmcRegisterLowerPart;
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ULONG bitCount;
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ULONG buffer;
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ULONG buffer2; // S006
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UCHAR charBuffer;
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LONG repeatCounter; // S008
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/* End L001 */
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//
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// Get the address of the processor control block for the current
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// processor.
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//
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Prcb = PCR->Prcb;
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//
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// Initialize the IRQL translation tables in the PCR. These tables are
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// used by the interrupt dispatcher to determine the new IRQL and the
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// mask value that is to be loaded into the PSR. They are also used by
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// the routines that raise and lower IRQL to load a new mask value into
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// the PSR.
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//
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for (Index = 0; Index < sizeof(HalpIrqlMask); Index += 1) {
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PCR->IrqlMask[Index] = HalpIrqlMask[Index];
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}
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for (Index = 0; Index < sizeof(HalpIrqlTable); Index += 1) {
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PCR->IrqlTable[Index] = HalpIrqlTable[Index];
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}
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/* Start L001 */
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//
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// All interrupt disables.
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//
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pmcRegisterAddr = (ULONG)( &(PMC_CONTROL1)->MKR ); // S003
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pmcRegisterUpperPart = MKR_DISABLE_ALL_INTERRUPT_HIGH;
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pmcRegisterLowerPart = MKR_DISABLE_ALL_INTERRUPT_LOW;
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HalpWriteLargeRegister( pmcRegisterAddr,
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&pmcRegisterUpperPart,
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&pmcRegisterLowerPart );
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//
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// If processor 0 is being initialized, then set all device
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// interrupt disables.
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//
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if (Prcb->Number == 0) {
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HalpBuiltinInterruptEnable = iREN_DISABLE_ALL_INTERRUPT;
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for (Index = 0; Index < UNKNOWN_COUNT_BUF_LEN; Index += 1) { // S004
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HalpUnknownInterruptCount[Index] = 0;
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}
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// } // S009
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/* End L001 */
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//
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// Disable individual device interrupts and make sure no device interrupts
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// are pending.
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//
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/* Start L001 */
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WRITE_REGISTER_ULONG( &( LR_CONTROL2 )->iREN,
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HalpBuiltinInterruptEnable );
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WRITE_REGISTER_ULONG( &( IOB_CONTROL )->EIMR.Long,
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EIMR_DISABLE_ALL_EIF );
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repeatCounter = 0; // S008
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while( ((DataLong = READ_REGISTER_ULONG( &( LR_CONTROL2 )->iRRE) & iRRE_MASK) != 0) &&
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(++repeatCounter < 16) ) { // S008
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for( bitCount = 0 ; bitCount <= 31 ; bitCount++ ) {
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if( (DataLong & ( 1 << bitCount )) != 0) {
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// Start S007
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if( bitCount < 15 ){
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WRITE_REGISTER_ULONG( &( LR_CONTROL2 )->iRSF,
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( 1 << bitCount ) );
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}
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// End S007
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WRITE_REGISTER_ULONG( &( IOB_CONTROL )->AIMR.Long,
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HalpNaBusCodeTable[bitCount] );
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}
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}
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WRITE_REGISTER_ULONG( &( LR_CONTROL2 )->iRSF,
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iRSF_CLEAR_INTERRUPT );
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pmcRegisterAddr = (ULONG)( &(PMC_CONTROL1)->IPRR ); // S003
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pmcRegisterUpperPart = 0x0;
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pmcRegisterLowerPart = 0xffffffff;
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HalpWriteLargeRegister( pmcRegisterAddr,
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&pmcRegisterUpperPart,
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&pmcRegisterLowerPart );
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}
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/* End L001 */
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HalpBuiltinInterruptEnable |= 0x10; // S010
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//
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// If processor 0 is being initialized, then enable device interrupts.
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//
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// if (Prcb->Number == 0) { // S009
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/* Start L001 */
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//
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// Enable INT0-1 interrupt on PMC
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//
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/* Start S003 */
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WRITE_REGISTER_ULONG( &( IOB_CONTROL )->AII0.Long,
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AII_INIT_DATA );
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WRITE_REGISTER_ULONG( &( IOB_CONTROL )->AII1.Long,
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AII_INIT_DATA );
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WRITE_REGISTER_ULONG( &( IOB_CONTROL )->AII2.Long,
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AII_INIT_DATA );
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WRITE_REGISTER_ULONG( &( IOB_CONTROL )->AII3.Long,
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AII_INIT_DATA );
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/* End S003 */
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pmcRegisterAddr = (ULONG)( &(PMC_CONTROL1)->MKR ); // S003
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HalpReadLargeRegister( pmcRegisterAddr,
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&pmcRegisterUpperPart,
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&pmcRegisterLowerPart );
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pmcRegisterLowerPart = ( pmcRegisterLowerPart
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| MKR_INT0_DEVICE_ENABLE_LOW // S00b
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// | MKR_INT1_DEVICE_ENABLE_LOW // S00a, S00b
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| MKR_INT2_DEVICE_ENABLE_LOW // S00b
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); // S003
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HalpWriteLargeRegister( pmcRegisterAddr,
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&pmcRegisterUpperPart,
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&pmcRegisterLowerPart );
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// DataLong = READ_REGISTER_ULONG(&((PDMA_REGISTERS)DMA_VIRTUAL_BASE)->InterruptEnable.Long);
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// DataLong |= ENABLE_DEVICE_INTERRUPTS;
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// WRITE_REGISTER_ULONG(&((PDMA_REGISTERS)DMA_VIRTUAL_BASE)->InterruptEnable.Long,
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// DataLong);
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/* End L001 */
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}
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/* Start L001 */
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//
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// Connect the eif interrupt to the eif interrupt routine
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//
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PCR->InterruptRoutine[EIF_LEVEL] = HalpEifDispatch;
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//
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// Enable the eif interrupt
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//
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pmcRegisterAddr = (ULONG)( &(PMC_CONTROL1)->MKR ); // S003
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HalpReadLargeRegister( pmcRegisterAddr,
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&pmcRegisterUpperPart,
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&pmcRegisterLowerPart );
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pmcRegisterUpperPart = ( pmcRegisterUpperPart | MKR_INT5_ENABLE_HIGH );
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pmcRegisterLowerPart = ( pmcRegisterLowerPart | MKR_INT5_ENABLE_LOW );
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HalpWriteLargeRegister( pmcRegisterAddr,
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&pmcRegisterUpperPart,
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&pmcRegisterLowerPart );
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buffer = READ_REGISTER_ULONG( &( PMC_CONTROL1 )->STSR.Long);
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buffer = (buffer | STSR_EIF_ENABLE);
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#if defined(DISABLE_NMI) // S00d
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buffer = (buffer | STSR_NMI_DISABLE);
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#endif
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WRITE_REGISTER_ULONG( &( PMC_CONTROL1 )->STSR.Long, buffer);
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WRITE_REGISTER_ULONG( &( PMC_CONTROL1 )->ERRMK.Long, ERRMK_EIF_ENABLE);
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WRITE_REGISTER_ULONG( &( IOB_CONTROL )->IEMR.Long, IEMR_ENABLE_ALL_EIF);
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WRITE_REGISTER_ULONG( &( IOB_CONTROL )->EIMR.Long, EIMR_ENABLE_ALL_EIF);
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/* Start S006 */
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buffer = READ_REGISTER_ULONG( &( IOB_CONTROL )->SCFR.Long );
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IOB_DUMMY_READ;
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if( (buffer & SCFR_SIC_SET0_CONNECT) == 0 ) { // S007
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buffer2 = READ_REGISTER_ULONG( &(SIC_ERR_CONTROL_OR(SIC_NO0_OFFSET))->CKE0.Long );
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buffer2 &= CKE0_DISABLE_SBE; // S00c
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buffer2 |= CKE0_ENABLE_ALL_EIF;
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WRITE_REGISTER_ULONG( &( SIC_ERR_CONTROL_OR(SIC_SET0_OFFSET) )->CKE0.Long,
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buffer2
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);
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// S00e vvv
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buffer2 = READ_REGISTER_ULONG( &(SIC_DATA_CONTROL_OR(SIC_NO0_OFFSET))->DPCM.Long );
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buffer2 &= DPCM_ENABLE_MASK; // S00c
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WRITE_REGISTER_ULONG( &( SIC_DATA_CONTROL_OR(SIC_SET0_OFFSET) )->DPCM.Long,
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buffer2
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);
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#if 0 // S00f
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WRITE_REGISTER_ULONG( &( SIC_ERR_CONTROL_OR(SIC_SET0_OFFSET) )->SECT.Long,
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SECT_REWRITE_ENABLE
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);
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#endif
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// S00e ^^^
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WRITE_REGISTER_ULONG( &( SIC_ERR_CONTROL_OR(SIC_SET0_OFFSET) )->CKE1.Long,
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CKE1_ENABLE_ALL_EIF
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);
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}
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if( (buffer & SCFR_SIC_SET1_CONNECT) == 0 ) { // S007
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buffer2 = READ_REGISTER_ULONG( &(SIC_ERR_CONTROL_OR(SIC_NO2_OFFSET))->CKE0.Long );
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buffer2 &= CKE0_DISABLE_SBE; // S00c
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buffer2 |= CKE0_ENABLE_ALL_EIF;
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WRITE_REGISTER_ULONG( &( SIC_ERR_CONTROL_OR(SIC_SET1_OFFSET) )->CKE0.Long,
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buffer2
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);
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// S00e vvv
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buffer2 = READ_REGISTER_ULONG( &(SIC_DATA_CONTROL_OR(SIC_NO2_OFFSET))->DPCM.Long );
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buffer2 &= DPCM_ENABLE_MASK; // S00c
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WRITE_REGISTER_ULONG( &( SIC_DATA_CONTROL_OR(SIC_SET1_OFFSET) )->DPCM.Long,
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buffer2
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);
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#if 0 // S00f
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WRITE_REGISTER_ULONG( &( SIC_ERR_CONTROL_OR(SIC_SET1_OFFSET) )->SECT.Long,
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SECT_REWRITE_ENABLE
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);
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#endif
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// S00e ^^^
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WRITE_REGISTER_ULONG( &( SIC_ERR_CONTROL_OR(SIC_SET1_OFFSET) )->CKE1.Long,
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CKE1_ENABLE_ALL_EIF
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);
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}
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/* End S006 */
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// S007
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//
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// If processor 0 is being initialized, then connect the interval timer
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// interrupt to the stall interrupt routine so the stall execution count
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// can be computed during phase 1 initialization. Otherwise, connect the
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// interval timer interrupt to the appropriate interrupt service routine
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// and set stall execution count from the computation made on processor
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// 0.
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//
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PCR->InterruptRoutine[TIMER_LEVEL] = HalpTimerDispatch; // S003
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if (Prcb->Number == 0) {
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/* Start L001 */
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PCR->InterruptRoutine[CLOCK_VECTOR] = HalpStallInterrupt;
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/* End L001 */
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} else {
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/* Start L001 */
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PCR->InterruptRoutine[CLOCK_VECTOR] = HalpClockInterrupt1;
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/* End L001 */
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PCR->StallScaleFactor = HalpStallScaleFactor;
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}
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//
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// Initialize the interval timer to interrupt at the specified interval.
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//
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/* Start L001 */
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WRITE_REGISTER_ULONG( &( PMC_CONTROL1 )->TMSR1.Long, CLOCK_INTERVAL);
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//
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// Initialize the profile timer to interrupt at the default interval.
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//
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WRITE_REGISTER_ULONG( &( PMC_CONTROL1 )->TMSR2.Long,
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DEFAULT_PROFILETIMER_COUNT);
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/* End L001 */
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//
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// Enable the interval timer interrupt on the current processor.
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//
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/* Start L001 */
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WRITE_REGISTER_ULONG( &( PMC_CONTROL1 )->MKSR.Long, 0x3f-IPR_CLOCK_BIT_NO); // S007
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WRITE_REGISTER_ULONG( &( PMC_CONTROL1 )->TMCR1.Long, 0x3);
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/* End L001 */
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//
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// If processor 0 is being initialized, then connect the count/compare
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// interrupt to the count interrupt routine to handle early count/compare
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// interrupts during phase 1 initialization. Otherwise, connect the
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// count\comapre interrupt to the appropriate interrupt service routine.
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//
|
|
|
|
/* Start L001 */
|
|
if (Prcb->Number != 0) {
|
|
PCR->InterruptRoutine[PROFILE_VECTOR] = HalpProfileInterrupt;
|
|
WRITE_REGISTER_ULONG( &( PMC_CONTROL1 )->MKSR.Long, 0x3f-IPR_PROFILE_BIT_NO); // S007
|
|
WRITE_REGISTER_ULONG( &( PMC_CONTROL1 )->TMCR2.Long, 0x3);
|
|
}
|
|
/* End L001 */
|
|
|
|
//
|
|
// Connect the interprocessor interrupt service routine and enable
|
|
// interprocessor interrupts.
|
|
//
|
|
|
|
PCR->InterruptRoutine[IPI_LEVEL] = HalpIpiInterrupt;
|
|
|
|
/*Start L001 */
|
|
pmcRegisterAddr = (ULONG)( &(PMC_CONTROL1)->MKR ); // S003
|
|
HalpReadLargeRegister( pmcRegisterAddr,
|
|
&pmcRegisterUpperPart,
|
|
&pmcRegisterLowerPart );
|
|
pmcRegisterUpperPart = ( pmcRegisterUpperPart | MKR_INT4_ENABLE_HIGH );
|
|
pmcRegisterLowerPart = ( pmcRegisterLowerPart | MKR_INT4_ENABLE_LOW );
|
|
HalpWriteLargeRegister( pmcRegisterAddr,
|
|
&pmcRegisterUpperPart,
|
|
&pmcRegisterLowerPart );
|
|
/*End L001 */
|
|
|
|
//
|
|
// Reserve the local device interrupt vector for exclusive use by the HAL.
|
|
//
|
|
|
|
|
|
/* Start L001 */
|
|
// PCR->ReservedVectors |= (1 << DEVICE_LEVEL);
|
|
// PCR->ReservedVectors |= (1 << INT1_LEVEL); // S00a
|
|
PCR->ReservedVectors |= (1 << INT2_LEVEL);
|
|
/* End L001 */
|
|
|
|
return TRUE;
|
|
}
|