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544 lines
16 KiB
544 lines
16 KiB
/*++
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Copyright (c) 1993 Microsoft Corporation
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Copyright (c) 1994 Digital Equipment Corporation
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Module Name:
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pintolin.h
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Abstract:
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This file includes the platform-dependent Pin To Line Tables
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Author:
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Environment:
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Kernel mode
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Revision History:
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James Livingston (Digital) 23-June-1994
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Extracted Sable table from common.
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Dick Bissen [DEC] 12-May-1994
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Changed EB66PCIPinToLineTable for pass2 of the module.
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--*/
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//
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// These tables represent the mapping from slot number and interrupt pin
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// into a PCI Interrupt Vector.
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// On Mustang and EB66, the interrupt vector is Interrupt Request Register bit
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// representing that interrupt + 1.
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// On EB66, the value also represents the Interrupt Mask Register Bit,
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// since it is identical to the Interrupt Read Register. On Mustang,
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// the Interrupt Mask Register only allows masking of all interrupts
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// from the two plug-in slots.
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//
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// Formally, these mappings can be expressed as:
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//
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// PCIPinToLine:
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// SlotNumber.DeviceNumber x InterruptPin -> InterruptLine
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//
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// LineToVector:
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// InterruptLine -> InterruptVector
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//
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// VectorToIRRBit:
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// InterruptVector -> InterruptRequestRegisterBit
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//
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// VectorToIMRBit:
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// InterruptVector -> InterruptMaskRegisterBit
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//
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// SlotNumberToIDSEL:
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// SlotNumber.DeviceNumber -> IDSEL
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//
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// subject to following invariants (predicates must always be true):
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//
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// Slot.DeviceNumber in {0,...,15}
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//
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// InterruptPin in {1, 2, 3, 4}
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//
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// InterruptRequestRegisterBit in {0,...,15}
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//
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// InterruptMaskRegisterBit in {0,...,15}
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//
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// PCIPinToLine(SlotNumber.DeviceNumber, InterruptPin) =
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// PCIPinToLineTable[SlotNumber.DeviceNumber, InterruptPin]
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// (Table-lookup function initialized below)
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//
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// LineToVector(InterruptLine) = PCI_VECTORS + InterruptLine
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//
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// VectorToIRRBit(InterruptVector) = InterruptVector - 1
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//
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// VectorToIMRBit(InterruptVector) [see below]
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//
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// SlotNumberToIDSEL(SlotNumber.DeviceNumber) = (1 << (Slot.DeviceNumber+11))
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//
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// where:
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//
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// SlotNumber.DeviceNumber:
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// Alpha AXP Platforms receive interrupts on local PCI buses only, which
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// are limited to 16 devices (PCI AD[11]-AD[26]). (We loose AD[17]-AD[31]
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// since PCI Config space is a sparse space, requiring a five-bit shift.)
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//
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// InterruptPin:
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// Each virtual slot has up to four interrupt pins INTA#, INTB#, INTC#, INTD#,
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// as per the PCI Spec. V2.0, Section 2.2.6. (FYI, only multifunction devices
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// use INTB#, INTC#, INTD#.)
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//
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// PCI configuration space indicates which interrupt pin a device will use
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// in the InterruptPin register, which has the values:
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//
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// INTA# = 1, INTB#=2, INTC#=3, INTD# = 4
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//
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// Note that there may be up to 8 functions/device on a PCI multifunction
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// device plugged into the option slots, e.g., Slot #0.
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// Each function has its own PCI configuration space, addressed
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// by the SlotNumber.FunctionNumber field, and will identify which
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// interrput pin of the four it will use in its own InterruptPin register.
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//
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// If the option is a PCI-PCI bridge, interrupts across the bridge will
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// somehow be combined to appear on some combination of the four
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// interrupt pins that the bridge plugs into.
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//
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// InterruptLine:
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// This PCI Configuration register, unlike x86 PC's, is maintained by
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// software and represents offset into PCI interrupt vectors.
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// Whenever HalGetBusData or HalGetBusDataByOffset is called,
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// HalpPCIPinToLine() computes the correct InterruptLine register value
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// by using the SablePCIPinToLineTable mapping.
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//
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// InterruptRequestRegisterBit:
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// 0xff is used to mark an invalid IRR bit, hence an invalid request
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// for a vector. Also, note that the 16 bits of the EB66 IRR must
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// be access as two 8-bit reads.
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//
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// InterruptMaskRegisterBit:
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// On EB66, the PinToLine table may also be find the to write the
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// InterruptMaskRegister. Formally, we can express this invariant as
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//
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// VectorToIMRBit(InterrruptVector) = InterruptVector - 1
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//
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// On Mustang, the table is useless. The InterruptMaskRegister has
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// only two bits the completely mask all interrupts from either
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// Slot #0 or Slot#1 (PCI AD[17] and AD[18]):
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//
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// InterruptVector in {3,4,5,6} then VectorToIMRBit(InterruptVector) = 0
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// InterruptVector in {7,8,9,10} then VectorToIMRBit(InterruptVector) = 1
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//
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// IDSEL:
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// For accessing PCI configuration space on a local PCI bus (as opposed
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// to over a PCI-PCI bridge), type 0 configuration cycles must be generated.
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// In this case, the IDSEL pin of the device to be accessed is tied to one
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// of the PCI Address lines AD[11] - AD[26]. (The function field in the
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// PCI address is used should we be accessing a multifunction device.)
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// Anyway, virtual slot 0 represents the device with IDSEL = AD[11], and
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// so on.
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//
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#if 0
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//
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// The following PinToLineTable is used with old
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// Standard I/O boards that didn't have the 5th 8259.
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// The 5th 8259 (Slave 3) was added to break out the
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// PCI A,B,C,D interrupts to separate interrupt pins.
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//
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ULONG OldSablePCIPinToLineTable[][4] = {
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{ EthernetPortVector, // Virtual Slot 0 = PCI_AD[11] Tulip
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EthernetPortVector,
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EthernetPortVector,
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EthernetPortVector },
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{ ScsiPortVector, // Virtual Slot 1 = PCI_AD[12] SCSI
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ScsiPortVector,
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ScsiPortVector,
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ScsiPortVector },
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 2 = PCI_AD[13] Eisa Bridge
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 3 = PCI_AD[14] Not used
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 4 = PCI_AD[15] Not used
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 5 = PCI_AD[16] Not used
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{ OldPciSlot0Vector, // Virtual Slot 6 = PCI_AD[17] Phys. Slot #0
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OldPciSlot0Vector,
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OldPciSlot0Vector,
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OldPciSlot0Vector },
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{ OldPciSlot1Vector, // Virtual Slot 7 = PCI_AD[18] Phys. Slot #1
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OldPciSlot1Vector,
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OldPciSlot1Vector,
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OldPciSlot1Vector },
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{ OldPciSlot2Vector, // Virtual Slot 8 = PCI_AD[19] Phys. Slot #2
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OldPciSlot2Vector,
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OldPciSlot2Vector,
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OldPciSlot2Vector },
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 9 = PCI_AD[20] Not used
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{ 0xff, 0xff, 0xff, 0xff } // Virtual Slot 10 = PCI_AD[21] Not used
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};
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#endif
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//
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// Interrupt Vector Table Mapping for Sable (PCI 0)
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//
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ULONG SablePinToLineTable[][4] = {
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{ EthernetPortVector, // Virtual Slot 0 = PCI_AD[11] Tulip
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EthernetPortVector,
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EthernetPortVector,
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EthernetPortVector },
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{ ScsiPortVector, // Virtual Slot 1 = PCI_AD[12] SCSI
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ScsiPortVector,
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ScsiPortVector,
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ScsiPortVector },
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 2 = PCI_AD[13] Eisa Bridge
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 3 = PCI_AD[14] Not used
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 4 = PCI_AD[15] Not used
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 5 = PCI_AD[16] Not used
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{ PciSlot0AVector, // Virtual Slot 6 = PCI_AD[17] Phys. Slot #0
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PciSlot0BVector,
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PciSlot0CVector,
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PciSlot0DVector },
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{ PciSlot1AVector, // Virtual Slot 7 = PCI_AD[18] Phys. Slot #1
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PciSlot1BVector,
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PciSlot1CVector,
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PciSlot1DVector },
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{ PciSlot2AVector, // Virtual Slot 8 = PCI_AD[19] Phys. Slot #2
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PciSlot2BVector,
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PciSlot2CVector,
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PciSlot2DVector },
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 9 = PCI_AD[20] Not used
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{ 0xff, 0xff, 0xff, 0xff } // Virtual Slot 10 = PCI_AD[21] Not used
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};
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//
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// Interrupt Vector Table Mapping for Lynx (PCI 0)
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//
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ULONG LynxPinToLineTable1[][4] = {
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{ LynxReservedVector, // Virtual slot 0 - reserved
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LynxReservedVector,
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LynxReservedVector,
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LynxReservedVector },
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{ LynxReservedVector, // Virtual slot 1 - reserved
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LynxReservedVector,
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LynxReservedVector,
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LynxReservedVector },
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{ LynxReservedVector, // Virtual slot 2 - PCI-EISA Bridge
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LynxReservedVector,
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LynxReservedVector,
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LynxReservedVector },
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{ LynxReservedVector, // Virtual slot 3 - PCI-PCI Bridge
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LynxReservedVector,
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LynxReservedVector,
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LynxReservedVector },
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{ LynxScsi0Vector, // Virtual slot 4 - NCRC810A
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LynxReservedVector,
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LynxReservedVector,
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LynxReservedVector },
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{ LynxReservedVector, // Virtual slot 5 - reserved
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LynxReservedVector,
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LynxReservedVector,
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LynxReservedVector },
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{ LynxPciSlot4AVector, // Virtual slot 6 - PCI slot 4
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LynxPciSlot4BVector,
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LynxPciSlot4CVector,
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LynxPciSlot4DVector },
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{ LynxPciSlot5AVector, // Virtual slot 7 - PCI slot 5
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LynxPciSlot5BVector,
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LynxPciSlot5CVector,
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LynxPciSlot5DVector },
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{ LynxPciSlot6AVector, // Virtual slot 8 - PCI slot 6
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LynxPciSlot6BVector,
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LynxPciSlot6CVector,
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LynxPciSlot6DVector },
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{ LynxPciSlot7AVector, // Virtual slot 9 - PCI slot 7
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LynxPciSlot7BVector,
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LynxPciSlot7CVector,
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LynxPciSlot7DVector },
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{ LynxReservedVector, // Virtual slot 10 - reserved
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LynxReservedVector,
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LynxReservedVector,
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LynxReservedVector }
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};
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ULONG LynxPinToLineTable2[][4] = {
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{ RmLpLynxEthVector, // Virtual slot 0 - dc21040 for RM/LP
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LynxReservedVector,
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LynxReservedVector,
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LynxReservedVector },
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{ LynxScsi1Vector, // Virtual slot 1 - NCRC810A (SCSI)
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LynxReservedVector,
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LynxReservedVector,
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LynxReservedVector },
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{ LynxReservedVector, // Virtual slot 2 - reserved
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LynxReservedVector,
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LynxReservedVector,
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LynxReservedVector },
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{ LynxReservedVector, // Virtual slot 3 - reserved
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LynxReservedVector,
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LynxReservedVector,
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LynxReservedVector },
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{ LynxReservedVector, // Virtual slot 4 - reserved
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LynxReservedVector,
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LynxReservedVector,
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LynxReservedVector },
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{ LynxReservedVector, // Virtual slot 5 - reserved
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LynxReservedVector,
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LynxReservedVector,
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LynxReservedVector },
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{ LynxPciSlot0AVector, // Virtual slot 6 - PCI slot 0
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LynxPciSlot0BVector,
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LynxPciSlot0CVector,
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LynxPciSlot0DVector },
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{ LynxPciSlot1AVector, // Virtual slot 7 - PCI slot 1
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LynxPciSlot1BVector,
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LynxPciSlot1CVector,
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LynxPciSlot1DVector },
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{ LynxPciSlot2AVector, // Virtual slot 8 - PCI slot 2
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LynxPciSlot2BVector,
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LynxPciSlot2CVector,
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LynxPciSlot2DVector },
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{ LynxPciSlot3AVector, // Virtual slot 9 - PCI slot 3
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LynxPciSlot3BVector,
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LynxPciSlot3CVector,
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LynxPciSlot3DVector },
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{ LynxReservedVector, // Virtual slot 10 - reserved
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LynxReservedVector,
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LynxReservedVector,
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LynxReservedVector },
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{ LynxReservedVector, // Virtual slot 11 - reserved
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LynxReservedVector,
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LynxReservedVector,
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LynxReservedVector },
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{ LynxReservedVector, // Virtual slot 12 - reserved
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LynxReservedVector,
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LynxReservedVector,
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LynxReservedVector },
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{ LynxReservedVector, // Virtual slot 13 - reserved
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LynxReservedVector,
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LynxReservedVector,
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LynxReservedVector },
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{ LynxReservedVector, // Virtual slot 14 - reserved
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LynxReservedVector,
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LynxReservedVector,
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LynxReservedVector },
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{ LynxReservedVector, // Virtual slot 15 - reserved
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LynxReservedVector,
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LynxReservedVector,
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LynxReservedVector }
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};
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#ifdef XIO_PASS1
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//
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// Interrupt Vector Table Mapping for XIO (Pass 1)
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//
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ULONG XioPinToLineTable[][4] = {
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{ XioReservedVector, // Virtual slot 0 - reserved
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XioReservedVector,
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XioReservedVector,
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XioReservedVector },
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{ XioPciSlot0AVector, // Virtual Slot 1 = PCI Slot 0
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XioPciSlot0BVector,
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XioPciSlot0CVector,
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XioPciSlot0DVector },
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{ XioPciSlot1AVector, // Virtual Slot 2 = PCI Slot 1
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XioPciSlot1BVector,
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XioPciSlot1CVector,
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XioPciSlot1DVector }
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};
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#endif // XIO_PASS1
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#ifdef XIO_PASS2
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//
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// Interrupt Vector Table Mapping for XIO (Pass 2)
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//
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ULONG XioPinToLineTable1[][4] = {
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{ XioReservedVector, // Virtual slot 0 - reserved
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XioReservedVector,
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XioReservedVector,
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XioReservedVector },
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{ XioReservedVector, // Virtual slot 1 - reserved
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XioReservedVector,
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XioReservedVector,
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XioReservedVector },
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{ XioReservedVector, // Virtual slot 2 - reserved
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XioReservedVector,
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XioReservedVector,
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XioReservedVector },
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{ XioReservedVector, // Virtual slot 3 - PCI-PCI Bridge
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XioReservedVector,
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XioReservedVector,
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XioReservedVector },
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{ XioReservedVector, // Virtual slot 4 - reserved
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XioReservedVector,
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XioReservedVector,
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XioReservedVector },
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{ XioReservedVector, // Virtual slot 5 - reserved
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XioReservedVector,
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XioReservedVector,
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XioReservedVector },
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{ XioPciSlot4AVector, // Virtual slot 6 - PCI slot 4
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XioPciSlot4BVector,
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XioPciSlot4CVector,
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XioPciSlot4DVector },
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{ XioPciSlot5AVector, // Virtual slot 7 - PCI slot 5
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XioPciSlot5BVector,
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XioPciSlot5CVector,
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XioPciSlot5DVector },
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{ XioPciSlot6AVector, // Virtual slot 8 - PCI slot 6
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XioPciSlot6BVector,
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XioPciSlot6CVector,
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XioPciSlot6DVector },
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{ XioPciSlot7AVector, // Virtual slot 9 - PCI slot 7
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XioPciSlot7BVector,
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XioPciSlot7CVector,
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XioPciSlot7DVector },
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{ XioReservedVector, // Virtual slot 10 - reserved
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XioReservedVector,
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XioReservedVector,
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XioReservedVector }
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};
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ULONG XioPinToLineTable2[][4] = {
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{ XioReservedVector, // Virtual slot 0 - reserved
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XioReservedVector,
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XioReservedVector,
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XioReservedVector },
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{ XioReservedVector, // Virtual slot 1 - reserved
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XioReservedVector,
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XioReservedVector,
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XioReservedVector },
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{ XioReservedVector, // Virtual slot 2 - reserved
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XioReservedVector,
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XioReservedVector,
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XioReservedVector },
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{ XioReservedVector, // Virtual slot 3 - reserved
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XioReservedVector,
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XioReservedVector,
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XioReservedVector },
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{ XioReservedVector, // Virtual slot 4 - reserved
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XioReservedVector,
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XioReservedVector,
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XioReservedVector },
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{ XioReservedVector, // Virtual slot 5 - reserved
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XioReservedVector,
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XioReservedVector,
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XioReservedVector },
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{ XioPciSlot0AVector, // Virtual slot 6 - PCI slot 0
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XioPciSlot0BVector,
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XioPciSlot0CVector,
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XioPciSlot0DVector },
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{ XioPciSlot1AVector, // Virtual slot 7 - PCI slot 1
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XioPciSlot1BVector,
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XioPciSlot1CVector,
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XioPciSlot1DVector },
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{ XioPciSlot2AVector, // Virtual slot 8 - PCI slot 2
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XioPciSlot2BVector,
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XioPciSlot2CVector,
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XioPciSlot2DVector },
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{ XioPciSlot3AVector, // Virtual slot 9 - PCI slot 3
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XioPciSlot3BVector,
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XioPciSlot3CVector,
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XioPciSlot3DVector },
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{ XioReservedVector, // Virtual slot 10 - reserved
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XioReservedVector,
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XioReservedVector,
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XioReservedVector },
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{ XioReservedVector, // Virtual slot 11 - reserved
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XioReservedVector,
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XioReservedVector,
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XioReservedVector },
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{ XioReservedVector, // Virtual slot 12 - reserved
|
|
XioReservedVector,
|
|
XioReservedVector,
|
|
XioReservedVector },
|
|
|
|
{ XioReservedVector, // Virtual slot 13 - reserved
|
|
XioReservedVector,
|
|
XioReservedVector,
|
|
XioReservedVector },
|
|
|
|
{ XioReservedVector, // Virtual slot 14 - reserved
|
|
XioReservedVector,
|
|
XioReservedVector,
|
|
XioReservedVector },
|
|
|
|
{ XioReservedVector, // Virtual slot 15 - reserved
|
|
XioReservedVector,
|
|
XioReservedVector,
|
|
XioReservedVector }
|
|
};
|
|
|
|
#endif // XIO_PASS2
|