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205 lines
4.0 KiB
205 lines
4.0 KiB
/*++
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Copyright (c) 1993 Digital Equipment Corporation
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Module Name:
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ebmapio.c
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Abstract:
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This module contains the functions to map HAL-accessed I/O addresses
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on the Sable system.
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Author:
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Joe Notarangelo 25-Oct-1993
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Environment:
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Kernel mode
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Revision History:
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--*/
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#include "halp.h"
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#include "isaaddr.h"
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//
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// Define global data used to locate the EISA control space.
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//
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PVOID HalpEisaControlBase;
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PVOID HalpEisaIntAckBase;
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PVOID HalpCMOSRamBase;
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//
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// Define the array that maps logical processor numbers to the corresponding
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// QVA for that processor's CPU CSRs.
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//
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PSABLE_CPU_CSRS HalpSableCpuCsrs[HAL_MAXIMUM_PROCESSOR+1];
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BOOLEAN
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HalpMapIoSpace (
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VOID
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)
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/*++
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Routine Description:
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This routine maps the HAL I/O space for a Sable
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system using the Quasi VA.
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Arguments:
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None.
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Return Value:
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If the initialization is successfully completed, then a value of TRUE
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is returned. Otherwise, a value of FALSE is returned.
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--*/
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{
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PVOID PciIoSpaceBase;
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#if !defined(AXP_FIRMWARE)
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PKPRCB Prcb;
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extern HalpLogicalToPhysicalProcessor[HAL_MAXIMUM_PROCESSOR+1];
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Prcb = PCR->Prcb;
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//
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// Assign CPU specific CSR address
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//
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switch( HalpLogicalToPhysicalProcessor[Prcb->Number] ) {
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case SABLE_CPU0:
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HAL_PCR->IpirSva = SABLE_CPU0_IPIR_PHYSICAL | SUPERPAGE_ENABLE;
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HAL_PCR->CpuCsrsQva = SABLE_CPU0_CSRS_QVA;
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HalpSableCpuCsrs[Prcb->Number] = SABLE_CPU0_CSRS_QVA;
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break;
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case SABLE_CPU1:
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HAL_PCR->IpirSva = SABLE_CPU1_IPIR_PHYSICAL | SUPERPAGE_ENABLE;
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HAL_PCR->CpuCsrsQva = SABLE_CPU1_CSRS_QVA;
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HalpSableCpuCsrs[Prcb->Number] = SABLE_CPU1_CSRS_QVA;
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break;
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case SABLE_CPU2:
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HAL_PCR->IpirSva = SABLE_CPU2_IPIR_PHYSICAL | SUPERPAGE_ENABLE;
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HAL_PCR->CpuCsrsQva = SABLE_CPU2_CSRS_QVA;
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HalpSableCpuCsrs[Prcb->Number] = SABLE_CPU2_CSRS_QVA;
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break;
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case SABLE_CPU3:
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HAL_PCR->IpirSva = SABLE_CPU3_IPIR_PHYSICAL | SUPERPAGE_ENABLE;
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HAL_PCR->CpuCsrsQva = SABLE_CPU3_CSRS_QVA;
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HalpSableCpuCsrs[Prcb->Number] = SABLE_CPU3_CSRS_QVA;
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break;
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default:
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#ifdef HALDBG
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DbgPrint("HalpMapIoSpace: Invalid Cpu number %d\n", Prcb->Number);
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DbgBreakPoint();
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#else
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;
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#endif // HALDBG
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}
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#endif // AXP_FIRMWARE
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//
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// Map EISA control space.
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//
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PciIoSpaceBase = HAL_MAKE_QVA( SABLE_PCI0_SPARSE_IO_PHYSICAL );
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HalpEisaControlBase = PciIoSpaceBase;
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HalpCMOSRamBase = (PVOID)
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( (ULONG)HAL_MAKE_QVA( SABLE_PCI0_SPARSE_IO_PHYSICAL ) +
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CMOS_ISA_PORT_ADDRESS );
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//
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// Map the real-time clock registers.
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//
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HalpRtcAddressPort = (PVOID)((ULONG)PciIoSpaceBase + RTC_ISA_ADDRESS_PORT);
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HalpRtcDataPort = (PVOID)((ULONG)PciIoSpaceBase + RTC_ISA_DATA_PORT);
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return TRUE;
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}
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ULONG
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HalpMapDebugPort(
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IN ULONG ComPort,
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OUT PULONG ReadQva,
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OUT PULONG WriteQva
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)
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/*++
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Routine Description:
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This routine maps the debug com port so that the kernel debugger
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may function - if called it is called very earlier in the boot sequence.
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Arguments:
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ComPort - Supplies the number of the com port to use as the debug port.
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ReadQva - Receives the QVA used to access the read registers of the debug
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port.
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WriteQva - Receives the QVA used to access the write registers of the
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debug port.
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Return Value:
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Returns the base bus address of the device used as the debug port.
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--*/
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{
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ULONG ComPortAddress;
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ULONG PortQva;
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//
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// Compute the port address, based on the desired com port.
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//
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switch( ComPort ){
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case 1:
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ComPortAddress = COM1_ISA_PORT_ADDRESS;
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break;
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case 2:
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default:
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ComPortAddress = COM2_ISA_PORT_ADDRESS;
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}
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//
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// Return the QVAs for read and write access.
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//
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PortQva = (ULONG)HAL_MAKE_QVA(SABLE_PCI0_SPARSE_IO_PHYSICAL) +
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ComPortAddress;
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*ReadQva = PortQva;
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*WriteQva = PortQva;
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return ComPortAddress;
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}
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