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148 lines
4.4 KiB
148 lines
4.4 KiB
/*++
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Copyright (c) 1995 Digital Equipment Corporation
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Module Name:
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xioref.h
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Abstract:
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This file defines the structures and definitions of the XIO
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interrupt architecture.
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Author:
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Dave Richards 12-May-1995
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Environment:
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Kernel mode
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Revision History:
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--*/
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#ifndef _XIOREFH_
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#define _XIOREFH_
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#ifndef _LANGUAGE_ASSEMBLY
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#ifdef XIO_PASS1
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typedef struct _XIO_INTERRUPT_CSRS{
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UCHAR InterruptAcknowledge; // IO Address 0x0532
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UCHAR Filler0; //
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UCHAR MasterControl; // IO Address 0x0534
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UCHAR MasterMask; // IO Address 0x0535
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UCHAR SlaveControl; // IO Address 0x0536
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UCHAR SlaveMask; // IO Address 0x0537
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} XIO_INTERRUPT_CSRS, *PXIO_INTERRUPT_CSRS;
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enum _XIO_INTERRUPT_VECTORS {
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XioMasterBaseVector = 0x30,
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XioReservedVector = 0x30,
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XioSlaveCascadeVector,
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XioMasterPassiveReleaseVector = 0x37,
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XioSlaveBaseVector = 0x38,
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XioPciSlot0AVector = 0x38,
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XioPciSlot0BVector,
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XioPciSlot0CVector,
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XioPciSlot0DVector,
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XioPciSlot1AVector,
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XioPciSlot1BVector,
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XioPciSlot1CVector,
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XioPciSlot1DVector,
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XioSlavePassiveReleaseVector = 0x3f,
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};
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#endif // XIO_PASS1
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#ifdef XIO_PASS2
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enum _XIO_INTERRUPT_VECTORS {
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XioBaseVector = 0xc0, // XIO Base Vector
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XioReservedVector = 0xc0, //
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XioIcIcIrq0 = 0xc0, //
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XioIcIcIrq1, //
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XioIcIcIrq2, //
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XioIcIcIrq3, //
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XioIcIcIrq4, //
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XioIcIcIrq5, //
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XioIcIcIrq6, //
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XioIcIcIrq7, //
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XioIcIcIrq8, //
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XioIcIcIrq9, //
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XioIcIcIrq10, //
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XioIcIcIrq11, //
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XioIcIcIrq12, //
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XioIcIcIrq13, //
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XioIcIcIrq14, //
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XioIcIcIrq15, //
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XioIcIcIrq16, //
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XioIcIcIrq17, //
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XioIcIcIrq18, //
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XioIcIcIrq19, //
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XioIcIcIrq20, //
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XioIcIcIrq21, //
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XioIcIcIrq22, //
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XioIcIcIrq23, //
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XioIcIcIrq24, //
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XioIcIcIrq25, //
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XioIcIcIrq26, //
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XioIcIcIrq27, //
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XioIcIcIrq28, //
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XioIcIcIrq29, //
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XioIcIcIrq30, //
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XioIcIcIrq31, //
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XioPciSlot4AVector, // PCI Slot 4 A
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XioPciSlot4BVector, // PCI Slot 4 B
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XioPciSlot4CVector, // PCI Slot 4 C
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XioPciSlot4DVector, // PCI Slot 4 D
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XioPciSlot5AVector, // PCI Slot 5 A
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XioPciSlot5BVector, // PCI Slot 5 B
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XioPciSlot5CVector, // PCI Slot 5 C
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XioPciSlot5DVector, // PCI Slot 5 D
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XioPciSlot6AVector, // PCI Slot 6 A
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XioPciSlot6BVector, // PCI Slot 6 B
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XioPciSlot6CVector, // PCI Slot 6 C
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XioPciSlot6DVector, // PCI Slot 6 D
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XioPciSlot7AVector, // PCI Slot 7 A
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XioPciSlot7BVector, // PCI Slot 7 B
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XioPciSlot7CVector, // PCI Slot 7 C
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XioPciSlot7DVector, // PCI Slot 7 D
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XioPciSlot0AVector, // PCI Slot 0 A
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XioPciSlot0BVector, // PCI Slot 0 B
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XioPciSlot0CVector, // PCI Slot 0 C
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XioPciSlot0DVector, // PCI Slot 0 D
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XioPciSlot1AVector, // PCI Slot 1 A
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XioPciSlot1BVector, // PCI Slot 1 B
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XioPciSlot1CVector, // PCI Slot 1 C
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XioPciSlot1DVector, // PCI Slot 1 D
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XioPciSlot2AVector, // PCI Slot 2 A
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XioPciSlot2BVector, // PCI Slot 2 B
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XioPciSlot2CVector, // PCI Slot 2 C
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XioPciSlot2DVector, // PCI Slot 2 D
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XioPciSlot3AVector, // PCI Slot 3 A
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XioPciSlot3BVector, // PCI Slot 3 B
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XioPciSlot3CVector, // PCI Slot 3 C
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XioPciSlot3DVector // PCI Slot 3 D
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};
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#endif // XIO_PASS2
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//
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// The following variable indicates whether an XIO module is present
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// in the system.
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//
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extern BOOLEAN HalpXioPresent;
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#endif // _LANGUAGE_ASSEMBLY
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#endif // _XIOREFH_
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