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139 lines
5.4 KiB
139 lines
5.4 KiB
//#pragma comment(exestr, "$Header: /usr4/winnt/SOURCES/ddk35/src/hal/halsni/mips/RCS/sniregs.h,v 1.1 1994/10/13 15:47:06 holli Exp $")
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/*++
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Copyright (c) 1993 SNI
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Module Name:
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SNIregs.h
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Abstract:
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This module is the header file that describes hardware structures
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for the system board registers
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The System addresses are found in SNIdef.h
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--*/
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#ifndef _SNIREGS_
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#define _SNIREGS_
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/*******************************************************************
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** Description of the R4x000 ASIC Chipset registers for SNI Machines
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**
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** 32 bits access only
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*******************************************************************/
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//
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// UCONF register
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//
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#define UCONF_ENSCMODE (1<<0) /* Secondary mode valid for R4000 */
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#define UCONF_ENEXTINT (1<<1) /* External interruption request */
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#define UCONF_NMI (1<<5) /* Interrupt level for NMI */
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#define UCONF_NMI_MSK (1<<6) /* Interrupt mask for NMI */
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#define UCONF_MDINT (1<<7) /* Select test mode for interruptions */
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#define UCONF_INT0_MSK (1<<8) /* Interrupt mask for INT0 ( eisa ) */
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#define UCONF_INT1_MSK (1<<9) /* Interrupt mask for INT1 ( scci 1, 2 ) */
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#define UCONF_INT2_MSK (1<<10) /* Interrupt mask for INT2 ( duart 2681 ) */
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#define UCONF_INT3_MSK (1<<11) /* Interrupt mask for INT3 ( timer 8254 ) */
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#define UCONF_INT4_MSK (1<<12) /* Interrupt mask for INT4 ( lance ) */
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#define UCONF_INT5_MSK (1<<13) /* Interrupt mask for INT5 ( dbg button ) */
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#define UCONF_INT0 (1<<14) /* Interrupt level for INT0 ( eisa ) */
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#define UCONF_INT1 (1<<15) /* Interrupt level for INT1 ( scci 1, 2 ) */
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#define UCONF_INT2 (1<<16) /* Interrupt level for INT2 ( duart 2681 ) */
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#define UCONF_INT3 (1<<17) /* Interrupt level for INT3 ( timer 8254 ) */
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#define UCONF_INT4 (1<<18) /* Interrupt level for INT4 ( lance ) */
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#define UCONF_INT5 (1<<19) /* Interrupt level for INT5 ( dbg button ) */
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#define UCONF_ENCPUHIT (1<<20) /* Enable address comparators */
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#define UCONF_ENCKDATA (1<<25) /* Enable check bits on data read */
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#define UCONF_SYSCMD0 (1<<26)
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#define UCONF_SYSCMD1 (1<<27)
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#define UCONF_SYSCMD2 (1<<28)
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#define UCONF_SYSCMD3 (1<<29)
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#define UCONF_INT UCONF_INT4|UCONF_INT0
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//
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// IOADTIMEOUT2 & IOADTIMEOUT1
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//
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#define IO_HOLD (1<<0) /* The R4K_CS request the IO bus */
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#define IO_HLDA (1<<1) /* The IO arbitrer acknowledge */
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#define IO_HWR (1<<3) /* Set to 1 for a write IO cycle */
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#define IO_HADR_MASK 0x3FFFFFF8 /* IO address (29:3) in progress */
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//
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// IOMEMCONF
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//
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#define IOMEM_RAFPER 8 /* Select Refresh Period */
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#define IOMEM_SELRC (1<<4) /* Select fast Ttc time on memory */
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#define IOMEM_SELRAF (1<<5) /* Select fast refresh precharge */
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#define IOMEM_SELSIDE (1<<6) /* Select dual side SIPS */
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#define IOMEM_SELDD (1<<7) /* Select DD pattern for memory */
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#define IOMEM_SEL16MB (1<<8) /* Select 16 Mb technology SIPS */
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#define IOMEM_SELDHOLD (1<<9) /* Select long hold time on data write */
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#define IOMEM_DISHLDA (1<<15) /* Mask arbitrer acknowledge */
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#define IOMEM_ENRDCMP (1<<16) /* Enable anticipation on IO read */
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#define IOMEM_ENWRCMP (1<<20) /* Enable bufferisation on IO write */
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#define IOMEM_ENIOTMOUT (1<<21) /* Enable output timeout */
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#define IOMEM_SELIODD (1<<22) /* Enable fast mode for IO burst DD */
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#define IOMEM_MDTIMEOUT (1<<23) /* Select short timeout */
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#define BANK_16 0
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#define BANK_32 IOMEM_SELSIDE
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#define BANK_64 IOMEM_SEL16MB
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#define BANK_128 IOMEM_SEL16MB | IOMEM_SELSIDE
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#define IOMEM_INIT IOMEM_RAFPER /* Initial register load */
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//
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// IOMMU
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//
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#define IOMMU_SWAP 0x7fff /* all segments swapped */
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#define IOMMU_BITS 0x0000 /* all segments 32 bits */
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//
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// DMACCESS & DMAHIT
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//
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#define DMA_COUNT_MASK 0x0000FFFF /* Count mask (15:0) */
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//
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// MACHINE STATUS REGISTER (MSR)
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//
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/* SNI machine status register information */
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#define MSR_VSYNC (1<<0) /* active high - video synchronization */
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#define MSR_TEMP (1<<1) /* active high - excessive temperature */
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#define MSR_LINEGOOD (1<<2) /* active low - power good */
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#define MSR_TIMER1 (1<<3) /* active low - int timer 1 */
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#define MSR_TIMER0 (1<<4) /* active low - int timer 0 */
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#define MSR_DBG_BUT (1<<5) /* active low - debug button int */
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#define MSR_TIMEOUT (1<<6) /* active low - timeout int */
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#define MSR_BAT_EN (1<<7) /* active high - batteries connected */
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//
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// MACHINE CONFIGURATION REGISTER (MCR)
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//
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/* SNI machine configuration register */
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#define MCR_TEMPBATACK (1<<0) /* active high - Disable / clear TEMP an Temp info */
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#define MCR_POWER_OFF (1<<1) /* active high - Stop power */
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#define MCR_STOP_BAT (1<<2) /* active high - Stop batteries */
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#define MCR_PODD (1<<3) /* active high - Select ODD parity R4K_CS */
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#define MCR_INRESET (1<<5) /* active high - Reset board */
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#define MCR_ENBREAK (1<<7) /* active high - Enable Break Duart B machine reset */
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#define LINEGOOD_L MSR_LINEGOOD /* high : powerfail */
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#endif // _SNIREGS_
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