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1201 lines
34 KiB
1201 lines
34 KiB
//#pragma comment(exestr, "$Header: /usr4/winnt/SOURCES/halpcims/src/hal/halsnipm/mips/RCS/snidisp.c,v 1.5 1996/03/04 13:24:39 pierre Exp $")
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/*++
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Copyright (c) 1993-94 Siemens Nixdorf Informationssysteme AG
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Copyright (c) 1991-93 Microsoft Corporation
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Module Name:
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SNIdisp.c
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Abstract:
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This module implements the HAL display initialization and output routines
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for the different SNI machines.
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At the moment we know about the following boards:
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WEITEK P9100 PCIBUS (not in the HAL at the moment...)
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MATROX STORM PCIBUS ( 80x50 Alpha Mode)
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Cirrus 5434 PCI cards ( 80x50 Alpha Mode)
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Standard (unknown) VGA on PCI( 80x50 Alpha Mode)
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If we can not identify the board, we don't initialise the display and we call
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the vendor printf to display strings.
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At the boot phase all I/O is done via the unmapped uncached Segment (KSEG1) of the
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R4000 (HalpEisaControlBase); later with the mapped value of HalpEisaControlBase
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Memory is always accessed via unmapped/uncached (KSEG1) area
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Environment:
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Kernel mode
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Revision History:
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Removed HalpInitializeDisplay1, because we do no longer use the P9000 in graphic mode ...
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NOTE:
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We did use our own ...MoveMemory() instead of RtlMoveMemory(),
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as there is a Hardware bug in our machine and RtlMoveMemory uses
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the floating point registers for fast 64 bit move and on our bus
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only 32 bit can be found ... :-)
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--*/
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#include "halp.h"
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#include "string.h"
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#include "vgadata.h"
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#define MEGA_MOVE_MEMORY(D,S,L) MegaMoveMemory(D,S,L) // orig. RtlMoveMemory()
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//
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// supported VGA text modi
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//
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typedef enum _TEXT_MODE {
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TEXT_80x50,
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TEXT_132x50
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} TEXT_MODE;
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//
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// Define forward referenced procedure prototypes.
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//
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extern VOID
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HalpReadPCIConfig (
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IN ULONG BusNumber,
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IN ULONG Slot,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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);
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VOID HalpDisplaySmallCharacter (IN UCHAR Character);
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VOID HalpOutputSmallCharacter (IN PUCHAR Font);
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VOID HalpInitializeVGADisplay(TEXT_MODE TextMode);
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VOID HalpClearVGADisplay (VOID);
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VOID HalpDisplayVGAString (PUCHAR String);
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VOID HalpPutVGACharacter (UCHAR Character);
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VOID HalpNextVGALine (VOID);
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VOID HalpScrollVGADisplay (VOID);
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VOID DownLoadVGAFont (VOID);
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VOID HalpResetS3Chip (VOID);
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VOID HalpResetCirrusChip (VOID);
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VOID HalpResetP9000 (VOID);
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VOID HalpResetMatroxStorm (VOID);
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VOID HalpVGASetup (VOID);
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VOID HalpDoNoSetup (VOID);
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typedef
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VOID
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(*PHALP_CONTROLLER_SETUP) (
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VOID
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);
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//
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// Supported board definitions.
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//
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typedef enum _VIDEO_BOARD {
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S3_GENERIC, // Standard S3 based Card (miro crystal 8s)
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S3_GENERIC_VLB, // Standard S3 based Card (Local Bus)
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CIRRUS_GENERIC, // Generic Cirrus VGA (Cirrus CL54xx)
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CIRRUS_GENERIC_VLB, // Generic Cirrus VGA (Cirrus CL54xx) (Local Bus)
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CIRRUS_ONBOARD, // The Desktop onboard VGA (Cirrus CL5434)
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VGA_GENERIC, // generic (unknown) VGA
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VGA_GENERIC_VLB, // generic (unknown) VGA on the Vesa Local BUS
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MATROX_STORM,
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VIDEO_BOARD_UNKNOWN // unknown Display Adapter
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} VIDEO_BOARD;
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//
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// some supported VGA chips
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//
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typedef enum _VIDEO_CHIP {
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S3,
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CIRRUS,
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VGA, // generic (unknown) VGA
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VGA_P9000,
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VGA_STORM,
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VIDEO_CHIP_UNKNOWN
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} VIDEO_CHIP;
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typedef struct _VIDEO_BOARD_INFO {
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PUCHAR FirmwareString;
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PHALP_CONTROLLER_SETUP ControllerSetup;
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VIDEO_BOARD VideoBoard;
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VIDEO_CHIP VideoChip;
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} VIDEO_BOARD_INFO, *PVIDEO_BOARD_INFO;
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VIDEO_BOARD_INFO KnownVideoBoards[] = {
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{"VGA ON PCIBUS", HalpVGASetup , VGA_GENERIC, VGA },
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{"CIRRUS 5434 PCIBUS", HalpVGASetup , CIRRUS_GENERIC, CIRRUS},
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{"MATROX STORM PCIBUS", HalpVGASetup , MATROX_STORM , VGA_STORM }
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};
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LONG numVideoBoards = sizeof (KnownVideoBoards) / sizeof(VIDEO_BOARD_INFO);
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//
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// Define static data.
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//
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VIDEO_BOARD HalpVideoBoard = VIDEO_BOARD_UNKNOWN;
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VIDEO_CHIP HalpVideoChip = VIDEO_CHIP_UNKNOWN;
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PHALP_CONTROLLER_SETUP HalpDisplayControllerSetup = HalpDoNoSetup;
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ULONG HalpColumn;
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ULONG HalpRow;
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ULONG HalpDisplayText;
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ULONG HalpDisplayWidth;
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ULONG HalpScrollLength;
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ULONG HalpScrollLine;
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ULONG HalpBytesPerRow;
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PVOID HalpVGAControlBase=( PVOID)( EISA_IO); // Base Address for VGA register access
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PUSHORT VideoBuffer = ( PUSHORT)( EISA_MEMORY_BASE + 0xb8000);
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PUCHAR FontBuffer = ( PUCHAR )( EISA_MEMORY_BASE + 0xa0000);
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BOOLEAN HalpFirstBoot = TRUE;
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ULONG HalpMgaStormBase = 0;
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ULONG Halpval40;
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ULONG HalpMatroxBus,HalpMatroxSlot;
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//
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// Declare externally defined data.
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//
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BOOLEAN HalpDisplayOwnedByHal;
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PHAL_RESET_DISPLAY_PARAMETERS HalpReturnToVga;
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//
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// Put all code for HAL initialization in the INIT section. It will be
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// deallocated by memory management when phase 1 initialization is
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// completed.
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//
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#if defined(ALLOC_PRAGMA)
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#pragma alloc_text(INIT, HalpInitializeDisplay0)
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#pragma alloc_text(INIT, HalpInitializeDisplay1)
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#endif
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VOID MegaMoveMemory(
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OUT PVOID Destination,
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IN PVOID Source,
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IN ULONG Length
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)
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/*++
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Our private function written to substitute the RtlMoveMemory()
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function (64 bit problem).
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--*/
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{
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ULONG lo_index_ul;
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PULONG Dst, Src;
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Dst = (PULONG)Destination;
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Src = (PULONG)Source;
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for (lo_index_ul=0; lo_index_ul < Length/sizeof(ULONG); lo_index_ul++)
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*Dst++ = *Src++;
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}
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BOOLEAN
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HalpInitializeDisplay0 (
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IN PLOADER_PARAMETER_BLOCK LoaderBlock
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)
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/*++
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Routine Description:
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This routine maps the video memory and control registers into the user
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part of the idle process address space, initializes the video control
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registers, and clears the video screen.
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Arguments:
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LoaderBlock - Supplies a pointer to the loader parameter block.
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Return Value:
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If the initialization is successfully completed, than a value of TRUE
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is returned. Otherwise, a value of FALSE is returned.
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--*/
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{
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PCONFIGURATION_COMPONENT_DATA ConfigurationEntry;
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PVIDEO_BOARD_INFO VideoBoard;
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LONG Index;
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ULONG MatchKey;
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//
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// Find the configuration entry for the first display controller.
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//
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MatchKey = 0;
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ConfigurationEntry = KeFindConfigurationEntry(LoaderBlock->ConfigurationRoot,
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ControllerClass,
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DisplayController,
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&MatchKey);
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if (ConfigurationEntry == NULL) {
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return FALSE;
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}
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//
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// Determine which video controller is present in the system.
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// N.B. Be carefull with debug prints during Phase 0, it
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// will kill the initial break point request from the debugger ...
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//
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for( Index=0, VideoBoard = KnownVideoBoards; Index < numVideoBoards; Index++, VideoBoard++) {
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if (!strcmp( ConfigurationEntry->ComponentEntry.Identifier,
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VideoBoard->FirmwareString
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)) {
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HalpVideoBoard = VideoBoard->VideoBoard;
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HalpVideoChip = VideoBoard->VideoChip;
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HalpDisplayControllerSetup = VideoBoard->ControllerSetup;
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break;
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}
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}
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if (Index >= numVideoBoards) {
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HalpVideoBoard = VIDEO_BOARD_UNKNOWN;
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HalpVideoChip = VIDEO_CHIP_UNKNOWN;
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HalpDisplayControllerSetup = HalpVGASetup;
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//
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// let's see, if the bios emulator can initialize the card ....
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//
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HalpDisplayWidth = 80;
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HalpDisplayText = 25;
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return TRUE;
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}
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//
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// Initialize the display controller.
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//
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HalpDisplayControllerSetup();
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HalpFirstBoot = FALSE;
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return TRUE;
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}
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BOOLEAN
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HalpInitializeDisplay1 (
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IN PLOADER_PARAMETER_BLOCK LoaderBlock
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)
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/*++
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Routine Description:
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This routine normally allocates pool for the OEM font file, but
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in this version we use only VGA facilities of the Grapgic boards
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so we simply return TRUE
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Arguments:
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LoaderBlock - Supplies a pointer to the loader parameter block.
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Return Value:
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TRUE
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--*/
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{
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return TRUE;
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}
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VOID
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HalAcquireDisplayOwnership (
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IN PHAL_RESET_DISPLAY_PARAMETERS ResetDisplayParameters
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)
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/*++
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Routine Description:
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This routine switches ownership of the display away from the HAL to
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the system display driver. It is called when the system has reached
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a point during bootstrap where it is self supporting and can output
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its own messages. Once ownership has passed to the system display
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driver any attempts to output messages using HalDisplayString must
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result in ownership of the display reverting to the HAL and the
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display hardware reinitialized for use by the HAL.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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//
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// Set HAL ownership of the display to false.
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//
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HalpDisplayOwnedByHal = FALSE;
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HalpReturnToVga = ResetDisplayParameters;
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return;
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}
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VOID
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HalpDoNoSetup(
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VOID
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)
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/*++
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Routine Description:
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This routine does nothing...
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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HalpDisplayOwnedByHal = TRUE;
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return;
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}
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VOID
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HalpVGASetup(
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VOID
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)
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/*++
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Routine Description:
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This routine initializes a VGA based Graphic card
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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UCHAR byte;
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HalpVGAControlBase = (PVOID)HalpEisaControlBase;
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VideoBuffer = ( PUSHORT)( EISA_MEMORY_BASE + 0xb8000);
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FontBuffer = ( PUCHAR )( EISA_MEMORY_BASE + 0xa0000);
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//
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// if "only" VGA is detected look for an S3 or cirrus chip (VGA ON ATBUS)
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// if the firmware detects an S3 chip, look if this is an 805i (interleave)
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//
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if ((HalpVideoChip == VGA) || (HalpVideoChip == S3)){
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WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x1206); // look for Cirrus chips
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byte = READ_REGISTER_UCHAR(VGA_SEQ_DATA); // read it back
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if (byte != 0x12) { // no cirrus
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WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x4838); // unlock the S3 regs
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WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xa539); // Unlock the SC regs
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WRITE_REGISTER_UCHAR(VGA_CRT_IDX, 0x30); // look for s3 chip id
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byte = READ_REGISTER_UCHAR(VGA_CRT_DATA) ; // look only for major id
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switch (byte & 0xf0){
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case 0xa0: // 801/805 chipset
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if (byte == 0xa8) { // the new 805i (interleave)
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// DebugPrint(("HAL: Found the new 805i Chip resetting to 805 mode\n"));
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WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0053);
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WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0067);
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}
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case 0x80:
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case 0x90:
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// DebugPrint(("HAL: Found S3 Chip set - Chip id 0x%x\n",byte));
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HalpVideoChip = S3;
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WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0038); // lock s3 regs
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WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0039); // lock more s3 regs
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break;
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default: DebugPrint(("HAL: This seems to be no S3 Chip\n"));
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}
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} else { // this may be an cirrus
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WRITE_REGISTER_UCHAR(VGA_CRT_IDX, 0x27); // cirrus id reg
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byte = READ_REGISTER_UCHAR(VGA_CRT_DATA);
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if ((byte & 0xe0) == 0x80) { // look for 100xxxxx
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// DebugPrint(("HAL: Found Cirrus Chip set - Chip id 0x%x\n",byte));
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HalpVideoChip = CIRRUS;
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WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0006); // lock Cirrus extensions
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}
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}
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}
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switch (HalpVideoChip) {
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case S3: HalpResetS3Chip();
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break;
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case CIRRUS: HalpResetCirrusChip();
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break;
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case VGA_STORM:
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HalpResetMatroxStorm();
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break;
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default: ;
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}
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HalpInitializeVGADisplay(TEXT_80x50);
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//
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// Initialize the current display column, row, and ownership values.
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//
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HalpColumn = 0;
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HalpRow = 0;
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HalpDisplayOwnedByHal = TRUE;
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return;
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}
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VOID
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HalQueryDisplayParameters (
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OUT PULONG WidthInCharacters,
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OUT PULONG HeightInLines,
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OUT PULONG CursorColumn,
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OUT PULONG CursorRow
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)
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/*++
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Routine Description:
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This routine return information about the display area and current
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cursor position.
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Arguments:
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WidthInCharacter - Supplies a pointer to a varible that receives
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the width of the display area in characters.
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HeightInLines - Supplies a pointer to a variable that receives the
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height of the display area in lines.
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CursorColumn - Supplies a pointer to a variable that receives the
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current display column position.
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CursorRow - Supplies a pointer to a variable that receives the
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current display row position.
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Return Value:
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None.
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--*/
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{
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//
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// Set the display parameter values and return.
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//
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*WidthInCharacters = HalpDisplayWidth;
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*HeightInLines = HalpDisplayText;
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*CursorColumn = HalpColumn;
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*CursorRow = HalpRow;
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return;
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}
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|
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VOID
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|
HalSetDisplayParameters (
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IN ULONG CursorColumn,
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IN ULONG CursorRow
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)
|
|
|
|
/*++
|
|
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|
Routine Description:
|
|
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|
This routine set the current cursor position on the display area.
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|
Arguments:
|
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|
CursorColumn - Supplies the new display column position.
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CursorRow - Supplies a the new display row position.
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Return Value:
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None.
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|
--*/
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{
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//
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|
// Set the display parameter values and return.
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//
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if (CursorColumn > HalpDisplayWidth) {
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CursorColumn = HalpDisplayWidth;
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}
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if (CursorRow > HalpDisplayText) {
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CursorRow = HalpDisplayText;
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}
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HalpColumn = CursorColumn;
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HalpRow = CursorRow;
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return;
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}
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|
|
VOID
|
|
HalDisplayString (
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PUCHAR String
|
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)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine displays a character string on the display screen.
|
|
|
|
Arguments:
|
|
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|
String - Supplies a pointer to the characters that are to be displayed.
|
|
|
|
Return Value:
|
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None.
|
|
|
|
--*/
|
|
|
|
{
|
|
KIRQL OldIrql;
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|
|
KeRaiseIrql(HIGH_LEVEL, &OldIrql);
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|
|
if(HalpIsMulti) KiAcquireSpinLock(&HalpDisplayAdapterLock);
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|
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//
|
|
// If ownership of the display has been switched to the system display
|
|
// driver, then reinitialize the display controller and revert ownership
|
|
// to the HAL.
|
|
//
|
|
|
|
if (HalpDisplayOwnedByHal == FALSE) {
|
|
|
|
if (((HalpVideoBoard == VIDEO_BOARD_UNKNOWN) || (HalpVideoBoard == VGA_GENERIC)) && (HalpReturnToVga != NULL)) {
|
|
(HalpReturnToVga)(80,25);
|
|
}
|
|
HalpDisplayControllerSetup();
|
|
|
|
}
|
|
|
|
// display the string
|
|
|
|
// if( HalpVideoChip == VIDEO_CHIP_UNKNOWN) {
|
|
// ((SNI_PRIVATE_VECTOR *)(SYSTEM_BLOCK->VendorVector))->printf(String);
|
|
// } else {
|
|
HalpDisplayVGAString(String);
|
|
// }
|
|
|
|
if(HalpIsMulti) KiReleaseSpinLock(&HalpDisplayAdapterLock);
|
|
|
|
KeLowerIrql(OldIrql);
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
VOID
|
|
HalpDisplayVGAString (
|
|
PUCHAR String
|
|
)
|
|
{
|
|
while (*String) {
|
|
switch (*String) {
|
|
case '\n':
|
|
HalpNextVGALine();
|
|
break;
|
|
case '\r':
|
|
HalpColumn = 0;
|
|
break;
|
|
default:
|
|
HalpPutVGACharacter(*String);
|
|
if (++HalpColumn == HalpDisplayWidth) {
|
|
HalpNextVGALine();
|
|
}
|
|
}
|
|
++String;
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
VOID
|
|
HalpNextVGALine(
|
|
VOID
|
|
)
|
|
{
|
|
if (HalpRow==HalpDisplayText-1) {
|
|
HalpScrollVGADisplay();
|
|
} else {
|
|
++HalpRow;
|
|
}
|
|
HalpColumn = 0;
|
|
}
|
|
|
|
VOID
|
|
HalpScrollVGADisplay(
|
|
VOID
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Scrolls the text on the display up one line.
|
|
|
|
Arguments:
|
|
|
|
None
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
|
|
{
|
|
PUSHORT NewStart;
|
|
ULONG i;
|
|
|
|
|
|
NewStart = VideoBuffer+HalpDisplayWidth;
|
|
MegaMoveMemory((PVOID)VideoBuffer, (PVOID)NewStart, (HalpDisplayText-1)*HalpDisplayWidth*sizeof(USHORT));
|
|
|
|
for (i=(HalpDisplayText-1)*HalpDisplayWidth; i<HalpDisplayText*HalpDisplayWidth; i++) {
|
|
VideoBuffer[i] = (REVERSE_ATTRIBUTE << 8) | ' ';
|
|
}
|
|
}
|
|
|
|
VOID
|
|
HalpPutVGACharacter(
|
|
UCHAR Character
|
|
)
|
|
{
|
|
PUSHORT cp = (PUSHORT)VideoBuffer;
|
|
int x = HalpColumn;
|
|
int y = HalpRow;
|
|
|
|
cp[y*HalpDisplayWidth + x] = (USHORT)((REVERSE_ATTRIBUTE << 8) | (Character ));
|
|
}
|
|
|
|
|
|
VOID
|
|
HalpClearVGADisplay(
|
|
VOID
|
|
)
|
|
{
|
|
ULONG i;
|
|
PUSHORT cp = (PUSHORT)VideoBuffer;
|
|
USHORT Attribute = (REVERSE_ATTRIBUTE << 8) | ' ';
|
|
|
|
for(i=0; i < HalpDisplayText*HalpDisplayWidth; i++) {
|
|
VideoBuffer[i] = Attribute;
|
|
}
|
|
|
|
HalpColumn=0;
|
|
HalpColumn=0;
|
|
}
|
|
|
|
|
|
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
HARDWARE specific Part of Display routines
|
|
|
|
this part of this file deals with special Hardware parts of some
|
|
graphic adapters (RamDac, Clock Generator, VGA Chipsets etc.
|
|
|
|
-------------------------------------------------------------------*/
|
|
|
|
VOID
|
|
DownLoadVGAFont(
|
|
VOID
|
|
)
|
|
/*+++
|
|
|
|
The Space occupied for 1 caracter in the charackter generator memory of an VGA
|
|
is 0x20 bytes, The font itself uses only 8 bytes, so we skip over the difference
|
|
|
|
---*/
|
|
{
|
|
|
|
PUCHAR dst = (PUCHAR)FontBuffer;
|
|
PUCHAR src = (PUCHAR)font_8x8;
|
|
long i, count = 256;
|
|
|
|
INIT_VGA_FONT();
|
|
|
|
while(count--){
|
|
for (i=0; i<8; i++)
|
|
*dst++ = *src++;
|
|
dst += 0x18;
|
|
}
|
|
EXIT_VGA_FONT() ;
|
|
}
|
|
|
|
VOID
|
|
HalpInitializeVGADisplay(
|
|
TEXT_MODE TextMode
|
|
)
|
|
{
|
|
|
|
static UCHAR _80x50_crt_regs [MAX_CRT] = { // 80x50 text mode
|
|
0x5f, 0x4f, 0x50, 0x82, 0x55, // cr0 - cr4
|
|
0x81, 0xBF, 0x1f, 0x0, 0x47, // cr9 - 7 lines per char
|
|
0x20, 0x00, 0x00, 0x00, 0x00, // cra - cursor off
|
|
0x00, 0x9c, 0x8e, 0x8f, 0x28,
|
|
0x1f, 0x96, 0xb9, 0xa3, 0xff
|
|
};
|
|
|
|
static UCHAR _132x50_crt_regs [MAX_CRT] = { // 132x50 text mode
|
|
0xa0, 0x83, 0x84, 0x83, 0x8a, // cr0 - cr4
|
|
0x9e, 0xBF, 0x1f, 0x0, 0x47, // cr9 - 7 lines per char
|
|
0x20, 0x00, 0x00, 0x00, 0x00,
|
|
0x00, 0x9c, 0x85, 0x8f, 0x42,
|
|
0x1f, 0x95, 0xa5, 0xa3, 0xff
|
|
};
|
|
|
|
static UCHAR default_graph_regs[GRAPH_MAX] =
|
|
{
|
|
0x00, 0x00, 0x00, 0x00, 0x00,
|
|
0x10, 0x0e, 0x00, 0xff
|
|
};
|
|
|
|
static UCHAR default_pal_regs[MAX_PALETTE] = {
|
|
0x00, 0x01, 0x02, 0x03, 0x04,
|
|
0x05, 0x14, 0x7, 0x38, 0x39,
|
|
0x3A, 0x3B, 0x3C, 0x3d, 0x3e,
|
|
0x3f, 0x08, 0x00, 0x0f, 0x00,
|
|
0x00
|
|
};
|
|
|
|
int i;
|
|
UCHAR byte;
|
|
|
|
//
|
|
// Matrox modification : (cf I/O space mapping p 3.9 of MGA STORM specification)
|
|
// PCI convention states that i/o space should only be accessed in bytes)
|
|
//
|
|
|
|
//
|
|
// VGA_MISC : 25.xxx MHZ frequency -> 640 horizontal pixels (val = 63)
|
|
// VGA_MISC : 28.xxx MHZ frequency -> 720 horizontal pixels (val = 67)
|
|
//
|
|
|
|
if (HalpVideoChip == VGA_STORM) WRITE_REGISTER_UCHAR(VGA_MISC_WRITE, 0x67) ; // else little frame
|
|
|
|
// reset ATC FlipFlop
|
|
byte = READ_REGISTER_UCHAR(VGA_ATC_FF);
|
|
WRITE_REGISTER_UCHAR(VGA_ATC_DATA, 0); // Disable palette
|
|
|
|
// stop the sequencer
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0100);
|
|
|
|
if (HalpVideoChip != VGA_STORM) {
|
|
if (TextMode == TEXT_132x50) {
|
|
// external clock (40MHz)
|
|
WRITE_REGISTER_UCHAR(VGA_MISC_WRITE, 0xAF);
|
|
} else {
|
|
// COLOR registers , enable RAM, 25 MHz 400 Lines,
|
|
WRITE_REGISTER_UCHAR(VGA_MISC_WRITE, 0x63) ;
|
|
}
|
|
}
|
|
|
|
// Select the timing sequencer values
|
|
// 8 dot/char
|
|
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0101);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0302);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0003);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0204);
|
|
|
|
// start the sequencer
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0300);
|
|
|
|
// Unprotect CRT regs and program them
|
|
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX , 0x0011);
|
|
|
|
for(i=0; i<MAX_CRT; i++) {
|
|
WRITE_REGISTER_UCHAR(VGA_CRT_IDX, i);
|
|
if (TextMode == TEXT_132x50){
|
|
WRITE_REGISTER_UCHAR(VGA_CRT_DATA, _132x50_crt_regs[i]);
|
|
} else {
|
|
WRITE_REGISTER_UCHAR(VGA_CRT_DATA, _80x50_crt_regs[i]);
|
|
}
|
|
}
|
|
|
|
DownLoadVGAFont();
|
|
|
|
HalpDisplayWidth = (TextMode == TEXT_132x50) ? 132 : 80;
|
|
HalpDisplayText = 50;
|
|
|
|
HalpClearVGADisplay();
|
|
|
|
i = READ_REGISTER_UCHAR(VGA_ATC_FF); // Reset attr FF
|
|
|
|
if (!HalpFirstBoot) {
|
|
|
|
//
|
|
// if this is not the First Boot
|
|
// i.e. an Bugcheck; we have to setup
|
|
// the Attribute and colors of the VGA PART
|
|
//
|
|
|
|
for(i=0; i<GRAPH_MAX; i++) {
|
|
WRITE_REGISTER_UCHAR(VGA_GRAPH_IDX , i);
|
|
WRITE_REGISTER_UCHAR(VGA_GRAPH_DATA, default_graph_regs[i]);
|
|
}
|
|
|
|
for(i=0; i<MAX_PALETTE; i++) { // PALETTE (ATC)
|
|
WRITE_REGISTER_UCHAR(VGA_ATC_IDX , i);
|
|
WRITE_REGISTER_UCHAR(VGA_ATC_DATA, default_pal_regs[i]);
|
|
}
|
|
|
|
|
|
}
|
|
|
|
WRITE_REGISTER_UCHAR(VGA_DAC_MASK , 0xff);
|
|
|
|
//
|
|
// set the 16 base colors for text mode in the DAC
|
|
//
|
|
|
|
WRITE_REGISTER_UCHAR(VGA_DAC_WRITE_INDEX, 0x00);
|
|
for(i=0; i<48; i++) {
|
|
WRITE_REGISTER_UCHAR(VGA_DAC_DATA, base_colors[i]);
|
|
}
|
|
|
|
WRITE_REGISTER_UCHAR(VGA_ATC_IDX, 0x20);
|
|
|
|
WRITE_REGISTER_UCHAR(VGA_SEQ_IDX, 0x01); // Screen on
|
|
byte = READ_REGISTER_UCHAR(VGA_SEQ_DATA);
|
|
WRITE_REGISTER_UCHAR(VGA_SEQ_DATA, (byte & 0xdf)); // in the sequencer
|
|
}
|
|
|
|
VOID
|
|
HalpMgaWaitLock(
|
|
UCHAR clock,
|
|
UCHAR p
|
|
)
|
|
{
|
|
UCHAR tmpByte;
|
|
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_INDEX,STORM_TVP3026_PLL_ADDR);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_DATA,0xea);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_INDEX,clock);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_DATA,(p & 0x7f));
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_INDEX,STORM_TVP3026_PLL_ADDR);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_DATA,0xea);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_INDEX,clock);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_DATA,p );
|
|
KeStallExecutionProcessor(10);
|
|
|
|
tmpByte = 0;
|
|
while (!(tmpByte & 0x40)) {
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_INDEX,clock);
|
|
tmpByte = READ_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_DATA);
|
|
KeStallExecutionProcessor(10);
|
|
}
|
|
|
|
}
|
|
|
|
|
|
VOID
|
|
HalpResetMatroxStorm(
|
|
VOID
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine initializes the VGA part of an Matrox storm card
|
|
|
|
Arguments:
|
|
|
|
None.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
{
|
|
USHORT buffer[8];
|
|
UCHAR tmpByte;
|
|
|
|
if (!HalpMgaStormBase) {
|
|
for(HalpMatroxBus=0;HalpMatroxBus<32;++HalpMatroxBus) {
|
|
|
|
for(HalpMatroxSlot=0;HalpMatroxSlot<32;++HalpMatroxSlot) {
|
|
|
|
HalpReadPCIConfig(HalpMatroxBus,HalpMatroxSlot,&buffer,0,14);
|
|
|
|
if ((buffer[0] == 0x102b) && (buffer[1] == 0x0519) && (buffer[5] == 0x0300)) {
|
|
HalpReadPCIConfig(HalpMatroxBus,HalpMatroxSlot,&HalpMgaStormBase,0x10,4);
|
|
break;
|
|
|
|
}
|
|
}
|
|
if (HalpMgaStormBase) break;
|
|
}
|
|
}
|
|
if ( HalpMgaStormBase == (ULONG)0) return;
|
|
|
|
// tranlated address
|
|
HalpMgaStormBase |= 0xa0000000;
|
|
|
|
/*** wait for the drawing engine to be idle ***/
|
|
tmpByte = 0;
|
|
while (tmpByte & 0x01) tmpByte = READ_REGISTER_UCHAR(HalpMgaStormBase + STORM_OFFSET + STORM_STATUS + 2);
|
|
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_OFFSET + STORM_MISC_W, 0x67);
|
|
|
|
if (HalpFirstBoot) {
|
|
HalpReadPCIConfig(HalpMatroxBus,HalpMatroxSlot,&Halpval40,STORM_PCI_OPTION,4);
|
|
} else {
|
|
// interleave bit is reset - gclk not divided - VGA io locations decoded
|
|
HalpSetPCIData(HalpMatroxBus,HalpMatroxSlot,(PUCHAR)(&Halpval40),STORM_PCI_OPTION,4);
|
|
}
|
|
|
|
if (!HalpFirstBoot) {
|
|
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_OFFSET +STORM_MISC_W, 0x2f);
|
|
|
|
/*** first : reset (especially for cursor...) ***/
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_INDEX,STORM_TVP3026_PLL_RESET);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_DATA,0);
|
|
|
|
/*** like fw -> pgm clocks (50Mhz) ***/
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_OFFSET +STORM_MISC_W, 0x2f); // to pgm PLL
|
|
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_INDEX,STORM_TVP3026_PLL_ADDR);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_DATA,0);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_INDEX,STORM_TVP3026_PIX_CLK_DATA);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_DATA,0xfd);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_INDEX,STORM_TVP3026_PIX_CLK_DATA);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_DATA,0x3a);
|
|
HalpMgaWaitLock(STORM_TVP3026_PIX_CLK_DATA,0xb2);
|
|
|
|
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_INDEX,STORM_TVP3026_MCLK_CTL);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_DATA,0x0);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_INDEX,STORM_TVP3026_MCLK_CTL);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_DATA,0x8);
|
|
|
|
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_INDEX,STORM_TVP3026_PLL_ADDR);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_DATA,0);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_INDEX,STORM_TVP3026_MEM_CLK_DATA);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_DATA,0xfd);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_INDEX,STORM_TVP3026_MEM_CLK_DATA);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_DATA,0x3a);
|
|
HalpMgaWaitLock(STORM_TVP3026_MEM_CLK_DATA,0xb2);
|
|
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_INDEX,STORM_TVP3026_MCLK_CTL);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_DATA,0x10);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_INDEX,STORM_TVP3026_MCLK_CTL);
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_RAMDAC_OFFSET + STORM_TVP3026_DATA,0x18);
|
|
|
|
WRITE_REGISTER_UCHAR (HalpMgaStormBase + STORM_OFFSET + STORM_MISC_W, 0x67); // VGA clock 25.xxxMhz
|
|
|
|
WRITE_REGISTER_UCHAR(VGA_CRTCEXT_IDX , VGA_CRTCEXT0);
|
|
WRITE_REGISTER_UCHAR(VGA_CRTCEXT_DATA, 0);
|
|
WRITE_REGISTER_UCHAR(VGA_CRTCEXT_IDX , VGA_CRTCEXT1);
|
|
WRITE_REGISTER_UCHAR(VGA_CRTCEXT_DATA, 0);
|
|
WRITE_REGISTER_UCHAR(VGA_CRTCEXT_IDX , VGA_CRTCEXT2);
|
|
WRITE_REGISTER_UCHAR(VGA_CRTCEXT_DATA, 0);
|
|
WRITE_REGISTER_UCHAR(VGA_CRTCEXT_IDX , VGA_CRTCEXT3);
|
|
WRITE_REGISTER_UCHAR(VGA_CRTCEXT_DATA, 0);
|
|
WRITE_REGISTER_UCHAR(VGA_CRTCEXT_IDX , VGA_CRTCEXT4);
|
|
WRITE_REGISTER_UCHAR(VGA_CRTCEXT_DATA, 0);
|
|
WRITE_REGISTER_UCHAR(VGA_CRTCEXT_IDX , VGA_CRTCEXT5);
|
|
WRITE_REGISTER_UCHAR(VGA_CRTCEXT_DATA, 0);
|
|
}
|
|
|
|
}
|
|
|
|
|
|
VOID
|
|
HalpResetS3Chip(
|
|
VOID
|
|
)
|
|
/*+++
|
|
|
|
This function resets/loads default values to the S3 Chip
|
|
extended registers
|
|
|
|
this code is borrowed/derived from the s3 miniport driver
|
|
|
|
---*/
|
|
{
|
|
UCHAR byte;
|
|
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x4838); // unlock the S3 regs
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xa539); // Unlock the SC regs
|
|
|
|
WRITE_REGISTER_UCHAR(VGA_SEQ_IDX, 0x01); // Screen off
|
|
byte = READ_REGISTER_UCHAR(VGA_SEQ_DATA);
|
|
WRITE_REGISTER_UCHAR(VGA_SEQ_DATA, (byte | 0x20)); // stop the sequencer
|
|
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0140); // Enable the enhanced 8514 registers
|
|
WRITE_REGISTER_USHORT(S3_ADVFUNC_CNTL, 0x02); // reset to normal VGA operation
|
|
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0032); // Backward Compat 3
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0035); // CRTC Lock
|
|
|
|
WRITE_REGISTER_UCHAR(VGA_SEQ_IDX, 0x00); // async reset
|
|
WRITE_REGISTER_UCHAR(VGA_SEQ_DATA, 0x01); //
|
|
|
|
WRITE_REGISTER_UCHAR(VGA_FEAT_CNTRL, 0x00); // normal sync
|
|
WRITE_REGISTER_UCHAR(VGA_MISC_READ, 0x00); //
|
|
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x8531);
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x2033); // Backward Compat 2
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0034); // Backward Compat 3
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x853a); // S3 Misc 1
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x5a3b); // Data Transfer Exec Pos
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x103c); // Interlace Retrace start
|
|
|
|
WRITE_REGISTER_UCHAR(VGA_SEQ_IDX, 0x00); // start the sequencer
|
|
WRITE_REGISTER_UCHAR(VGA_SEQ_DATA, 0x03); //
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xa640); // VLB: 3Wait
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x1841);
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0050);
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0051);
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xff52);
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0053);
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x3854);
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0055);
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0056);
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0057);
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x8058); // ISA Latch ? (bit 3)
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x005c);
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x005d);
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x005e);
|
|
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0760);
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x8061);
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xa162);
|
|
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0043); // Extended Mode
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0045); // HW graphics Cursor Mode
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0046); // HW graphics Cursor Orig x
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xff47); // HW graphics Cursor Orig x
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xfc48); // HW graphics Cursor Orig y
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xff49); // HW graphics Cursor Orig y
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xff4a); // HW graphics Cursor Orig y
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xff4b); // HW graphics Cursor Orig y
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xff4c); // HW graphics Cursor Orig y
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xff4d); // HW graphics Cursor Orig y
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xff4e); // Dsp Start x pixel pos
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xdf4f); // Dsp Start y pixel pos
|
|
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0042); // select default clock
|
|
|
|
WRITE_REGISTER_UCHAR(VGA_MISC_WRITE, 0x63); // Clock select
|
|
/*
|
|
// this should be done in the InitializeVGA code ...
|
|
|
|
WRITE_REGISTER_UCHAR(VGA_SEQ_IDX, 0x01); // Screen on
|
|
byte = READ_REGISTER_UCHAR(VGA_SEQ_DATA);
|
|
WRITE_REGISTER_UCHAR(VGA_SEQ_DATA, (byte & 0xdf)); // in the sequencer
|
|
*/
|
|
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0038); // lock s3 regs
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0039); // lock more s3 regs
|
|
|
|
}
|
|
|
|
VOID
|
|
HalpResetCirrusChip(
|
|
VOID
|
|
)
|
|
/*+++
|
|
|
|
This function resets/loads default values to the Cirrus Chip
|
|
extended registers for use with extended text mode (80x50)
|
|
|
|
Register values found in the cirrus manual, appendix D5
|
|
|
|
---*/
|
|
{
|
|
UCHAR byte;
|
|
|
|
WRITE_REGISTER_UCHAR(VGA_SEQ_IDX, 0x01); // Screen off
|
|
byte = READ_REGISTER_UCHAR(VGA_SEQ_DATA);
|
|
WRITE_REGISTER_UCHAR(VGA_SEQ_DATA, (byte | 0x20)); // stop the sequencer
|
|
|
|
// extended sequencer and crtc regs for cirrus
|
|
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x1206); // unlock the extended registers
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0007);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x4008);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x5709);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x180a);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x660b);
|
|
|
|
// new modifs
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x3b1b);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x000f);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0016);
|
|
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x001b);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0007);
|
|
WRITE_REGISTER_USHORT(VGA_GRAPH_IDX, 0x0009);
|
|
WRITE_REGISTER_USHORT(VGA_GRAPH_IDX, 0x000a);
|
|
WRITE_REGISTER_USHORT(VGA_GRAPH_IDX, 0x000b);
|
|
// end new modifs
|
|
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0010);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0011);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0012);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0013);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0018);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0119);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x001a);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x3b1b);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x2f1c);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x301d);
|
|
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x331e);
|
|
|
|
}
|