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338 lines
6.8 KiB
338 lines
6.8 KiB
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/*++
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Copyright (c) 1990 Microsoft Corporation
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Copyright (c) 1994 MOTOROLA, INC. All Rights Reserved. This file
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contains copyrighted material. Use of this file is restricted
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by the provisions of a Motorola Software License Agreement.
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Copyright (c) 1994, 1995 International Buisness Machines Corporation.
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Module Name:
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pxmemctl.c
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Abstract:
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The module initializes any planar registers.
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This module also implements machince check parity error handling.
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Author:
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Jim Wooldridge ([email protected])
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Revision History:
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Chris Karamatas ([email protected]) - added HalpHandleMemoryError
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--*/
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#include "halp.h"
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#include <pxmemctl.h>
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#include "pxidaho.h"
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#include "pci.h"
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#include "pcip.h"
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BOOLEAN
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HalpInitPlanar (
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VOID
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)
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{
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//
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// Enable Dynamic Power Management on 603 and 603+.
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//
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HalpSetDpm();
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return TRUE;
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}
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BOOLEAN
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HalpMapPlanarSpace (
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VOID
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)
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/*++
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Routine Description:
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This routine maps the interrupt acknowledge and error address
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spaces for a PowerPC system.
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Arguments:
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None.
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Return Value:
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If the initialization is successfully completed, than a value of TRUE
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is returned. Otherwise, a value of FALSE is returned.
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--*/
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{
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PHYSICAL_ADDRESS physicalAddress;
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//
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// Map interrupt control space.
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//
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physicalAddress.HighPart = 0;
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physicalAddress.LowPart = INTERRUPT_PHYSICAL_BASE;
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HalpInterruptBase = MmMapIoSpace(physicalAddress,
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PAGE_SIZE,
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FALSE);
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return TRUE;
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}
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BOOLEAN
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HalpMapBusConfigSpace (
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VOID
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)
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/*++
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Routine Description:
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This routine maps the HAL PCI config
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spaces for a PowerPC system.
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Arguments:
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None.
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Return Value:
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If the initialization is successfully completed, than a value of TRUE
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is returned. Otherwise, a value of FALSE is returned.
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--*/
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{
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HalpPciConfigBase = (PVOID) IO_CONTROL_PHYSICAL_BASE;
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return TRUE;
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}
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BOOLEAN
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HalpPhase0MapBusConfigSpace (
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VOID
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)
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/*++
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Routine Description:
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This routine maps the HAL PCI config
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spaces for a PowerPC system.
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Arguments:
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None.
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Return Value:
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If the initialization is successfully completed, than a value of TRUE
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is returned. Otherwise, a value of FALSE is returned.
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--*/
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{
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HalpPciConfigBase = (PVOID) IO_CONTROL_PHYSICAL_BASE;
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if (HalpIoControlBase == NULL) {
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HalpIoControlBase = (PUCHAR)KePhase0MapIo(IO_CONTROL_PHYSICAL_BASE, 0x400000);
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}
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if (HalpIoControlBase == NULL)
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return FALSE;
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else
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return TRUE;
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}
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VOID
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HalpPhase0UnMapBusConfigSpace (
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VOID
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)
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/*++
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Routine Description:
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This routine maps the HAL PCI config
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spaces for a PowerPC system.
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Arguments:
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None.
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Return Value:
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If the initialization is successfully completed, than a value of TRUE
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is returned. Otherwise, a value of FALSE is returned.
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--*/
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{
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}
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VOID
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HalpDisplayRegister(
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PUCHAR RegHex,
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int Bytes
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)
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/*++
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Routine Description:
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Displays (via HalDisplayString) a new-line terminated
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string of hex digits representing the input value. The
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input value is pointed to by the first argument is
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from 1 to 4 bytes in length.
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Arguments:
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RegHex Pointer to the value to be displayed.
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Bytes Length of input value in bytes (1-4).
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Return Value:
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None.
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--*/
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{
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#define DISP_MAX 4
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UCHAR RegString[(DISP_MAX * 2) + 2];
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UCHAR Num, High, Low;
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PUCHAR Byte = &RegString[(DISP_MAX * 2) + 1];
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*Byte = '\0';
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*--Byte = '\n';
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if ( (unsigned)Bytes > DISP_MAX ) {
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Bytes = DISP_MAX;
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}
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while (Bytes--) {
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Num = *RegHex++;
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High = (Num >> 4) + '0';
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Low = (Num & 0xf) + '0';
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if ( High > '9' ) {
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High += ('A' - '0' - 0xA);
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}
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if ( Low > '9' ) {
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Low += ('A' - '0' - 0xA);
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}
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*--Byte = Low;
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*--Byte = High;
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}
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HalDisplayString(Byte);
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}
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VOID
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HalpHandleMemoryError(
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VOID
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)
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{
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int byte;
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IDAHO_CONFIG PCI_Config_Space;
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UCHAR BusAddress[4];
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//
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// REM Make sure Options Reg.1 (0xBA) and Enable Detection Reg. (0xC0) are programed
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// Reset Error Det Reg when done ?
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HalGetBusData(PCIConfiguration, 0, 0, &PCI_Config_Space, sizeof(IDAHO_CONFIG));
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// Dump Error Detection Reg, Bus Address, Status Error,
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HalDisplayString ("TEA/MCP: System Error.\n");
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HalDisplayString ("Error Detection Register 1: ");
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HalpDisplayRegister (&PCI_Config_Space.ErrorDetection1,1);
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//
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// The error may have been detected during xfers on: cpu (local), memory, or pci bus
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//
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// Idaho will NOT generate/check Local Bus Parity
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if (PCI_Config_Space.ErrorDetection1 & 0x03) { // idaho <-> 603 :Local bus Cycle
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HalDisplayString ("Unsupported Local Bus Cycle\n");
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for (byte = 0; byte < 4; byte++) // Correct endianess if address is local
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BusAddress[byte] = PCI_Config_Space.ErrorAddress[3-byte];
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HalDisplayString ("Local Bus Error Address: ");
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HalpDisplayRegister(BusAddress,4);
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HalDisplayString ("CPU Bus Error Status - TT(0:4);TSIZ(0:2): ");
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HalpDisplayRegister(&PCI_Config_Space.CpuBusErrorStatus,1);
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// if (ErrorDetection & 0x01 {
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// HalDisplayString ("Unsupported Transfer Attributes\n");
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// }
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// if (ErrorDetection & 0x02 {
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// HalDisplay ("Extended Transfer Detected\n");
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// }
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}
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else if (PCI_Config_Space.ErrorDetection1 & 0x08) { // PCI Cycle
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HalDisplayString ("PCI Cycle\n");
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for (byte=0; byte<4; byte++)
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BusAddress[byte] = PCI_Config_Space.ErrorAddress[byte];
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HalDisplayString ("PCI Bus Address: ");
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HalpDisplayRegister(BusAddress,4);
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HalDisplayString ("PCI Bus Error Status: ");
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HalpDisplayRegister(&PCI_Config_Space.PciBusErrorStatus,1);
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// if PCI_Config_Space.PciBusErrorStatus & 0x10
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// HalDisplayString("Memory Controller was Slave on PCI Bus\n");
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// else
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// HalDisplayString("Memory Controller was Master on PCI Bus\n");
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HalDisplayString ("PCI Device Status Register D(15:8): ");
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HalpDisplayRegister(&PCI_Config_Space.DeviceStatus[1],1);
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// if PCI_Config_Space.DeviceStatus[1] & 0x81
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// HalDisplayString("Local Bus Agent Read Cycle\n");
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// if ErrorDetection & 0x80 // Local Bus Agent Write Cycle
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// HalDisplayString ("PCI System Error\n");
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// if ErrorDetection & 0x40 // Local Bus Agent Write\Read Address
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// HalDisplayString ("PCI Parity Error\n ");// Parity Error
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// Read PCI status Reg
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// if ErrorDetection & 0x20
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// HalDisplayString ("No Such Address in Physical Memory\n");
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}
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// if ErrorDetection & 0x10
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// HalDisplayString ("Refresh Timeout\n");
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}
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