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556 lines
18 KiB
556 lines
18 KiB
;/*
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;++
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;
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; Copyright (c) 1992 Intel Corporation
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; All rights reserved
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;
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; INTEL CORPORATION PROPRIETARY INFORMATION
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;
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; This software is supplied to Microsoft under the terms
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; of a license agreement with Intel Corporation and may not be
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; copied nor disclosed except in accordance with the terms
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; of that agreement.
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;
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;
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; Module Name:
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;
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; apic.inc
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;
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; Abstract:
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;
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; This module contains the definitions used by HAL to manipulate
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; APIC interrupt controller and APIC-specific constants.
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;
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; WARNING: This file is included by both ASM and C files.
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;
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; Author:
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;
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; Hugh Bynum and Ron Mosgrove Aug-1992
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;
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;--
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if 0 ; Begin C only code */
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//
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// APIC defines for C code
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// BE SURE TO CHANGE THESE VALUES IN BOTH TABLES!
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//
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#define IO_BASE_ADDRESS 0xFEC00000 // Physical address
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#define IO_REGISTER_SELECT 0x00000000 // offset from IO_BASE_ADDRESS
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#define IO_REGISTER_WINDOW 0x00000010 // offset from IO_BASE_ADDRESS
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#define IO_UNIT_0 0x00000000 // adder for IO unit 0
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#define IO_UNIT_1 0x00001000 // adder for IO unit 1
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#define IO_UNIT_2 0x00002000 // adder for IO unit 2
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#define IO_UNIT_3 0x00003000 // adder for IO unit 3
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#define IO_ID_REGISTER 0x00000000
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#define IO_VERS_REGISTER 0x00000001
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#define IO_ARB_ID_REGISTER 0x00000002
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#define IO_REDIR_00_LOW 0x00000010
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#define IO_REDIR_00_HIGH 0x00000011
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#define IO_MAX_REDIR_MASK 0x00FF0000
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#define IO_VERSION_MASK 0x000000FF
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#define LU_BASE_ADDRESS 0xFEE00000 // Physical address
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#define LU_ID_REGISTER 0x00000020 // offset from LU_BASE_ADDRESS
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#define LU_VERS_REGISTER 0x00000030 // offset from LU_BASE_ADDRESS
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#define LU_TPR 0x00000080 // offset from LU_BASE_ADDRESS
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#define LU_APR 0x00000090 // offset from LU_BASE_ADDRESS
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#define LU_PPR 0x000000A0 // offset from LU_BASE_ADDRESS
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#define LU_EOI 0x000000B0 // offset from LU_BASE_ADDRESS
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#define LU_REMOTE_REGISTER 0x000000C0 // offset from LU_BASE_ADDRESS
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#define LU_LOGICAL_DEST 0x000000D0 // offset from LU_BASE_ADDRESS
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#define LU_LOGICAL_DEST_MASK 0xFF000000
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#define LU_DEST_FORMAT 0x000000E0 // offset from LU_BASE_ADDRESS
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#define LU_DEST_FORMAT_MASK 0xF0000000
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#define LU_DEST_FORMAT_FLAT 0xFFFFFFFF
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#define LU_SPURIOUS_VECTOR 0x000000F0 // offset from LU_BASE_ADDRESS
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#define LU_UNIT_ENABLED 0x00000100
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#define LU_ISR_0 0x00000100 // offset from LU_BASE_ADDRESS
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#define LU_TMR_0 0x00000180 // offset from LU_BASE_ADDRESS
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#define LU_IRR_0 0x00000200 // offset from LU_BASE_ADDRESS
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#define LU_ERROR_STATUS 0x00000280 // offset from LU_BASE_ADDRESS
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#define LU_INT_CMD_LOW 0x00000300 // offset from LU_BASE_ADDRESS
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#define LU_INT_CMD_HIGH 0x00000310 // offset from LU_BASE_ADDRESS
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#define LU_TIMER_VECTOR 0x00000320 // offset from LU_BASE_ADDRESS
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#define LU_INT_VECTOR_0 0x00000350 // TEMPORARY - do not use
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#define LU_INT_VECTOR_1 0x00000360 // TEMPORARY - do not use
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#define LU_INITIAL_COUNT 0x00000380 // offset from LU_BASE_ADDRESS
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#define LU_CURRENT_COUNT 0x00000390 // offset from LU_BASE_ADDRESS
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#define LU_DIVIDER_CONFIG 0x000003E0 // offset from LU_BASE_ADDRESS
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#define APIC_ID_MASK 0x0F000000
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#define APIC_ID_SHIFT 24
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#define INT_VECTOR_MASK 0x000000FF
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#define RESERVED_HIGH_INT 0x000000F8
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#define DELIVERY_MODE_MASK 0x00000700
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#define DELIVER_FIXED 0x00000000
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#define DELIVER_LOW_PRIORITY 0x00000100
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#define DELIVER_SMI 0x00000200
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#define DELIVER_REMOTE_READ 0x00000300
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#define DELIVER_NMI 0x00000400
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#define DELIVER_INIT 0x00000500
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#define DELIVER_EXTINT 0x00000700
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#define LOGICAL_DESTINATION 0x00000800
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#define DELIVERY_PENDING 0x00001000
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#define ACTIVE_LOW 0x00002000
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#define REMOTE_IRR 0x00004000
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#define LEVEL_TRIGGERED 0x00008000
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#define INTERRUPT_MASKED 0x00010000
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#define PERIODIC_TIMER 0x00020000
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#define ICR_LEVEL_ASSERTED 0x00004000
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#define ICR_RR_STATUS_MASK 0x00030000
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#define ICR_RR_INVALID 0x00000000
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#define ICR_RR_IN_PROGRESS 0x00010000
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#define ICR_RR_VALID 0x00020000
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#define ICR_SHORTHAND_MASK 0x000C0000
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#define ICR_USE_DEST_FIELD 0x00000000
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#define ICR_SELF 0x00040000
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#define ICR_ALL_INCL_SELF 0x00080000
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#define ICR_ALL_EXCL_SELF 0x000C0000
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#define DESTINATION_MASK 0xFF000000
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#define DESTINATION_SHIFT 24
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/*
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endif
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; APIC defines for assembly code
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; BE SURE TO CHANGE THESE VALUES IN BOTH TABLES!
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;
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IO_BASE_ADDRESS equ 0FEC00000H ; Physical address
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IO_REGISTER_SELECT equ 00000000H ; offset from IO_BASE_ADDRESS
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IO_REGISTER_WINDOW equ 00000010H ; offset from IO_BASE_ADDRESS
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IO_UNIT_0 equ 00000000H ; adder for IO unit 0
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IO_UNIT_1 equ 00001000H ; adder for IO unit 1
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IO_UNIT_2 equ 00002000H ; adder for IO unit 2
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IO_UNIT_3 equ 00003000H ; adder for IO unit 3
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IO_ID_REGISTER equ 00000000H ;
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IO_VERS_REGISTER equ 00000001H ;
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IO_ARB_ID_REGISTER equ 00000002H ;
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IO_REDIR_00_LOW equ 00000010H ;
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IO_REDIR_00_HIGH equ 00000011H ;
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IO_MAX_REDIR_MASK equ 00FF0000H ;
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IO_VERSION_MASK equ 000000FFH ;
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LU_BASE_ADDRESS equ 0FEE00000H ;
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LU_ID_REGISTER equ 00000020H ; offset from LU_BASE_ADDRESS
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LU_VERS_REGISTER equ 00000030H ; offset from LU_BASE_ADDRESS
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LU_TPR equ 00000080H ; offset from LU_BASE_ADDRESS
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LU_APR equ 00000090H ; offset from LU_BASE_ADDRESS
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LU_PPR equ 000000A0H ; offset from LU_BASE_ADDRESS
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LU_EOI equ 000000B0H ; offset from LU_BASE_ADDRESS
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LU_REMOTE_REGISTER equ 000000C0H ; offset from LU_BASE_ADDRESS
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LU_LOGICAL_DEST equ 000000D0H ; offset from LU_BASE_ADDRESS
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LU_LOGICAL_DEST_MASK equ 0FF000000H ;
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LU_DEST_FORMAT equ 000000E0H ; offset from LU_BASE_ADDRESS
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LU_DEST_FORMAT_MASK equ 0F0000000H ;
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LU_DEST_FORMAT_FLAT equ 0FFFFFFFFH ;
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LU_SPURIOUS_VECTOR equ 000000F0H ; offset from LU_BASE_ADDRESS
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LU_UNIT_ENABLED equ 00000100H ;
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LU_ISR_0 equ 00000100H ; offset from LU_BASE_ADDRESS
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LU_TMR_0 equ 00000180H ; offset from LU_BASE_ADDRESS
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LU_IRR_0 equ 00000200H ; offset from LU_BASE_ADDRESS
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LU_ERROR_STATUS equ 00000280H ; offset from LU_BASE_ADDRESS
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LU_INT_CMD_LOW equ 00000300H ; offset from LU_BASE_ADDRESS
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LU_INT_CMD_HIGH equ 00000310H ; offset from LU_BASE_ADDRESS
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LU_TIMER_VECTOR equ 00000320H ; offset from LU_BASE_ADDRESS
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LU_INT_VECTOR_0 equ 00000350H ; TEMPORARY - do not use
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LU_INT_VECTOR_1 equ 00000360H ; TEMPORARY - do not use
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LU_INITIAL_COUNT equ 00000380H ; offset from LU_BASE_ADDRESS
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LU_CURRENT_COUNT equ 00000390H ; offset from LU_BASE_ADDRESS
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LU_DIVIDER_CONFIG equ 000003E0H ; offset from LU_BASE_ADDRESS
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LU_DIVIDE_BY_1 equ 0000000BH ;
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LU_DIVIDE_BY_2 equ 00000000H ;
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LU_DIVIDE_BY_4 equ 00000001H ;
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LU_DIVIDE_BY_8 equ 00000002H ;
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LU_DIVIDE_BY_16 equ 00000003H ;
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LU_DIVIDE_BY_32 equ 00000008H ;
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LU_DIVIDE_BY_64 equ 00000009H ;
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LU_DIVIDE_BY_128 equ 0000000AH ;
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APIC_ID_MASK equ 0F000000H ;
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APIC_ID_SHIFT equ 24 ;
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INT_VECTOR_MASK equ 000000FFH ;
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RESERVED_HIGH_INT equ 000000F8H ;
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DELIVERY_MODE_MASK equ 00000700H ;
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DELIVER_FIXED equ 00000000H ;
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DELIVER_LOW_PRIORITY equ 00000100H ;
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DELIVER_SMI equ 00000200H ;
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DELIVER_REMOTE_READ equ 00000300H ;
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DELIVER_NMI equ 00000400H ;
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DELIVER_INIT equ 00000500H ;
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DELIVER_EXTINT equ 00000700H ;
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PHYSICAL_DESTINATION equ 00000000H ;
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LOGICAL_DESTINATION equ 00000800H ;
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DELIVERY_PENDING equ 00001000H ;
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ACTIVE_LOW equ 00002000H ;
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REMOTE_IRR equ 00004000H ;
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LEVEL_TRIGGERED equ 00008000H ;
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INTERRUPT_MASKED equ 00010000H ;
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INTERRUPT_MOT_MASKED equ 00000000H ;
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PERIODIC_TIMER equ 00020000H ;
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ICR_LEVEL_ASSERTED equ 00004000H ;
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ICR_RR_STATUS_MASK equ 00030000H ;
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ICR_RR_INVALID equ 00000000H ;
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ICR_RR_IN_PROGRESS equ 00010000H ;
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ICR_RR_VALID equ 00020000H ;
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ICR_SHORTHAND_MASK equ 000C0000H ;
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ICR_USE_DEST_FIELD equ 00000000H ;
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ICR_SELF equ 00040000H ;
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ICR_ALL_INCL_SELF equ 00080000H ;
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ICR_ALL_EXCL_SELF equ 000C0000H ;
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DESTINATION_MASK equ 0FF000000H ;
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DESTINATION_SHIFT equ 24 ; shift count for dest. mask
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;
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; remaining macro definitions for assembler only
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;
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;++
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;
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; WRITE_IO_APIC
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;
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; Macro Description:
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;
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; This macro writes a value to a register in the I/O Apic.
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;
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; Arguments:
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;
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; Register - Register to be written
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;
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; Value - Value to write
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;
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;--
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WRITE_IO_APIC MACRO Register , Value
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.errb <Register>
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.errb <Value>
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; Need two scratch registers
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push eax ; Save registers
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push ecx
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push Value ; Save paramters on the stack
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push Register
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pop eax ; Get the Register
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mov ecx, _HalpIOunitBase
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add ecx, IO_REGISTER_SELECT+IO_UNIT_0 ; Register select on I/O Unit
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mov dword ptr [ecx], eax ; Program register
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pop eax ; Get the Value
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mov ecx, _HalpIOunitBase
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add ecx, IO_REGISTER_WINDOW+IO_UNIT_0 ; Register select on I/O Unit
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mov dword ptr [ecx], eax ; Program register
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pop ecx ; Restore scratch registers
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pop eax
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; We're Out'a Here
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endm
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;++
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;
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; READ_IO_APIC
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;
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; Macro Description:
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;
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; This macro reads a 32 bit register from the I/O Apic.
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;
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; Arguments:
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;
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; Register - Register to be read
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;
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; Return
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;
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; eax - value read from I/O Apic
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;
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;--
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READ_IO_APIC MACRO Register
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.errb <Register>
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ifndef _HalpIOunitBase
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extrn _HalpIOunitBase:DWORD
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endif
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push ecx ; Need one scratch register
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push Register
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pop eax ; Get the Register
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mov ecx, _HalpIOunitBase
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add ecx, IO_REGISTER_SELECT+IO_UNIT_0 ; Register select on I/O Unit
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mov dword ptr [ecx], eax ; Program register
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mov ecx, _HalpIOunitBase
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add ecx, IO_REGISTER_WINDOW+IO_UNIT_0 ; Register Window on I/O Unit
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mov eax, dword ptr [ecx] ; Program register
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pop ecx ; Restore scratch register
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; We're Out'a Here
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endm
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;++
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;
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; GetIOApicRedirTable
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;
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; Macro Description:
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;
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; This reads a redirection table entry from the I/O APIC (unit 0).
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;
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; Arguments:
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;
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; IoApicInputPin - Interrupt Input (INTI) we're interested in
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; The Caller MUST have locked access to the IO Apic prior to
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; this call.
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;
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; Return
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;
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; 64 Bit redirection table entry in eax [31:0] and edx [63:32]
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;
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;--
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GetIOApicRedirTable MACRO IoApicInputPin
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.errb <IoApicInputPin>
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push IoApicInputPin ; Save paramter on the stack
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pop eax ; INTI we're looking for
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and eax, 0fh ; Make sure we're dealing with
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; defined inputs
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shl eax, 1 ; <IoApicInputPin> * 2
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add eax, IO_REDIR_00_LOW+IO_UNIT_0 ; eax == low(redir) of INTI
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push eax ; Save the register address
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inc eax ; Points to high(redir)
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READ_IO_APIC eax ; Read the Upper 32 Bits of the Redir
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mov edx, eax ; Save the High 32 Bits to return
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pop eax ; Get the low register address
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READ_IO_APIC eax ; Read the Lower 32 Bits of the Redir
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;
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; edx == bits 32-63 of RedirectionTable[IoApicInputPin]
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; eax == bits 00-31 of RedirectionTable[IoApicInputPin]
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;
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endm
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;++
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;
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; PutIOApicRedirTable
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;
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; Macro Description:
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;
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; This writes a redirection table entry to the I/O APIC (unit 0)..
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; The Caller MUST have locked access to the IO Apic prior to
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; this call.
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;
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; Arguments:
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;
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; IoApicInputPin - Interrupt Input (INTI) we're interested in
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;
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; LowWord - Low 32 Bits of redirection Table entry
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;
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; HighWord - High 32 Bits of redirection Table entry
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;
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;
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;--
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PutIOApicRedirTable MACRO IoApicInputPin , LowWord , HighWord
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.errb <IoApicInputPin>
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.errb <LowWord>
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.errb <HighWord>
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push LowWord ; Save paramter on the stack
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push HighWord
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push IoApicInputPin
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pop eax ; INTI we're looking for
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and eax, 0fh ; Make sure we're dealing with
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; defined inputs
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shl eax, 1 ; <IoApicInputPin> * 2
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add eax, IO_REDIR_00_LOW+IO_UNIT_0 ; eax == low(redir) of INTI
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pop edx ; edx <= Bits 31-63 of redir
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push eax ; Save the register address
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inc eax ; Points to high(redir)
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WRITE_IO_APIC eax , edx ; Write the Upper 32 Bits of the Redir
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pop eax ; Get the low register address
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pop edx ; edx <= Bits 00-31 of redir
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WRITE_IO_APIC eax , edx ; Write the Lower 32 Bits of the Redir
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endm
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;++
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;
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; GrabHalIoApicSpinLock
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;
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; Macro Description:
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;
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; This macro is used to prevent multiple CPU's from accessing the IO APIC on a MP
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; system. It grabs the IoAPIC Spin lock if available, ifnot then it waits until
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; it is available.
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;
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; The compliment of this macro is ReleaseHalIoApicSpinLock.
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;
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;--
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GrabHalIoApicSpinLock MACRO
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local WaitForRelease, StartSpinLockLoop, Gotit
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ifndef _HalpIOunitLock
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extrn _HalpIOunitLock:DWORD ; IoUnit SpinLock
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endif ; _HalpIOunitLock
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StartSpinLockLoop:
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pushfd ; Save Flags
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cli ; Don't Interrupt us here
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lea eax, _HalpIOunitLock ; The SpinLock we're interested in
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ACQUIRE_SPINLOCK eax, WaitForRelease ; Try for the lock, if Not successful
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; Go and wait till the owner frees it.
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;
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; We now own the spinlock
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;
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jmp Gotit
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WaitForRelease:
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sti ; Allow other activity while we wait
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SPIN_ON_SPINLOCK eax, StartSpinLockLoop ; Stare at it until it's free
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;
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; We'll Never get here
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;
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Gotit:
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popfd ; restore Original Flags
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endm
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;++
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;
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; ReleaseHalIoApicSpinLock
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;
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; Macro Description:
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;
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; This macro is used to prevent multiple CPU's from accessing the IO Apic on a MP
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; system. It frees the IoApic Spin lock.
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;
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; The compliment of this macro is GrabHalIoApicSpinLock.
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;--
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ReleaseHalIoApicSpinLock MACRO
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ifndef _HalpIOunitLock
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extrn _HalpIOunitLock:DWORD ; IoUnit SpinLock
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endif ; _HalpIOunitLock
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lea eax, _HalpIOunitLock
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RELEASE_SPINLOCK eax
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endm
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;++
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;
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; GrabHal8259SpinLock
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;
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; Macro Description:
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;
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; This macro is used to prevent multiple CPU's from accessing the IO APIC on a MP
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; system. It grabs the 8259 Spin lock if available, ifnot then it waits until
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; it is available.
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;
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; The compliment of this macro is ReleaseHal8259SpinLock.
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;
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;--
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GrabHal8259SpinLock MACRO
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local WaitForRelease, StartSpinLockLoop, Gotit
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ifndef _Halp8259Lock
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extrn _Halp8259Lock:DWORD ; 8259 SpinLock
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endif ; _Halp8259Lock
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StartSpinLockLoop:
|
|
|
|
pushfd ; Save Flags
|
|
cli ; Don't Interrupt us here
|
|
|
|
lea eax, _Halp8259Lock ; The SpinLock we're interested in
|
|
ACQUIRE_SPINLOCK eax, WaitForRelease ; Try for the lock, if Not successful
|
|
; Go and wait till the owner frees it.
|
|
|
|
;
|
|
; We now own the spinlock
|
|
;
|
|
|
|
jmp Gotit
|
|
|
|
WaitForRelease:
|
|
sti ; Allow other activity while we wait
|
|
SPIN_ON_SPINLOCK eax, StartSpinLockLoop ; Stare at it until it's free
|
|
|
|
;
|
|
; We'll Never get here
|
|
;
|
|
|
|
Gotit:
|
|
|
|
popfd ; restore Original Flags
|
|
|
|
endm
|
|
|
|
;++
|
|
;
|
|
; ReleaseHal8259SpinLock
|
|
;
|
|
; Macro Description:
|
|
;
|
|
; This macro is used to prevent multiple CPU's from accessing the IO Apic on a MP
|
|
; system. It frees the 8259 Spin lock.
|
|
;
|
|
; The compliment of this macro is GrabHal8259SpinLock.
|
|
;--
|
|
ReleaseHal8259SpinLock MACRO
|
|
|
|
ifndef _Halp8259Lock
|
|
extrn _Halp8259Lock:DWORD ; 8259 SpinLock
|
|
endif ; _Halp8259Lock
|
|
|
|
lea eax, _Halp8259Lock
|
|
RELEASE_SPINLOCK eax
|
|
|
|
endm
|
|
;*/
|