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841 lines
27 KiB
841 lines
27 KiB
/*++
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Copyright (c) 1992 Microsoft Corporation
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Module Name:
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cirrus.h
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Abstract:
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This module contains the definitions for the code that implements the
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Cirrus Logic VGA 6410/6420/542x device driver.
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Environment:
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Kernel mode
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Revision History:
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--*/
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#if !defined _PPC_
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#if !defined _MIPS_
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#define INT10_MODE_SET
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#endif
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#endif
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//
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// Do full save and restore.
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//
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#define EXTENDED_REGISTER_SAVE_RESTORE 1
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//
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// Banking ifdefs to enable banking
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// the banking type MUST match the type in clhard.asm
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//
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#define ONE_64K_BANK 0
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#define TWO_32K_BANKS 1
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#define MULTIPLE_REFRESH_TABLES 0
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//
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// Treat CL-GD5434_6 (rev 0xHH) as CL-GD5434 if requested.
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//
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#define CL5434_6_SPECIAL_REQUEST 0
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//---------------------------------------------------------------------------
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//
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// only one banking variable must be defined
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//
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#if TWO_32K_BANKS
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#if ONE_64K_BANK
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#error !!ERROR: two types of banking defined!
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#endif
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#elif ONE_64K_BANK
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#else
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#error !!ERROR: banking type must be defined!
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#endif
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//
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// Base address of VGA memory range. Also used as base address of VGA
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// memory when loading a font, which is done with the VGA mapped at A0000.
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//
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#define MEM_VGA 0xA0000
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#define MEM_VGA_SIZE 0x20000
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#define MEM_LINEAR 0x0
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#define MEM_LINEAR_SIZE 0x0
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// #ifdef _ALPHA_
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//
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// #define PHY_AD_20_23 0x060 // Value for SR7 to map video memory
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// #define PHY_VGA 0x0600000 // put it at 6 megabytes for Alpha (for now)
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// #define PHY_VGA_SIZE 0x0100000 // allocate a megabyte of space there
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//
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// #endif
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//
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#ifdef _PPC_
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//
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// For PPC SandleFoot, may work on blackhawk and commet too.
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//
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#undef MEM_LINEAR
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#undef MEM_LINEAR_SIZE
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#define LA_MASK 0x1
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#define MEM_LINEAR (LA_MASK << 24)
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#define MEM_LINEAR_SIZE 0x100000
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#endif
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#ifdef _MIPS_
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//
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// For MIPS NEC machine only
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//
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#undef MEM_LINEAR
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#undef MEM_LINEAR_SIZE
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#define LA_MASK 0xE
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#define MEM_LINEAR (LA_MASK << 20)
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#define MEM_LINEAR_SIZE 0x100000
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#define MEM_SNI_LINEAR_SIZE 0x200000
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#endif
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//
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// For Siemens Nixdorf Mips box
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//
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#define RM200_ONBOARD_ISA_IO_PHYS 0x16000000
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#define RM200_ONBOARD_VIDEO_MEM_PHYS 0x1E000000
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//
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// For memory mapped IO
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//
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#define MEMORY_MAPPED_IO_OFFSET (0xB8000 - 0xA0000)
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//
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// Port definitions for filling the ACCESS_RANGES structure in the miniport
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// information, defines the range of I/O ports the VGA spans.
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// There is a break in the IO ports - a few ports are used for the parallel
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// port. Those cannot be defined in the ACCESS_RANGE, but are still mapped
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// so all VGA ports are in one address range.
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//
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#define VGA_BASE_IO_PORT 0x000003B0
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#define VGA_START_BREAK_PORT 0x000003BB
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#define VGA_END_BREAK_PORT 0x000003C0
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#define VGA_MAX_IO_PORT 0x000003DF
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//
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// VGA register definitions
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//
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#define CRTC_ADDRESS_PORT_MONO 0x03B4 // CRT Controller Address and
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#define CRTC_DATA_PORT_MONO 0x03B5 // Data registers in mono mode
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#define FEAT_CTRL_WRITE_PORT_MONO 0x03BA // Feature Control write port
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// in mono mode
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#define INPUT_STATUS_1_MONO 0x03BA // Input Status 1 register read
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// port in mono mode
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#define ATT_INITIALIZE_PORT_MONO INPUT_STATUS_1_MONO
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// Register to read to reset
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// Attribute Controller index/data
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#define ATT_ADDRESS_PORT 0x03C0 // Attribute Controller Address and
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#define ATT_DATA_WRITE_PORT 0x03C0 // Data registers share one port
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// for writes, but only Address is
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// readable at 0x010
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#define ATT_DATA_READ_PORT 0x03C1 // Attribute Controller Data reg is
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// readable here
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#define MISC_OUTPUT_REG_WRITE_PORT 0x03C2 // Miscellaneous Output reg write
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// port
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#define INPUT_STATUS_0_PORT 0x03C2 // Input Status 0 register read
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// port
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#define VIDEO_SUBSYSTEM_ENABLE_PORT 0x03C3 // Bit 0 enables/disables the
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// entire VGA subsystem
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#define SEQ_ADDRESS_PORT 0x03C4 // Sequence Controller Address and
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#define SEQ_DATA_PORT 0x03C5 // Data registers
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#define DAC_PIXEL_MASK_PORT 0x03C6 // DAC pixel mask reg
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#define DAC_ADDRESS_READ_PORT 0x03C7 // DAC register read index reg,
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// write-only
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#define DAC_STATE_PORT 0x03C7 // DAC state (read/write),
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// read-only
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#define DAC_ADDRESS_WRITE_PORT 0x03C8 // DAC register write index reg
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#define DAC_DATA_REG_PORT 0x03C9 // DAC data transfer reg
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#define FEAT_CTRL_READ_PORT 0x03CA // Feature Control read port
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#define MISC_OUTPUT_REG_READ_PORT 0x03CC // Miscellaneous Output reg read
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// port
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#define GRAPH_ADDRESS_PORT 0x03CE // Graphics Controller Address
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#define GRAPH_DATA_PORT 0x03CF // and Data registers
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// ports in color mode
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#define CRTC_ADDRESS_PORT_COLOR 0x03D4 // CRT Controller Address and
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#define CRTC_DATA_PORT_COLOR 0x03D5 // Data registers in color mode
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#define FEAT_CTRL_WRITE_PORT_COLOR 0x03DA // Feature Control write port
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#define INPUT_STATUS_1_COLOR 0x03DA // Input Status 1 register read
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// port in color mode
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#define ATT_INITIALIZE_PORT_COLOR INPUT_STATUS_1_COLOR
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// Register to read to reset
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// Attribute Controller index/data
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// toggle in color mode
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//
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// Offsets in HardwareStateHeader->PortValue[] of save areas for non-indexed
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// VGA registers.
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//
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#define CRTC_ADDRESS_MONO_OFFSET 0x04
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#define FEAT_CTRL_WRITE_MONO_OFFSET 0x0A
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#define ATT_ADDRESS_OFFSET 0x10
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#define MISC_OUTPUT_REG_WRITE_OFFSET 0x12
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#define VIDEO_SUBSYSTEM_ENABLE_OFFSET 0x13
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#define SEQ_ADDRESS_OFFSET 0x14
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#define DAC_PIXEL_MASK_OFFSET 0x16
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#define DAC_STATE_OFFSET 0x17
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#define DAC_ADDRESS_WRITE_OFFSET 0x18
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#define GRAPH_ADDRESS_OFFSET 0x1E
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#define CRTC_ADDRESS_COLOR_OFFSET 0x24
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#define FEAT_CTRL_WRITE_COLOR_OFFSET 0x2A
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// toggle in color mode
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//
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// VGA indexed register indexes.
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//
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// CL-GD542x specific registers:
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//
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#define IND_CL_EXTS_ENB 0x06 // index in Sequencer to enable exts
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#define IND_NORD_SCRATCH_PAD 0x09 // index in Seq of Nordic scratch pad
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#define IND_CL_SCRATCH_PAD 0x0A // index in Seq of 542x scratch pad
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#define IND_ALP_SCRATCH_PAD 0x15 // index in Seq of Alpine scratch pad
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#define IND_CL_REV_REG 0x25 // index in CRTC of ID Register
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#define IND_CL_ID_REG 0x27 // index in CRTC of ID Register
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//
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#define IND_CURSOR_START 0x0A // index in CRTC of the Cursor Start
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#define IND_CURSOR_END 0x0B // and End registers
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#define IND_CURSOR_HIGH_LOC 0x0E // index in CRTC of the Cursor Location
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#define IND_CURSOR_LOW_LOC 0x0F // High and Low Registers
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#define IND_VSYNC_END 0x11 // index in CRTC of the Vertical Sync
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// End register, which has the bit
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// that protects/unprotects CRTC
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// index registers 0-7
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#define IND_CR2C 0x2C // Nordic LCD Interface Register
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#define IND_CR2D 0x2D // Nordic LCD Display Control
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#define IND_SET_RESET_ENABLE 0x01 // index of Set/Reset Enable reg in GC
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#define IND_DATA_ROTATE 0x03 // index of Data Rotate reg in GC
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#define IND_READ_MAP 0x04 // index of Read Map reg in Graph Ctlr
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#define IND_GRAPH_MODE 0x05 // index of Mode reg in Graph Ctlr
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#define IND_GRAPH_MISC 0x06 // index of Misc reg in Graph Ctlr
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#define IND_BIT_MASK 0x08 // index of Bit Mask reg in Graph Ctlr
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#define IND_SYNC_RESET 0x00 // index of Sync Reset reg in Seq
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#define IND_MAP_MASK 0x02 // index of Map Mask in Sequencer
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#define IND_MEMORY_MODE 0x04 // index of Memory Mode reg in Seq
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#define IND_CRTC_PROTECT 0x11 // index of reg containing regs 0-7 in
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// CRTC
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#define IND_CRTC_COMPAT 0x34 // index of CRTC Compatibility reg
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// in CRTC
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#define IND_PERF_TUNING 0x16 // index of performance tuning in Seq
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#define START_SYNC_RESET_VALUE 0x01 // value for Sync Reset reg to start
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// synchronous reset
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#define END_SYNC_RESET_VALUE 0x03 // value for Sync Reset reg to end
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// synchronous reset
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//
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// Value to write to Extensions Control register values extensions.
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//
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#define CL64xx_EXTENSION_ENABLE_INDEX 0x0A // GR0A to be exact!
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#define CL64xx_EXTENSION_ENABLE_VALUE 0xEC
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#define CL64xx_EXTENSION_DISABLE_VALUE 0xCE
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#define CL64xx_TRISTATE_CONTROL_REG 0xA1
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#define CL6340_ENABLE_READBACK_REGISTER 0xE0
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#define CL6340_ENABLE_READBACK_ALLSEL_VALUE 0xF0
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#define CL6340_ENABLE_READBACK_OFF_VALUE 0x00
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#define CL6340_IDENTIFICATION_REGISTER 0xE9
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//
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// Values for Attribute Controller Index register to turn video off
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// and on, by setting bit 5 to 0 (off) or 1 (on).
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//
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#define VIDEO_DISABLE 0
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#define VIDEO_ENABLE 0x20
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#define INDEX_ENABLE_AUTO_START 0x31
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// Masks to keep only the significant bits of the Graphics Controller and
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// Sequencer Address registers. Masking is necessary because some VGAs, such
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// as S3-based ones, don't return unused bits set to 0, and some SVGAs use
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// these bits if extensions are enabled.
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//
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#define GRAPH_ADDR_MASK 0x0F
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#define SEQ_ADDR_MASK 0x07
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//
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// Mask used to toggle Chain4 bit in the Sequencer's Memory Mode register.
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//
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#define CHAIN4_MASK 0x08
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//
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// Value written to the Read Map register when identifying the existence of
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// a VGA in VgaInitialize. This value must be different from the final test
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// value written to the Bit Mask in that routine.
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//
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#define READ_MAP_TEST_SETTING 0x03
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//
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// Default text mode setting for various registers, used to restore their
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// states if VGA detection fails after they've been modified.
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//
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#define MEMORY_MODE_TEXT_DEFAULT 0x02
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#define BIT_MASK_DEFAULT 0xFF
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#define READ_MAP_DEFAULT 0x00
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//
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// Palette-related info.
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//
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//
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// Highest valid DAC color register index.
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//
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#define VIDEO_MAX_COLOR_REGISTER 0xFF
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//
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// Highest valid palette register index
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//
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#define VIDEO_MAX_PALETTE_REGISTER 0x0F
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//
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// Indices for type of memory mapping; used in ModesVGA[], must match
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// MemoryMap[].
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//
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typedef enum _VIDEO_MEMORY_MAP {
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MemMap_Mono,
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MemMap_CGA,
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MemMap_VGA
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} VIDEO_MEMORY_MAP, *PVIDEO_MEMORY_MAP;
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//
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// Memory map table definition
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//
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typedef struct {
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ULONG MaxSize; // Maximum addressable size of memory
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ULONG Offset; // Start address of display memory
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} MEMORYMAPS;
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//
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// For a mode, the type of banking supported. Controls the information
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// returned in VIDEO_BANK_SELECT. PlanarHCBanking includes NormalBanking.
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//
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typedef enum _BANK_TYPE {
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NoBanking = 0,
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NormalBanking,
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PlanarHCBanking
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} BANK_TYPE, *PBANK_TYPE;
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//
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// Define type of cirrus boards
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//
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typedef enum _BOARD_TYPE {
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SPEEDSTARPRO = 1,
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SIEMENS_ONBOARD_CIRRUS,
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NEC_ONBOARD_CIRRUS,
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OTHER
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} BOARD_TYPE;
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//
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// The chip ID is returned to the display driver in the
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// DriverSpecificAttributeFlags field during processing of
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// the IOCTL_VIDEO_QUERY_CURRENT_MODE.
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//
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#define CL6410 0x0001
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#define CL6420 0x0002
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#define CL542x 0x0004
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#define CL543x 0x0008
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#define CL5434 0x0010
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#define CL5434_6 0x0020
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#define CL5436 0x0100
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#define CL5446 0x0200
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#define CL54UM36 0x0400
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#define CL754x 0x1000
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#define CL755x 0x2000
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#define CL756x 0x4000
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//
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// Actual Revision IDs for certain cirrus chips
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//
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#define CL5429_ID 0x27
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#define CL5428_ID 0x26
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#define CL5430_ID 0x28
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#define CL5434_ID 0x2A
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#define CL5436_ID 0x2B
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#define CL5446_ID 0x2E
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//
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// Driver Specific Attribute Flags
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//
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#define CAPS_NO_HOST_XFER 0x00000002 // Do not use host xfers to
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// the blt engine.
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#define CAPS_SW_POINTER 0x00000004 // Use software pointer.
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#define CAPS_TRUE_COLOR 0x00000008 // Set upper color registers.
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#define CAPS_MM_IO 0x00000010 // Use memory mapped IO.
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#define CAPS_BLT_SUPPORT 0x00000020 // BLTs are supported
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#define CAPS_IS_542x 0x00000040 // This is a 542x
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#define CAPS_IS_5436 0x00000080 // This is a 5436
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#define CAPS_CURSOR_VERT_EXP 0x00000100 // Flag set if 8x6 panel,
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// but 6x4 resolution
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#define CAPS_DSTN_PANEL 0x00000200 // DSTN panel in use
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// bitfields for the DisplayType
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#define crt 0x0001
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#define panel 0x0002
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#define panel8x6 0x0004
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#define panel10x7 0x0008
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#define TFT_LCD 0x0100
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#define STN_LCD 0x0200
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#define Mono_LCD 0x0400
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#define Color_LCD 0x0800
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#define Single_LCD 0x1000
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#define Dual_LCD 0x2000
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//
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// Indexes into array of mode table pointers
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//
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#define pCL6410_crt 0
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#define pCL6410_panel 1
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#define pCL6420_crt 2
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#define pCL6420_panel 3
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#define pCL542x 4
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#define pCL543x 5
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#define pStretchScan 6
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#define pNEC_CL543x 7
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#define NUM_CHIPTYPES 8
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typedef struct {
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USHORT BiosModeCL6410; // bios modes are different across the
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USHORT BiosModeCL6420; // products. that's why we need multiple
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USHORT BiosModeCL542x; // values.
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} CLMODE, *PCLMODE;
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//
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// Structure used to describe each video mode in ModesVGA[].
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//
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typedef struct {
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USHORT fbType; // color or monochrome, text or graphics, via
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// VIDEO_MODE_COLOR and VIDEO_MODE_GRAPHICS
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USHORT numPlanes; // # of video memory planes
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USHORT bitsPerPlane; // # of bits of color in each plane
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SHORT col; // # of text columns across screen with default font
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SHORT row; // # of text rows down screen with default font
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USHORT hres; // # of pixels across screen
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USHORT vres; // # of scan lines down screen
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USHORT wbytes; // # of bytes from start of one scan line to start of next
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ULONG sbytes; // total size of addressable display memory in bytes
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ULONG Frequency; // Vertical Frequency
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ULONG Interlaced; // Determines if the mode is interlaced or not
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ULONG MonitorType; // Sets the desired vertical freq in an int10
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ULONG MonTypeAX; // Sets the desired horizontal freq in an int10
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ULONG MonTypeBX;
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ULONG MonTypeCX;
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BOOLEAN HWCursorEnable; // Flag to disable cursor if necessary
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BANK_TYPE banktype; // NoBanking, NormalBanking, PlanarHCBanking
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VIDEO_MEMORY_MAP MemMap; // index from VIDEO_MEMORY_MAP of memory
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// mapping used by this mode
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USHORT ChipType; // flags that say which chipset runs this mode
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USHORT DisplayType; // display type this mode runs on(crt or panel)
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BOOLEAN ValidMode; // TRUE if mode valid, FALSE if not
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BOOLEAN LinearSupport; // TRUE if this mode can have its memory
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// mapped in linearly.
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CLMODE BiosModes;
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//
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// the mode will be TRUE if there is enough video memory to support the
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// mode, and the display type(it could be a panel), will support the mode.
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// PANELS only support 640x480 for now.
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//
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PUSHORT CmdStrings[NUM_CHIPTYPES]; // pointer to array of register-setting commands to
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// set up mode
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} VIDEOMODE, *PVIDEOMODE;
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//
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// Mode into which to put the VGA before starting a VDM, so it's a plain
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// vanilla VGA. (This is the mode's index in ModesVGA[], currently standard
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// 80x25 text mode.)
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//
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#define DEFAULT_MODE 0
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//
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// Info used by the Validator functions and save/restore code.
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// Structure used to trap register accesses that must be done atomically.
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//
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#define VGA_MAX_VALIDATOR_DATA 100
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#define VGA_VALIDATOR_UCHAR_ACCESS 1
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#define VGA_VALIDATOR_USHORT_ACCESS 2
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#define VGA_VALIDATOR_ULONG_ACCESS 3
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typedef struct _VGA_VALIDATOR_DATA {
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ULONG Port;
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UCHAR AccessType;
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ULONG Data;
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} VGA_VALIDATOR_DATA, *PVGA_VALIDATOR_DATA;
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//
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// Number of bytes to save in each plane.
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//
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#define VGA_PLANE_SIZE 0x10000
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//
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// Number of each type of indexed register in a standard VGA, used by
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// validator and state save/restore functions.
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//
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// Note: VDMs currently only support basic VGAs only.
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//
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#define VGA_NUM_SEQUENCER_PORTS 5
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#define VGA_NUM_CRTC_PORTS 25
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#define VGA_NUM_GRAPH_CONT_PORTS 9
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#define VGA_NUM_ATTRIB_CONT_PORTS 21
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#define VGA_NUM_DAC_ENTRIES 256
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#ifdef EXTENDED_REGISTER_SAVE_RESTORE
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//
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// Indices to start save/restore in extension registers:
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// For both chip types
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#define CL64xx_GRAPH_EXT_START 0x0b // does not include ext. enable
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#define CL64xx_GRAPH_EXT_END 0xFF
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#define CL542x_GRAPH_EXT_START 0x09
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#define CL542x_GRAPH_EXT_END 0x39
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#define CL542x_SEQUENCER_EXT_START 0x07 // does not include ext. enable
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#define CL542x_SEQUENCER_EXT_END 0x1F
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#define CL542x_CRTC_EXT_START 0x19
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#define CL542x_CRTC_EXT_END 0x1B
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//
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// Number of extended regs for both chip types
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//
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#define CL64xx_NUM_GRAPH_EXT_PORTS (CL64xx_GRAPH_EXT_END - CL64xx_GRAPH_EXT_START + 1)
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#define CL542x_NUM_GRAPH_EXT_PORTS (CL542x_GRAPH_EXT_END - CL542x_GRAPH_EXT_START + 1)
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#define CL542x_NUM_SEQUENCER_EXT_PORTS (CL542x_SEQUENCER_EXT_END - CL542x_SEQUENCER_EXT_START + 1)
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#define CL542x_NUM_CRTC_EXT_PORTS (CL542x_CRTC_EXT_END - CL542x_CRTC_EXT_START + 1)
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//
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// set values for save/restore area based on largest value for a chipset.
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//
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#define EXT_NUM_GRAPH_CONT_PORTS ((CL64xx_NUM_GRAPH_EXT_PORTS > \
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CL542x_NUM_GRAPH_EXT_PORTS) ? \
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CL64xx_NUM_GRAPH_EXT_PORTS : \
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CL542x_NUM_GRAPH_EXT_PORTS)
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#define EXT_NUM_SEQUENCER_PORTS CL542x_NUM_SEQUENCER_EXT_PORTS
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#define EXT_NUM_CRTC_PORTS CL542x_NUM_CRTC_EXT_PORTS
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#define EXT_NUM_ATTRIB_CONT_PORTS 0
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#define EXT_NUM_DAC_ENTRIES 0
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#else
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#define EXT_NUM_GRAPH_CONT_PORTS 0
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#define EXT_NUM_SEQUENCER_PORTS 0
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#define EXT_NUM_CRTC_PORTS 0
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#define EXT_NUM_ATTRIB_CONT_PORTS 0
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#define EXT_NUM_DAC_ENTRIES 0
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#endif
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//
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// These constants determine the offsets within the
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// VIDEO_HARDWARE_STATE_HEADER structure that are used to save and
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// restore the VGA's state.
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//
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#define VGA_HARDWARE_STATE_SIZE sizeof(VIDEO_HARDWARE_STATE_HEADER)
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#define VGA_BASIC_SEQUENCER_OFFSET (VGA_HARDWARE_STATE_SIZE + 0)
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#define VGA_BASIC_CRTC_OFFSET (VGA_BASIC_SEQUENCER_OFFSET + \
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VGA_NUM_SEQUENCER_PORTS)
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#define VGA_BASIC_GRAPH_CONT_OFFSET (VGA_BASIC_CRTC_OFFSET + \
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VGA_NUM_CRTC_PORTS)
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#define VGA_BASIC_ATTRIB_CONT_OFFSET (VGA_BASIC_GRAPH_CONT_OFFSET + \
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VGA_NUM_GRAPH_CONT_PORTS)
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#define VGA_BASIC_DAC_OFFSET (VGA_BASIC_ATTRIB_CONT_OFFSET + \
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VGA_NUM_ATTRIB_CONT_PORTS)
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#define VGA_BASIC_LATCHES_OFFSET (VGA_BASIC_DAC_OFFSET + \
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(3 * VGA_NUM_DAC_ENTRIES))
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#define VGA_EXT_SEQUENCER_OFFSET (VGA_BASIC_LATCHES_OFFSET + 4)
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#define VGA_EXT_CRTC_OFFSET (VGA_EXT_SEQUENCER_OFFSET + \
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EXT_NUM_SEQUENCER_PORTS)
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#define VGA_EXT_GRAPH_CONT_OFFSET (VGA_EXT_CRTC_OFFSET + \
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EXT_NUM_CRTC_PORTS)
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#define VGA_EXT_ATTRIB_CONT_OFFSET (VGA_EXT_GRAPH_CONT_OFFSET +\
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EXT_NUM_GRAPH_CONT_PORTS)
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#define VGA_EXT_DAC_OFFSET (VGA_EXT_ATTRIB_CONT_OFFSET + \
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EXT_NUM_ATTRIB_CONT_PORTS)
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#define VGA_VALIDATOR_OFFSET (VGA_EXT_DAC_OFFSET + 4 * EXT_NUM_DAC_ENTRIES)
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#define VGA_VALIDATOR_AREA_SIZE sizeof (ULONG) + (VGA_MAX_VALIDATOR_DATA * \
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sizeof (VGA_VALIDATOR_DATA)) + \
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sizeof (ULONG) + \
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sizeof (ULONG) + \
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sizeof (PVIDEO_ACCESS_RANGE)
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#define VGA_MISC_DATA_AREA_OFFSET VGA_VALIDATOR_OFFSET + VGA_VALIDATOR_AREA_SIZE
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#define VGA_MISC_DATA_AREA_SIZE 0
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#define VGA_PLANE_0_OFFSET VGA_MISC_DATA_AREA_OFFSET + VGA_MISC_DATA_AREA_SIZE
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#define VGA_PLANE_1_OFFSET VGA_PLANE_0_OFFSET + VGA_PLANE_SIZE
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#define VGA_PLANE_2_OFFSET VGA_PLANE_1_OFFSET + VGA_PLANE_SIZE
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#define VGA_PLANE_3_OFFSET VGA_PLANE_2_OFFSET + VGA_PLANE_SIZE
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//
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// Space needed to store all state data.
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//
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#define VGA_TOTAL_STATE_SIZE VGA_PLANE_3_OFFSET + VGA_PLANE_SIZE
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//
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// Device extension for the driver object. This data is only used
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// locally, so this structure can be added to as needed.
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//
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typedef struct _HW_DEVICE_EXTENSION {
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PHYSICAL_ADDRESS PhysicalVideoMemoryBase; // physical memory address and
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PHYSICAL_ADDRESS PhysicalFrameOffset; // physical memory address and
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ULONG PhysicalVideoMemoryLength; // length of display memory
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ULONG PhysicalFrameLength; // length of display memory for
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// the current mode.
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PUCHAR IOAddress; // base I/O address of VGA ports
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PUCHAR VideoMemoryAddress; // base virtual memory address of VGA memory
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ULONG NumAvailableModes; // number of available modes this session
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ULONG ModeIndex; // index of current mode in ModesVGA[]
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PVIDEOMODE CurrentMode; // pointer to VIDEOMODE structure for
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// current mode
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USHORT FontPelColumns; // Width of the font in pels
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USHORT FontPelRows; // height of the font in pels
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USHORT cursor_vert_exp_flag;
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VIDEO_CURSOR_POSITION CursorPosition; // current cursor position
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UCHAR CursorEnable; // whether cursor is enabled or not
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UCHAR CursorTopScanLine; // Cursor Start register setting (top scan)
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UCHAR CursorBottomScanLine; // Cursor End register setting (bottom scan)
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// add HW cursor data here
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BOOLEAN VideoPointerEnabled; // Whether HW Cursor is supported
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USHORT ChipType; // CL6410, CL6420, CL542x, or CL543x
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USHORT ChipRevision; // chip revision value
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INTERFACE_TYPE BusType; // isa, pci, etc.
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USHORT DisplayType; // crt, panel or panel8x6
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USHORT BoardType; // Diamond, etc ...
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ULONG AdapterMemorySize; // amount of installed video ram
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BOOLEAN LinearMode; // TRUE if memory is mapped linear
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BOOLEAN BiosGT130; // Do we have a 1.30 or higher bios
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BOOLEAN BIOSPresent; // Indicates whether a bios is present
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BOOLEAN AutoFeature; // Autostart on 54x6
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//
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// The following two values are used to pass information to the
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// IO Callback called by IOWaitDisplEnableThenWrite.
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//
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ULONG DEPort; // stores the port address to write to
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UCHAR DEValue; // stores the value to write
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//
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// These 4 fields must be at the end of the device extension and must be
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// kept in this order since this data will be copied to and from the save
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// state buffer that is passed to and from the VDM.
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//
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ULONG TrappedValidatorCount; // number of entries in the Trapped
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// validator data Array.
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VGA_VALIDATOR_DATA TrappedValidatorData[VGA_MAX_VALIDATOR_DATA];
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// Data trapped by the validator routines
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// but not yet played back into the VGA
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// register.
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ULONG SequencerAddressValue; // Determines if the Sequencer Address Port
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// is currently selecting the SyncReset data
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// register.
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ULONG CurrentNumVdmAccessRanges; // Number of access ranges in
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// the access range array pointed
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// to by the next field
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PVIDEO_ACCESS_RANGE CurrentVdmAccessRange; // Access range currently
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// associated to the VDM
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} HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION;
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//
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// Function prototypes.
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//
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//
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// Entry points for the VGA validator. Used in VgaEmulatorAccessEntries[].
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//
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VP_STATUS
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VgaValidatorUcharEntry (
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ULONG Context,
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ULONG Port,
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UCHAR AccessMode,
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PUCHAR Data
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);
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VP_STATUS
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VgaValidatorUshortEntry (
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ULONG Context,
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ULONG Port,
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UCHAR AccessMode,
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PUSHORT Data
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);
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VP_STATUS
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VgaValidatorUlongEntry (
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ULONG Context,
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ULONG Port,
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UCHAR AccessMode,
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PULONG Data
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);
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BOOLEAN
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VgaPlaybackValidatorData (
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PVOID Context
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);
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#ifdef _X86_
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//
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// Bank switch code start and end labels, defined in CLHARD.ASM
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//
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// three versions for Cirrus Logic products
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//
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extern UCHAR CL64xxBankSwitchStart;
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extern UCHAR CL64xxBankSwitchEnd;
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extern UCHAR CL64xxPlanarHCBankSwitchStart;
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extern UCHAR CL64xxPlanarHCBankSwitchEnd;
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extern UCHAR CL64xxEnablePlanarHCStart;
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extern UCHAR CL64xxEnablePlanarHCEnd;
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extern UCHAR CL64xxDisablePlanarHCStart;
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extern UCHAR CL64xxDisablePlanarHCEnd;
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extern UCHAR CL542xBankSwitchStart;
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extern UCHAR CL542xBankSwitchEnd;
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extern UCHAR CL542xPlanarHCBankSwitchStart;
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extern UCHAR CL542xPlanarHCBankSwitchEnd;
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extern UCHAR CL542xEnablePlanarHCStart;
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extern UCHAR CL542xEnablePlanarHCEnd;
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extern UCHAR CL542xDisablePlanarHCStart;
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extern UCHAR CL542xDisablePlanarHCEnd;
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extern UCHAR CL543xBankSwitchStart;
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extern UCHAR CL543xBankSwitchEnd;
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extern UCHAR CL543xPlanarHCBankSwitchStart;
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extern UCHAR CL543xPlanarHCBankSwitchEnd;
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#endif
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//
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// Vga init scripts for font loading
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//
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extern USHORT EnableA000Data[];
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extern USHORT DisableA000Color[];
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//
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// Mode Information
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//
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extern MEMORYMAPS MemoryMaps[];
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extern ULONG NumVideoModes;
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extern VIDEOMODE ModesVGA[];
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#define NUM_VGA_ACCESS_RANGES 4
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extern VIDEO_ACCESS_RANGE VgaAccessRange[];
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#define VGA_NUM_EMULATOR_ACCESS_ENTRIES 6
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extern EMULATOR_ACCESS_ENTRY VgaEmulatorAccessEntries[];
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#define NUM_MINIMAL_VGA_VALIDATOR_ACCESS_RANGE 4
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extern VIDEO_ACCESS_RANGE MinimalVgaValidatorAccessRange[];
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#define NUM_FULL_VGA_VALIDATOR_ACCESS_RANGE 2
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extern VIDEO_ACCESS_RANGE FullVgaValidatorAccessRange[];
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//
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// sr754x (NORDIC) prototypes
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//
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VP_STATUS
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NordicSaveRegs(
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PHW_DEVICE_EXTENSION HwDeviceExtension,
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PUSHORT NordicSaveArea
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);
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VP_STATUS
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NordicRestoreRegs(
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PHW_DEVICE_EXTENSION HwDeviceExtension,
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PUSHORT NordicSaveArea
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);
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ULONG
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GetAttributeFlags(
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PHW_DEVICE_EXTENSION HwDeviceExtension
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);
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