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1178 lines
29 KiB
1178 lines
29 KiB
/*++
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Copyright (c) 1992 Microsoft Corporation
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Module Name:
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Mode542x.h
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Abstract:
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This module contains all the global data used by the Cirrus Logic
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CL-542x driver.
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Environment:
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Kernel mode
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Revision History:
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--*/
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//
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// The next set of tables are for the CL542x
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// Note: all resolutions supported
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//
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//
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// 640x480 16-color mode (BIOS mode 12) set command string for CL 542x.
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//
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USHORT CL542x_640x480_16[] = {
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OWM, // begin setmode
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SEQ_ADDRESS_PORT,
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2, // count
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0x1206, // enable extensions
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0x0012,
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OWM,
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GRAPH_ADDRESS_PORT,
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3,
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0x0009, 0x000a, 0x000b, // no banking in 640x480 mode
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EOD
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};
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//
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// 800x600 16-color (60Hz refresh) mode set command string for CL 542x.
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//
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USHORT CL542x_800x600_16[] = {
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OWM, // begin setmode
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SEQ_ADDRESS_PORT,
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2, // count
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0x1206, // enable extensions
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0x0012,
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OWM,
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GRAPH_ADDRESS_PORT,
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3,
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0x0009, 0x000a, 0x000b, // no banking in 800x600 mode
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EOD
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};
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//
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// 1024x768 16-color (60Hz refresh) mode set command string for CL 542x.
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//
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USHORT CL542x_1024x768_16[] = {
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OWM, // begin setmode
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SEQ_ADDRESS_PORT,
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2, // count
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0x1206, // enable extensions
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0x0012,
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OWM,
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GRAPH_ADDRESS_PORT,
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3,
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#if ONE_64K_BANK
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0x0009, 0x000a, 0x000b,
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#endif
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#if TWO_32K_BANKS
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0x0009, 0x000a, 0x010b,
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#endif
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OB,
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DAC_PIXEL_MASK_PORT,
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0xFF,
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EOD
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};
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//-----------------------------
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// standard VGA text modes here
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// 80x25 at 640x350
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//
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//-----------------------------
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//
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// 80x25 text mode set command string for CL 542x.
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// (720x400 pixel resolution; 9x16 character cell.)
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//
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USHORT CL542x_80x25Text[] = {
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OWM, // begin setmode
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SEQ_ADDRESS_PORT,
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2, // count
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0x1206, // enable extensions
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0x0012,
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OWM,
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GRAPH_ADDRESS_PORT,
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3,
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0x0009, 0x000a, 0x000b, // no banking in text mode
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EOD
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};
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//
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// 80x25 text mode set command string for CL 542x.
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// (640x350 pixel resolution; 8x14 character cell.)
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//
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USHORT CL542x_80x25_14_Text[] = {
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OWM, // begin setmode
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SEQ_ADDRESS_PORT,
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2, // count
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0x1206, // enable extensions
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0x0012,
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OWM,
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GRAPH_ADDRESS_PORT,
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3,
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0x0009, 0x000a, 0x000b, // no banking in text mode
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EOD
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};
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//
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// 1280x1024 16-color mode (BIOS mode 0x6C) set command string for CL 542x.
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//
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USHORT CL542x_1280x1024_16[] = {
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OWM, // begin setmode
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SEQ_ADDRESS_PORT,
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2, // count
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0x1206, // enable extensions
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0x0012,
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OWM,
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GRAPH_ADDRESS_PORT,
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3,
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#if ONE_64K_BANK
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0x0009, 0x000a, 0x000b,
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#endif
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#if TWO_32K_BANKS
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0x0009, 0x000a, 0x010b,
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#endif
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EOD
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};
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//
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// 640x480 64k-color mode (BIOS mode 0x64) set command string for CL 542x.
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//
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USHORT CL542x_640x480_64k[] = {
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OWM, // begin setmode
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SEQ_ADDRESS_PORT,
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2, // count
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0x1206, // enable extensions
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0x0012,
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OWM,
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GRAPH_ADDRESS_PORT,
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4,
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0x0506, // Some BIOS's set Chain Odd maps bit
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#if ONE_64K_BANK
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0x0009, 0x000a, 0x000b,
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#endif
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#if TWO_32K_BANKS
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0x0009, 0x000a, 0x010b,
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#endif
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EOD
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};
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#ifdef INT10_MODE_SET
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//
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// 640x480 256-color mode (BIOS mode 0x5F) set command string for CL 542x.
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//
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USHORT CL542x_640x480_256[] = {
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OWM, // begin setmode
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SEQ_ADDRESS_PORT,
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2, // count
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0x1206, // enable extensions
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0x0012,
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OWM,
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GRAPH_ADDRESS_PORT,
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3,
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#if ONE_64K_BANK
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0x0009, 0x000a, 0x000b,
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#endif
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#if TWO_32K_BANKS
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0x0009, 0x000a, 0x010b,
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#endif
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EOD
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};
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//
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// 800x600 256-color mode (BIOS mode 0x5C) set command string for CL 542x.
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//
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USHORT CL542x_800x600_256[] = {
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OWM, // begin setmode
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SEQ_ADDRESS_PORT,
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2, // count
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0x1206, // enable extensions
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0x0012,
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OWM,
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GRAPH_ADDRESS_PORT,
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3,
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#if ONE_64K_BANK
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0x0009, 0x000a, 0x000b,
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#endif
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#if TWO_32K_BANKS
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0x0009, 0x000a, 0x010b,
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#endif
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EOD
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};
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#else
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/*
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* L001 1993.10.15 Kuroki
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*
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* - Modify for R96 MIPS R4400
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*
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* Delete : Micro channel Bus Initialize.
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* VDM & Text, Fullscreen mode support.
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* Banking routine.
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* CL64xx Chip support.
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* 16-color mode.
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*
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* Add : Liner Addressing.
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*
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* M002 1993.10.28 fujimoto
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*
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* - Add 24bits/pixel mode command sequence.
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*
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*/
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//
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// The next set of tables are for the CL542x
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// Note: 256 resolutions supported
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//
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//
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// 640x480 256-color 60Hz mode (BIOS mode 0x5F) set command string for
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// CL 542x.
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//
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USHORT CL542x_640x480_256a60[] = {
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OWM, // begin setmode
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SEQ_ADDRESS_PORT,
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2, // count
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0x1206, // enable extensions
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0x0012,
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OWM, // begin setmode
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SEQ_ADDRESS_PORT,
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15, // count
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0x100, // start sync reset
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0x0101,0x0F02,0x0003,0x0E04, // program up sequencer
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//
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// the Miniport Driver for R96 machine is Liner addressing mode.
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// This set command was changed Liner addressing.
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//
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(LA_MASK << 12 | 0x0107),
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0x0008,
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0x4A0B,0x5B0C,0x450D,0x7E0E,
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0x2B1B,0x2F1C,0x301D,0x331E,
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OB, // point sequencer index to ff
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SEQ_ADDRESS_PORT,
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0x0F,
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METAOUT+MASKOUT, // masked out.
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SEQ_DATA_PORT,
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0xDF,0x20, // and mask, xor mask
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OB, // misc. register
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MISC_OUTPUT_REG_WRITE_PORT,
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0xE3,
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OW, // text/graphics bit
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GRAPH_ADDRESS_PORT,
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0x506,
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OW, // end sync reset
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SEQ_ADDRESS_PORT,
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0x300,
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OW, // unprotect crtc 0-7
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CRTC_ADDRESS_PORT_COLOR,
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0x2011,
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METAOUT+INDXOUT, // program crtc registers
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CRTC_ADDRESS_PORT_COLOR,
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28,0, // count, startindex
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0x5D, 0x4F, 0x50, 0x82, 0x53, 0x9F,
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0x00, 0x3E, 0x00, 0x40, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0xE1, 0x83,
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0xDF, 0x50, 0x00, 0xE7, 0x04, 0xE3,
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0xFF, 0x00, 0x00, 0x22,
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METAOUT+INDXOUT, // program gdc registers
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GRAPH_ADDRESS_PORT,
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9,0, // count, startindex
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0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
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0x05, 0x0F, 0xFF,
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IB, // prepare atc for writing
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INPUT_STATUS_1_COLOR,
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METAOUT+ATCOUT, // program atc registers
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ATT_ADDRESS_PORT,
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21,0, // count, startindex
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
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0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
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0x0C, 0x0D, 0x0E, 0x0F, 0x41, 0x00,
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0x0F, 0x00, 0x00,
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OB, // turn video on.
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ATT_ADDRESS_PORT,
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0x20,
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OB,
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DAC_PIXEL_MASK_PORT,
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0xFF,
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OWM,
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GRAPH_ADDRESS_PORT,
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3,
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//
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// The Miniport Driver for R96 machine is Liner addressing mode.
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// This set command was changed it for Liner addressing.
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//
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0x0009, 0x000a, 0x000b,
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EOD
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};
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//
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// 640x480 256-color mode (BIOS mode 0x5F) set command string for CL 542x.
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//
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USHORT CL542x_640x480_256a72[] = {
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OWM, // begin setmode
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SEQ_ADDRESS_PORT,
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2, // count
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0x1206, // enable extensions
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0x0012,
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OWM, // begin setmode
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SEQ_ADDRESS_PORT,
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15, // count
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0x100, // start sync reset
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0x0101,0x0F02,0x0003,0x0E04, // program up sequencer
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//
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// the Miniport Driver for R96 machine is Liner addressing mode.
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// This set command was changed Liner addressing.
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//
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(LA_MASK << 12 | 0x0107), /* L001 */
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0x0008,
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0x4A0B,0x5B0C,0x450D,0x420E,
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0x2B1B,0x2F1C,0x301D,0x1F1E,
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OB, // point sequencer index to ff
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SEQ_ADDRESS_PORT,
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0x0F,
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METAOUT+MASKOUT, // masked out.
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SEQ_DATA_PORT,
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0xDF,0x20, // and mask, xor mask
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OB, // misc. register
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MISC_OUTPUT_REG_WRITE_PORT,
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0xEF,
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OW, // text/graphics bit
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GRAPH_ADDRESS_PORT,
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0x506,
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OW, // end sync reset
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SEQ_ADDRESS_PORT,
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0x300,
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OW, // unprotect crtc 0-7
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CRTC_ADDRESS_PORT_COLOR,
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0x2011,
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METAOUT+INDXOUT, // program crtc registers
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CRTC_ADDRESS_PORT_COLOR,
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28,0,
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0x61, 0x4F, 0x50, 0x82, 0x54, 0x99,
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0xF6, 0x1F, 0x00, 0x40, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0xE0, 0x03,
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0xDF, 0x50, 0x00, 0xE7, 0x04, 0xE3,
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0xFF, 0x00, 0x00, 0x22,
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METAOUT+INDXOUT, // program gdc registers
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GRAPH_ADDRESS_PORT,
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9,0, // count, startindex
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0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
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0x05, 0x0F, 0xFF,
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IB, // prepare atc for writing
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INPUT_STATUS_1_COLOR,
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METAOUT+ATCOUT, // program atc registers
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ATT_ADDRESS_PORT,
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21,0, // count, startindex
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
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0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
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0x0C, 0x0D, 0x0E, 0x0F, 0x41, 0x00,
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0x0F, 0x00, 0x00,
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OB, // turn video on.
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ATT_ADDRESS_PORT,
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0x20,
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OB,
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DAC_PIXEL_MASK_PORT,
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0xFF,
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OWM,
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GRAPH_ADDRESS_PORT,
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3,
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//
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// The Miniport Driver for R96 machine is Liner addressing mode.
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// This set command was changed it for Liner addressing.
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//
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0x0009, 0x000a, 0x000b, /* L001 */
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EOD
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};
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//
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// 800x600 256-color 56Hz mode (BIOS mode 0x5C) set command string for
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// CL 542x.
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//
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USHORT CL542x_800x600_256a56[] = {
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OWM, // begin setmode
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SEQ_ADDRESS_PORT,
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2, // count
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0x1206, // enable extensions
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0x0012,
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|
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OWM, // begin setmode
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SEQ_ADDRESS_PORT,
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15, // count
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0x100, // start sync reset
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0x0101,0x0F02,0x0003,0x0E04, // program up sequencer
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//
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// The Miniport Driver for R96 machine is Liner addressing mode.
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// This set command was changed Liner addressing.
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//
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(LA_MASK << 12 | 0x0107),
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0x0008,
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0x4A0B,0x5B0C,0x450D,0x7E0E,
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0x2B1B,0x2F1C,0x301D,0x331E,
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OB, // point sequencer index to ff
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SEQ_ADDRESS_PORT,
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0x0F,
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METAOUT+MASKOUT, // masked out.
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SEQ_DATA_PORT,
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0xDF,0x20, // and mask, xor mask
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OB, // misc. register
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MISC_OUTPUT_REG_WRITE_PORT,
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0xEF,
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OW, // text/graphics bit
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GRAPH_ADDRESS_PORT,
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0x506,
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OW, // end sync reset
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SEQ_ADDRESS_PORT,
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0x300,
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OW, // unprotect crtc 0-7
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CRTC_ADDRESS_PORT_COLOR,
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0x2011,
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METAOUT+INDXOUT, // program crtc registers
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CRTC_ADDRESS_PORT_COLOR,
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28,0, // count, startindex
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0x7B, 0x63, 0x64, 0x80, 0x69, 0x12,
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0x6F, 0xF0, 0x00, 0x60, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x58, 0x8A,
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0x57, 0x64, 0x00, 0x5F, 0x91, 0xE3,
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0xFF, 0x00, 0x00, 0x22,
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METAOUT+INDXOUT, // program gdc registers
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GRAPH_ADDRESS_PORT,
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9,0, // count, startindex
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0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
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0x05, 0x0F, 0xFF,
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IB, // prepare atc for writing
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INPUT_STATUS_1_COLOR,
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METAOUT+ATCOUT, // program atc registers
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ATT_ADDRESS_PORT,
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21,0, // count, startindex
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
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0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
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0x0C, 0x0D, 0x0E, 0x0F, 0x41, 0x00,
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0x0F, 0x00, 0x00,
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OB, // turn video on.
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ATT_ADDRESS_PORT,
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0x20,
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OB,
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DAC_PIXEL_MASK_PORT,
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0xFF,
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OWM,
|
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GRAPH_ADDRESS_PORT,
|
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3,
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|
|
|
//
|
|
// The Miniport Driver for R96 machine is Liner addressing mode.
|
|
// This set command was changed it for Liner addressing.
|
|
//
|
|
|
|
0x0009, 0x000a, 0x000b,
|
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|
|
EOD
|
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};
|
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|
|
//
|
|
// 800x600 256-color 60Hz mode (BIOS mode 0x5C) set command string for
|
|
// CL 542x.
|
|
//
|
|
|
|
USHORT CL542x_800x600_256a60[] = {
|
|
OWM, // begin setmode
|
|
SEQ_ADDRESS_PORT,
|
|
2, // count
|
|
0x1206, // enable extensions
|
|
0x0012,
|
|
|
|
OWM, // begin setmode
|
|
SEQ_ADDRESS_PORT,
|
|
15, // count
|
|
0x100, // start sync reset
|
|
0x0101,0x0F02,0x0003,0x0E04, // program up sequencer
|
|
|
|
//
|
|
// The Miniport Driver for R96 machine is Liner addressing mode.
|
|
// This set command was changed Liner addressing.
|
|
//
|
|
|
|
(LA_MASK << 12 | 0x0107),
|
|
0x0008,
|
|
0x4A0B,0x5B0C,0x450D,0x510E,
|
|
0x2B1B,0x2F1C,0x301D,0x3A1E,
|
|
|
|
OB, // point sequencer index to ff
|
|
SEQ_ADDRESS_PORT,
|
|
0x0F,
|
|
|
|
METAOUT+MASKOUT, // masked out.
|
|
SEQ_DATA_PORT,
|
|
0xDF,0x20, // and mask, xor mask
|
|
|
|
OB, // misc. register
|
|
MISC_OUTPUT_REG_WRITE_PORT,
|
|
0xEF,
|
|
|
|
OW, // text/graphics bit
|
|
GRAPH_ADDRESS_PORT,
|
|
0x506,
|
|
|
|
OW, // end sync reset
|
|
SEQ_ADDRESS_PORT,
|
|
0x300,
|
|
|
|
OW, // unprotect crtc 0-7
|
|
CRTC_ADDRESS_PORT_COLOR,
|
|
0x2011,
|
|
|
|
METAOUT+INDXOUT, // program crtc registers
|
|
CRTC_ADDRESS_PORT_COLOR,
|
|
28,0, // count, startindex
|
|
|
|
0x7F, 0x63, 0x64, 0x80, 0x6B, 0x1B,
|
|
0x72, 0xF0, 0x00, 0x60, 0x00, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0x58, 0x8C,
|
|
0x57, 0x64, 0x00, 0x5F, 0x91, 0xE3,
|
|
0xFF, 0x00, 0x00, 0x22,
|
|
|
|
METAOUT+INDXOUT, // program gdc registers
|
|
GRAPH_ADDRESS_PORT,
|
|
9,0, // count, startindex
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
|
|
0x05, 0x0F, 0xFF,
|
|
|
|
IB, // prepare atc for writing
|
|
INPUT_STATUS_1_COLOR,
|
|
|
|
METAOUT+ATCOUT, // program atc registers
|
|
ATT_ADDRESS_PORT,
|
|
21,0, // count, startindex
|
|
0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
|
|
0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
|
|
0x0C, 0x0D, 0x0E, 0x0F, 0x41, 0x00,
|
|
0x0F, 0x00, 0x00,
|
|
|
|
OB, // turn video on.
|
|
ATT_ADDRESS_PORT,
|
|
0x20,
|
|
|
|
OB,
|
|
DAC_PIXEL_MASK_PORT,
|
|
0xFF,
|
|
|
|
OWM,
|
|
GRAPH_ADDRESS_PORT,
|
|
3,
|
|
|
|
//
|
|
// The Miniport Driver for R96 machine is Liner addressing mode.
|
|
// This set command was changed it for Liner addressing.
|
|
//
|
|
|
|
0x0009, 0x000a, 0x000b,
|
|
|
|
EOD
|
|
};
|
|
|
|
//
|
|
// 800x600 256-color 72Hz mode (BIOS mode 0x5C) set command string for
|
|
// CL 542x.
|
|
//
|
|
|
|
USHORT CL542x_800x600_256a72[] = {
|
|
OWM, // begin setmode
|
|
SEQ_ADDRESS_PORT,
|
|
2, // count
|
|
0x1206, // enable extensions
|
|
0x0012,
|
|
|
|
OWM, // begin setmode
|
|
SEQ_ADDRESS_PORT,
|
|
15, // count
|
|
0x100, // start sync reset
|
|
0x0101,0x0F02,0x0003,0x0E04, // program up sequencer
|
|
|
|
//
|
|
// The Miniport Driver for R96 machine is Liner addressing mode.
|
|
// This set command was changed Liner addressing.
|
|
//
|
|
|
|
(LA_MASK << 12 | 0x0107),
|
|
0x0008,
|
|
|
|
0x4A0B,0x5B0C,0x450D,0x650E,
|
|
|
|
|
|
0x2B1B,0x2F1C,0x301D,0x3A1E,
|
|
|
|
OB, // point sequencer index to ff
|
|
SEQ_ADDRESS_PORT,
|
|
0x0F,
|
|
|
|
METAOUT+MASKOUT, // masked out.
|
|
SEQ_DATA_PORT,
|
|
0xDF,0x20, // and mask, xor mask
|
|
|
|
OB, // misc. register
|
|
MISC_OUTPUT_REG_WRITE_PORT,
|
|
|
|
0xEF,
|
|
|
|
OW, // text/graphics bit
|
|
GRAPH_ADDRESS_PORT,
|
|
0x506,
|
|
|
|
OW, // end sync reset
|
|
SEQ_ADDRESS_PORT,
|
|
0x300,
|
|
|
|
OW, // unprotect crtc 0-7
|
|
CRTC_ADDRESS_PORT_COLOR,
|
|
0x2011,
|
|
|
|
METAOUT+INDXOUT, // program crtc registers
|
|
CRTC_ADDRESS_PORT_COLOR,
|
|
28,0, // count, startindex
|
|
|
|
0x7D, 0x63, 0x64, 0x80, 0x6D, 0x1C,
|
|
0x96, 0xF0, 0x00, 0x60, 0x00, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0x7B, 0x81,
|
|
0x57, 0x64, 0x00, 0x5F, 0x91, 0xE3,
|
|
0xFF, 0x00, 0x00, 0x22,
|
|
|
|
METAOUT+INDXOUT, // program gdc registers
|
|
GRAPH_ADDRESS_PORT,
|
|
9,0, // count, startindex
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
|
|
0x05, 0x0F, 0xFF,
|
|
|
|
IB, // prepare atc for writing
|
|
INPUT_STATUS_1_COLOR,
|
|
|
|
METAOUT+ATCOUT, // program atc registers
|
|
ATT_ADDRESS_PORT,
|
|
21,0, // count, startindex
|
|
0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
|
|
0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
|
|
0x0C, 0x0D, 0x0E, 0x0F, 0x41, 0x00,
|
|
0x0F, 0x00, 0x00,
|
|
|
|
OB, // turn video on.
|
|
ATT_ADDRESS_PORT,
|
|
0x20,
|
|
|
|
OB,
|
|
DAC_PIXEL_MASK_PORT,
|
|
0xFF,
|
|
|
|
OWM,
|
|
GRAPH_ADDRESS_PORT,
|
|
3,
|
|
|
|
//
|
|
// The Miniport Driver for R96 machine is Liner addressing mode.
|
|
// This set command was changed it for Liner addressing.
|
|
//
|
|
|
|
0x0009, 0x000a, 0x000b,
|
|
|
|
EOD
|
|
};
|
|
|
|
//
|
|
// 1024x768 256-color 60Hz mode (BIOS mode 0x60) set command string for
|
|
// CL 542x.
|
|
//
|
|
|
|
USHORT CL542x_1024x768_256a60[] = {
|
|
OWM, // begin setmode
|
|
SEQ_ADDRESS_PORT,
|
|
2, // count
|
|
0x1206, // enable extensions
|
|
0x0012,
|
|
|
|
OWM, // begin setmode
|
|
SEQ_ADDRESS_PORT,
|
|
15, // count
|
|
0x100, // start sync reset
|
|
0x0101,0x0F02,0x0003,0x0E04, // program up sequencer
|
|
|
|
//
|
|
// The Miniport Driver for R96 machine is Liner addressing mode.
|
|
// This set command was changed Liner addressing.
|
|
//
|
|
|
|
(LA_MASK << 12 | 0x0107),
|
|
0x0008,
|
|
|
|
0x4A0B, 0x5B0C, 0x450D, 0x760E,
|
|
0x2B1B, 0x2F1C, 0x301D, 0x341E,
|
|
|
|
OB, // point sequencer index to ff
|
|
SEQ_ADDRESS_PORT,
|
|
0x0F,
|
|
|
|
METAOUT+MASKOUT, // masked out.
|
|
SEQ_DATA_PORT,
|
|
0xDF,0x20, // and mask, xor mask
|
|
|
|
OB, // misc. register
|
|
MISC_OUTPUT_REG_WRITE_PORT,
|
|
0xEF,
|
|
|
|
OW, // text/graphics bit
|
|
GRAPH_ADDRESS_PORT,
|
|
0x506,
|
|
|
|
OW, // end sync reset
|
|
SEQ_ADDRESS_PORT,
|
|
0x300,
|
|
|
|
OW, // unprotect crtc 0-7
|
|
CRTC_ADDRESS_PORT_COLOR,
|
|
0x2011,
|
|
|
|
METAOUT+INDXOUT, // program crtc registers
|
|
CRTC_ADDRESS_PORT_COLOR,
|
|
28,0, // count, startindex
|
|
|
|
0xA3, 0x7F, 0x80, 0x86, 0x85, 0x96,
|
|
0x24, 0xFD, 0x00, 0x60, 0x00, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0x02, 0x88,
|
|
0xFF, 0x80, 0x00, 0x00, 0x24, 0xE3,
|
|
0xFF, 0x4A, 0x00, 0x22,
|
|
|
|
METAOUT+INDXOUT, // program gdc registers
|
|
GRAPH_ADDRESS_PORT,
|
|
9,0, // count, startindex
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
|
|
0x05, 0x0F, 0xFF,
|
|
|
|
IB, // prepare atc for writing
|
|
INPUT_STATUS_1_COLOR,
|
|
|
|
METAOUT+ATCOUT, // program atc registers
|
|
ATT_ADDRESS_PORT,
|
|
21,0, // count, startindex
|
|
0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
|
|
0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
|
|
0x0C, 0x0D, 0x0E, 0x0F, 0x41, 0x00,
|
|
0x0F, 0x00, 0x00,
|
|
|
|
OB, // turn video on.
|
|
ATT_ADDRESS_PORT,
|
|
0x20,
|
|
|
|
OB,
|
|
DAC_PIXEL_MASK_PORT,
|
|
0xFF,
|
|
|
|
OWM,
|
|
GRAPH_ADDRESS_PORT,
|
|
3,
|
|
|
|
//
|
|
// The Miniport Driver for R96 machine is Liner addressing mode.
|
|
// This set command was changed it for Liner addressing.
|
|
//
|
|
|
|
0x0009, 0x000a, 0x000b,
|
|
|
|
EOD
|
|
};
|
|
|
|
//
|
|
// 1024x768 256-color 70Hz mode (BIOS mode 0x60) set command string for
|
|
// CL 542x.
|
|
//
|
|
|
|
USHORT CL542x_1024x768_256a70[] = {
|
|
OWM, // begin setmode
|
|
SEQ_ADDRESS_PORT,
|
|
2, // count
|
|
0x1206, // enable extensions
|
|
0x0012,
|
|
|
|
OWM, // begin setmode
|
|
SEQ_ADDRESS_PORT,
|
|
15, // count
|
|
0x100, // start sync reset
|
|
0x0101,0x0F02,0x0003,0x0E04, // program up sequencer
|
|
|
|
//
|
|
// The Miniport Driver for R96 machine is Liner addressing mode.
|
|
// This set command was changed Liner addressing.
|
|
//
|
|
|
|
(LA_MASK << 12 | 0x0107),
|
|
0x0008,
|
|
0x4A0B, 0x5B0C, 0x450D, 0x6E0E,
|
|
0x2B1B, 0x2F1C, 0x301D, 0x2A1E,
|
|
|
|
OB, // point sequencer index to ff
|
|
SEQ_ADDRESS_PORT,
|
|
0x0F,
|
|
|
|
METAOUT+MASKOUT, // masked out.
|
|
SEQ_DATA_PORT,
|
|
0xDF,0x20, // and mask, xor mask
|
|
|
|
OB, // misc. register
|
|
MISC_OUTPUT_REG_WRITE_PORT,
|
|
0xEF,
|
|
|
|
OW, // text/graphics bit
|
|
GRAPH_ADDRESS_PORT,
|
|
0x506,
|
|
|
|
OW, // end sync reset
|
|
SEQ_ADDRESS_PORT,
|
|
0x300,
|
|
|
|
OW, // unprotect crtc 0-7
|
|
CRTC_ADDRESS_PORT_COLOR,
|
|
0x2011,
|
|
|
|
METAOUT+INDXOUT, // program crtc registers
|
|
CRTC_ADDRESS_PORT_COLOR,
|
|
28,0, // count, startindex
|
|
|
|
0xA1, 0x7F, 0x80, 0x86, 0x85, 0x96,
|
|
0x24, 0xFD, 0x00, 0x60, 0x00, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0x02, 0x88,
|
|
0xFF, 0x80, 0x00, 0x00, 0x24, 0xE3,
|
|
0xFF, 0x4A, 0x00, 0x22,
|
|
|
|
METAOUT+INDXOUT, // program gdc registers
|
|
GRAPH_ADDRESS_PORT,
|
|
9,0, // count, startindex
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
|
|
0x05, 0x0F, 0xFF,
|
|
|
|
IB, // prepare atc for writing
|
|
INPUT_STATUS_1_COLOR,
|
|
|
|
METAOUT+ATCOUT, // program atc registers
|
|
ATT_ADDRESS_PORT,
|
|
21,0, // count, startindex
|
|
0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
|
|
0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
|
|
0x0C, 0x0D, 0x0E, 0x0F, 0x41, 0x00,
|
|
0x0F, 0x00, 0x00,
|
|
|
|
OB, // turn video on.
|
|
ATT_ADDRESS_PORT,
|
|
0x20,
|
|
|
|
OB,
|
|
DAC_PIXEL_MASK_PORT,
|
|
0xFF,
|
|
|
|
OWM,
|
|
GRAPH_ADDRESS_PORT,
|
|
3,
|
|
|
|
//
|
|
// The Miniport Driver for R96 machine is Liner addressing mode.
|
|
// This set command was changed it for Liner addressing.
|
|
//
|
|
|
|
0x0009, 0x000a, 0x000b,
|
|
|
|
EOD
|
|
};
|
|
|
|
//
|
|
// 1024x768 256-color 87Hz mode (BIOS mode 0x60) set command string for
|
|
// CL 542x. (Interlaced)
|
|
//
|
|
|
|
USHORT CL542x_1024x768_256a87[] = {
|
|
OWM, // begin setmode
|
|
SEQ_ADDRESS_PORT,
|
|
2, // count
|
|
0x1206, // enable extensions
|
|
0x0012,
|
|
|
|
OWM, // begin setmode
|
|
SEQ_ADDRESS_PORT,
|
|
15, // count
|
|
0x100, // start sync reset
|
|
0x0101,0x0F02,0x0003,0x0E04, // program up sequencer
|
|
|
|
//
|
|
// The Miniport Driver for R96 machine is Liner addressing mode.
|
|
// This set command was changed Liner addressing.
|
|
//
|
|
|
|
(LA_MASK << 12 | 0x0107),
|
|
0x0008,
|
|
0x4A0B, 0x5B0C, 0x450D, 0x550E,
|
|
0x2B1B, 0x2F1C, 0x301D, 0x361E,
|
|
|
|
OB, // point sequencer index to ff
|
|
SEQ_ADDRESS_PORT,
|
|
0x0F,
|
|
|
|
METAOUT+MASKOUT, // masked out.
|
|
SEQ_DATA_PORT,
|
|
0xDF,0x20, // and mask, xor mask
|
|
|
|
OB, // misc. register
|
|
MISC_OUTPUT_REG_WRITE_PORT,
|
|
|
|
0xEF,
|
|
|
|
OW, // text/graphics bit
|
|
GRAPH_ADDRESS_PORT,
|
|
0x506,
|
|
|
|
OW, // end sync reset
|
|
SEQ_ADDRESS_PORT,
|
|
0x300,
|
|
|
|
OW, // unprotect crtc 0-7
|
|
CRTC_ADDRESS_PORT_COLOR,
|
|
0x2011,
|
|
|
|
METAOUT+INDXOUT, // program crtc registers
|
|
CRTC_ADDRESS_PORT_COLOR,
|
|
28,0, // count, startindex
|
|
|
|
0x99, 0x7F, 0x80, 0x86, 0x83, 0x99,
|
|
0x96, 0x1F, 0x00, 0x40, 0x00, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0x7F, 0x83,
|
|
0x7F, 0x80, 0x00, 0x7F, 0x12, 0xE3,
|
|
0xff, 0x4A, 0x01, 0x22,
|
|
|
|
METAOUT+INDXOUT, // program gdc registers
|
|
GRAPH_ADDRESS_PORT,
|
|
9,0, // count, startindex
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
|
|
0x05, 0x0F, 0xFF,
|
|
|
|
IB, // prepare atc for writing
|
|
INPUT_STATUS_1_COLOR,
|
|
|
|
METAOUT+ATCOUT, // program atc registers
|
|
ATT_ADDRESS_PORT,
|
|
21,0, // count, startindex
|
|
0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
|
|
0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
|
|
0x0C, 0x0D, 0x0E, 0x0F, 0x41, 0x00,
|
|
0x0F, 0x00, 0x00,
|
|
|
|
OB, // turn video on.
|
|
ATT_ADDRESS_PORT,
|
|
0x20,
|
|
|
|
OB,
|
|
DAC_PIXEL_MASK_PORT,
|
|
0xFF,
|
|
|
|
OWM,
|
|
GRAPH_ADDRESS_PORT,
|
|
3,
|
|
|
|
//
|
|
// The Miniport Driver for R96 machine is Liner addressing mode.
|
|
// This set command was changed it for Liner addressing.
|
|
//
|
|
|
|
0x0009, 0x000a, 0x000b,
|
|
|
|
EOD
|
|
};
|
|
|
|
/* START M002 */
|
|
USHORT CL542x_640x480_16M[] = {
|
|
OWM, // begin setmode
|
|
SEQ_ADDRESS_PORT,
|
|
2, // count
|
|
0x1206, // enable extensions
|
|
0x0012,
|
|
|
|
OWM, // begin setmode
|
|
SEQ_ADDRESS_PORT,
|
|
15, // count
|
|
0x100, // start sync reset
|
|
0x0101,0x0F02,0x0003,0x0E04, // program up sequencer
|
|
//
|
|
// the Miniport Driver for R96 machine is Liner addressing mode.
|
|
// This set command was changed Liner addressing.
|
|
//
|
|
(LA_MASK << 12 | 0x0507), /* L001 */
|
|
0x0008,
|
|
0x3A0B, 0x5B0C, 0x450D, 0x7E0E,
|
|
0x161B, 0x2F1C, 0x301D, 0x331E,
|
|
|
|
OB, // point sequencer index to ff
|
|
SEQ_ADDRESS_PORT,
|
|
0x0F,
|
|
|
|
METAOUT+MASKOUT, // masked out.
|
|
SEQ_DATA_PORT,
|
|
0xDF,0x20, // and mask, xor mask
|
|
|
|
OB, // misc. register
|
|
MISC_OUTPUT_REG_WRITE_PORT,
|
|
0xe3,
|
|
|
|
OW, // text/graphics bit
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|
GRAPH_ADDRESS_PORT,
|
|
0x506,
|
|
|
|
OW, // end sync reset
|
|
SEQ_ADDRESS_PORT,
|
|
0x300,
|
|
|
|
OW, // unprotect crtc 0-7
|
|
CRTC_ADDRESS_PORT_COLOR,
|
|
0x2011,
|
|
|
|
METAOUT+INDXOUT, // program crtc registers
|
|
CRTC_ADDRESS_PORT_COLOR,
|
|
28,0, // count, startindex
|
|
0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80,
|
|
0x0b, 0x3e, 0x00, 0x40, 0x00, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0xea, 0x8c,
|
|
0xdf, 0x50, 0x00, 0xe7, 0x04, 0xe3,
|
|
0xff, 0x00, 0x00, 0x22,
|
|
|
|
METAOUT+INDXOUT, // program gdc registers
|
|
GRAPH_ADDRESS_PORT,
|
|
9,0, // count, startindex
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
|
|
0x05, 0x0F, 0xFF,
|
|
|
|
IB, // prepare atc for writing
|
|
INPUT_STATUS_1_COLOR,
|
|
|
|
METAOUT+ATCOUT, // program atc registers
|
|
ATT_ADDRESS_PORT,
|
|
21,0, // count, startindex
|
|
0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
|
|
0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
|
|
0x0C, 0x0D, 0x0E, 0x0F, 0x41, 0x00,
|
|
0x0F, 0x00, 0x00,
|
|
|
|
OB, // turn video on.
|
|
ATT_ADDRESS_PORT,
|
|
0x20,
|
|
|
|
IB, DAC_PIXEL_MASK_PORT, // Hidden DAC register(HDR) is accessed by
|
|
IB, DAC_PIXEL_MASK_PORT, // reading the DAC_PIXEL_MASK_PORT four times
|
|
IB, DAC_PIXEL_MASK_PORT, // in succession; the next write or read at
|
|
IB, DAC_PIXEL_MASK_PORT, // DAC_PIXEL_MASK_PORT will access the HDR.
|
|
//
|
|
OB, // For 24bpp mode, HDR[7,6]=1,1 and
|
|
DAC_PIXEL_MASK_PORT, // HDR[3:0]=0101.
|
|
0xC5, //
|
|
|
|
OWM,
|
|
GRAPH_ADDRESS_PORT,
|
|
3,
|
|
|
|
//
|
|
// The Miniport Driver for R96 machine is Liner addressing mode.
|
|
// This set command was changed it for Liner addressing.
|
|
//
|
|
|
|
0x0009, 0x000a, 0x000b, /* L001 */
|
|
|
|
EOD
|
|
};
|
|
/* END M002 */
|
|
|
|
|
|
|
|
#endif
|