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511 lines
22 KiB
511 lines
22 KiB
/**************************************************************************\
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$Header: o:\src/RCS/NTMGA.H 1.2 95/07/07 06:16:46 jyharbec Exp $
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$Log: NTMGA.H $
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* Revision 1.2 95/07/07 06:16:46 jyharbec
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* *** empty log message ***
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*
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* Revision 1.1 95/05/02 05:16:36 jyharbec
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* Initial revision
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*
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\**************************************************************************/
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/****************************************************************************\
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* Module: ntmga.h
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*
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* Definitions for the Storm miniport driver.
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*
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* Copyright (c) 1990-1992 Microsoft Corporation
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* Copyright (c) 1993-1994 Matrox Electronic Systems Inc.
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* Copyright (c) 1995 Matrox Graphics Inc.
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\****************************************************************************/
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// Bit definitions for HwModeData.DispType
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#define DISPTYPE_INTERLACED 0x01
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#define DISPTYPE_TV 0x02
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#define DISPTYPE_LUT 0x04
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#define DISPTYPE_M565 0x08
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#define DISPTYPE_DB 0x10
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#define DISPTYPE_MON_LIMITED 0x20
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#define DISPTYPE_HW_LIMITED 0x40
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#define DISPTYPE_UNDISPLAYABLE 0x80
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#define DISPTYPE_UNUSABLE (DISPTYPE_TV | \
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DISPTYPE_MON_LIMITED | \
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DISPTYPE_HW_LIMITED | \
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DISPTYPE_UNDISPLAYABLE)
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#define MGA_BUS_INVALID 0
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#define MGA_BUS_PCI 1
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#define MGA_BUS_ISA 2
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// We can support 8, 15, 16, 24, or 32bpp displays, at any of a number of
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// resolutions. A compact way to encode this information would be to
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// use bit fields. For now, we're assuming that we don't have more than
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// 8 resolutions, which allows us to pack things within a byte.
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// These should be in sync with the SingleWidths and SingleHeights in mga.c.
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#define BIT_640x480 0
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#define BIT_800x600 1
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#define BIT_1024x768 2
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#define BIT_1152x864 3
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#define BIT_1152x882 4
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#define BIT_1280x1024 5
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#define BIT_1600x1200 6
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#define BIT_1600x1280 7 // Check your assumptions (ModeFlags, in
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// particular) if you define more than 8!
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#define BIT_INVALID 32
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// Definitions for user 3D flags.
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#define USER_NO_3DFLAG 0x00
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#define USER_Z_3DFLAG 0x01
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#define USER_DB_3DFLAG 0x02
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#define USER_3DFLAG_MASK 0x03
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// Definitions for AttributeFlags field of VIDEO_MODE_INFORMATION structure.
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#define USER_3DFLAG_SHIFT 28
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#define VIDEO_MODE_555 0x80000000
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#define VIDEO_MODE_DB USER_DB_3DFLAG << USER_3DFLAG_SHIFT //0x20000000
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#define VIDEO_MODE_Z USER_3DFLAG_MASK << USER_3DFLAG_SHIFT //0x10000000
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#define DISPTYPE_DONT_USE 0xff
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#define ZBUFFER_DONT_USE 0xff
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typedef struct tagSIZEL
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{
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LONG cx;
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LONG cy;
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} SIZEL, *PSIZEL;
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typedef struct _USER_FLAGS
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{
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BOOLEAN bDevBits; // Device bitmap support
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BOOLEAN bCenterPopUp; // Center pop-up
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BOOLEAN bUseMgaInf; // Use of MGA.INF file
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BOOLEAN bSyncDac; // Wait for vsync when accessing DAC
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} USER_FLAGS, *PUSER_FLAGS;
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// Our 'SuperMode' structure for multi-board support.
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// This describes the supermode, which boards will be involved in supporting
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// it, and which mode of each board will be required.
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typedef struct _MULTI_MODE
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{
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ULONG MulModeNumber; // unique mode Id
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ULONG MulFlags; // flags for this mode
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ULONG MulWidth; // total width of mode
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ULONG MulHeight; // total height of mode
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ULONG MulPixWidth; // pixel depth of mode
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ULONG MulRefreshRate; // refresh rate of mode
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USHORT MulArrayWidth; // number of boards arrayed along X
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USHORT MulArrayHeight; // number of boards arrayed along Y
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UCHAR MulBoardNb[NB_BOARD_MAX]; // board numbers of required boards
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USHORT MulBoardMode[NB_BOARD_MAX]; // mode required from each board
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HwModeData *MulHwModes[NB_BOARD_MAX]; // pointers to required HwModeData
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} MULTI_MODE, *PMULTI_MODE;
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/*--------------------------------------------------------------------------*\
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| HW_DEVICE_EXTENSION
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| Define device extension structure. This is device-dependant/private
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| information.
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\*--------------------------------------------------------------------------*/
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#define NB_PIXWIDTHS 5
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typedef struct _MGA_DEVICE_EXTENSION {
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ULONG SuperModeNumber; // Current mode number
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ULONG NumberOfSuperModes; // Total number of modes
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PMULTI_MODE pSuperModes; // Array of super-modes structures
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// For each board:
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ULONG NumberOfModes[NB_BOARD_MAX]; // Number of available modes
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ULONG NumberOfValidModes[NB_BOARD_MAX];
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// Number of valid modes
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UCHAR ModeFlags[NB_BOARD_MAX][NB_PIXWIDTHS];
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// Modes supported by each board
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// in 8, 15, 16, 24, and 32bpp
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USHORT ModeFreqs[NB_BOARD_MAX][NB_PIXWIDTHS*8];
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// Refresh rates bit fields
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UCHAR ModeList[NB_BOARD_MAX][NB_PIXWIDTHS*8];
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// Valid hardware modes list
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HwModeData *pMgaHwModes[NB_BOARD_MAX]; // Array of mode information structs.
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BOOLEAN bUsingInt10; // May need this later
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BOOLEAN bUsingDpms;
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BOOLEAN bAccess4G;
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BOOLEAN bAccessIo;
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UCHAR User3dFlags;
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USER_FLAGS UserFlags;
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PVOID HwDevExtToUse[NB_BOARD_MAX];
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PVOID KernelModeMappedBaseAddress[NB_BOARD_MAX];
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// Kern-mode virt addr base of regs
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PVOID UserModeMappedBaseAddress[NB_BOARD_MAX];
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// User-mode virt addr base of regs
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MULTI_MODE MultiModes[NB_MODES_MAX]; // Internal list of super-modes
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PUCHAR PciSearchRange[2];
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PUCHAR BaseAddress4G; // Mapped 4G - 128k space
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PUCHAR MappedAddress[25]; // I/O, Registers, and PCI ranges
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UCHAR VesaSet[20 * NB_BOARD_MAX * sizeof(VesaSet)];
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} MGA_DEVICE_EXTENSION, *PMGA_DEVICE_EXTENSION;
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typedef struct _EXT_HW_DEVICE_EXTENSION
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{
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MGA_DEVICE_EXTENSION *pIntDevExt;
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} EXT_HW_DEVICE_EXTENSION, *PEXT_HW_DEVICE_EXTENSION;
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#define IO_VGA_CRTC_INDEX (StormAccessRanges[2] + 0x3d4 - 0x3D4)
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#define IO_VGA_CRTC_DATA (StormAccessRanges[2] + 0x3d5 - 0x3D4)
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#define IO_VGA_ATTR_INDEX (StormAccessRanges[1] + 0x3c0 - 0x3C0)
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#define IO_VGA_ATTR_DATA (StormAccessRanges[1] + 0x3c1 - 0x3C0)
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#define IO_VGA_MISC_W (StormAccessRanges[1] + 0x3c2 - 0x3C0)
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#define IO_VGA_MISC_R (StormAccessRanges[1] + 0x3cc - 0x3C0)
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#define IO_VGA_INST0 (StormAccessRanges[1] + 0x3c2 - 0x3C0)
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#define IO_VGA_SEQ_INDEX (StormAccessRanges[1] + 0x3c4 - 0x3C0)
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#define IO_VGA_SEQ_DATA (StormAccessRanges[1] + 0x3c5 - 0x3C0)
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#define IO_VGA_DACSTAT (StormAccessRanges[1] + 0x3c7 - 0x3C0)
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#define IO_VGA_GCTL_INDEX (StormAccessRanges[1] + 0x3ce - 0x3C0)
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#define IO_VGA_GCTL_DATA (StormAccessRanges[1] + 0x3cf - 0x3C0)
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#define IO_VGA_INSTS1 (StormAccessRanges[2] + 0x3da - 0x3D4)
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#define IO_VGA_FEAT (StormAccessRanges[2] + 0x3da - 0x3D4)
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#define IO_VGA_CRTCEXT_INDEX (StormAccessRanges[3] + 0x3de - 0x3DE)
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#define IO_VGA_CRTCEXT_DATA (StormAccessRanges[3] + 0x3df - 0x3DE)
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// Old ramdac definitions
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#define OLD_BT482 0
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#define OLD_BT484 90
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#define OLD_BT485 2
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#define OLD_SIERRA 92
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#define OLD_CHAMELEON 93
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#define OLD_VIEWPOINT 1
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#define OLD_TVP3026 9
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#define OLD_PX2085 7
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#define OLD_TVP3027 10
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/*--------------------------------------------------------------------------*\
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| Structure definitions
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\*--------------------------------------------------------------------------*/
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typedef struct _VIDEO_NUM_OFFSCREEN_BLOCKS
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{
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ULONG NumBlocks; // number of offscreen blocks
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ULONG OffscreenBlockLength; // size of OFFSCREEN_BLOCK structure
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} VIDEO_NUM_OFFSCREEN_BLOCKS, *PVIDEO_NUM_OFFSCREEN_BLOCKS;
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typedef struct _OFFSCREEN_BLOCK
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{
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ULONG Type; // N_VRAM, N_DRAM, Z_VRAM, or Z_DRAM
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ULONG XStart; // X origin of offscreen memory area
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ULONG YStart; // Y origin of offscreen memory area
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ULONG Width; // offscreen width, in pixels
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ULONG Height; // offscreen height, in pixels
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ULONG SafePlanes; // offscreen available planes
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ULONG ZOffset; // Z start offset, if any Z
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} OFFSCREEN_BLOCK, *POFFSCREEN_BLOCK;
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typedef struct _RAMDAC_INFO
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{
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ULONG Flags; // Ramdac type
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ULONG Width; // Maximum cursor width
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ULONG Height; // Maximum cursor height
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ULONG OverScanX; // X overscan
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ULONG OverScanY; // Y overscan
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} RAMDAC_INFO, *PRAMDAC_INFO;
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// These structures are used with IOCTL_VIDEO_MTX_QUERY_HW_DATA. They should
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// be kept more or less in sync with the CursorInfo and HwData structures.
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typedef struct _CURSOR_INFO
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{
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ULONG MaxWidth;
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ULONG MaxHeight;
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ULONG MaxDepth;
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ULONG MaxColors;
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ULONG CurWidth;
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ULONG CurHeight;
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LONG cHotSX;
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LONG cHotSY;
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LONG HotSX;
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LONG HotSY;
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} CURSOR_INFO, *PCURSOR_INFO;
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typedef struct _HW_DATA
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{
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ULONG StructLength; /* Structure length in bytes */
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ULONG MapAddress; /* Memory map address */
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ULONG MapAddress2; /* Physical base address, frame buffer */
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ULONG RomAddress; /* Physical base address, flash EPROM */
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ULONG ProductType; /* MGA Ultima ID, MGA Impression ID, ... */
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ULONG ProductRev; /* 4 bit revision codes as follows */
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/* 0 - 3 : pcb revision */
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/* 4 - 7 : Titan revision */
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/* 8 - 11 : Dubic revision */
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/* 12 - 31 : all 1's indicating no other device
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present */
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ULONG ShellRev; /* Shell revision */
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ULONG BindingRev; /* Binding revision */
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ULONG MemAvail; /* Frame buffer memory in bytes */
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UCHAR VGAEnable; /* 0 = vga disabled, 1 = vga enabled */
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UCHAR Sync; /* relects the hardware straps */
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UCHAR Device8_16; /* relects the hardware straps */
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UCHAR PortCfg; /* 0-Disabled, 1-Mouse Port, 2-Laser Port */
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UCHAR PortIRQ; /* IRQ level number, -1 = interrupts disabled */
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ULONG MouseMap; /* Mouse I/O map base if PortCfg = Mouse Port else don't care */
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UCHAR MouseIRate; /* Mouse interrupt rate in Hz */
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UCHAR DacType; /* 0 = BT482, 3 = BT485 */
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CURSOR_INFO cursorInfo;
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ULONG VramAvail; /* VRAM memory available on board in bytes */
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ULONG DramAvail; /* DRAM memory available on board in bytes */
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ULONG CurrentOverScanX; /* Left overscan in pixels */
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ULONG CurrentOverScanY; /* Top overscan in pixels */
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ULONG YDstOrg; /* Physical offset of display start */
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ULONG YDstOrg_DB; /* Starting offset for double buffer */
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ULONG CurrentZoomFactor;
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ULONG CurrentXStart;
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ULONG CurrentYStart;
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ULONG CurrentPanXGran; /* X Panning granularity */
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ULONG CurrentPanYGran; /* Y Panning granularity */
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ULONG Features; /* Bit 0: 0 = DDC monitor not available */
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/* 1 = DDC monitor available */
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EpromInfo EpromData; /* Flash EPROM informations */
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/*** New fields for STORM ***/
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ULONG MgaBase1; /* MGA control aperture */
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ULONG MgaBase2; /* Direct frame buffer */
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ULONG RomBase; /* BIOS flash EPROM */
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ULONG PresentMCLK;
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} HW_DATA, *PHW_DATA;
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typedef struct _DPMS_INFO
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{
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BOOLEAN bSupport;
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UCHAR ucState;
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ULONG ulVersion;
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ULONG ulCapabilities;
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} DPMS_INFO, *PDPMS_INFO;
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/*--------------------------------------------------------------------------*\
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| Constant definitions
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\*--------------------------------------------------------------------------*/
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#define VIDEO_MAX_COLOR_REGISTER 0xFF // Highest DAC color register index.
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// MGA Register Map
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#define PALETTE_RAM_WRITE (RAMDAC_OFFSET + 0)
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#define PALETTE_DATA (RAMDAC_OFFSET + 1)
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// RamDacs
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#define DacTypeBT482 BT482
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#define DacTypeBT484 BT484
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#define DacTypeBT485 BT485
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#define DacTypeSIERRA SIERRA
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#define DacTypeCHAMELEON CHAMELEON
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#define DacTypeVIEWPOINT VIEWPOINT
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#define DacTypeTVP3026 TVP3026
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#define DacTypePX2085 PX2085
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#define DacTypeTVP3030 TVP3030
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#define RAMDAC_NONE 0x0000
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#define RAMDAC_BT482 0x1000
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#define RAMDAC_BT485 0x2000
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#define RAMDAC_VIEWPOINT 0x3000
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#define RAMDAC_TVP3026 0x4000
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#define RAMDAC_PX2085 0x5000
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#define RAMDAC_TVP3030 0x6000
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#define ZOOM_X1 0x00010001
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#define MCTLWTST_STD 0xC0001010
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#define TYPE_INTERLACED 0x01
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// DWGCTL Fields Definitions
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#define opcode_MASK 0x0000000F
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#define opcode_LINE_OPEN 0x00000000
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#define opcode_AUTOLINE_OPEN 0x00000001
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#define opcode_LINE_CLOSE 0x00000002
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#define opcode_AUTOLINE_CLOSE 0x00000003
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#define opcode_TRAP 0x00000004
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#define opcode_TEXTURE_TRAP 0x00000005
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#define opcode_RESERVED_1 0x00000006
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#define opcode_RESERVED_2 0x00000007
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#define opcode_BITBLT 0x00000008
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#define opcode_ILOAD 0x00000009
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#define opcode_IDUMP 0x0000000a
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#define opcode_RESERVED_3 0x0000000b
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#define opcode_FBITBLT 0x0000000c
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#define opcode_ILOAD_SCALE 0x0000000d
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#define opcode_RESERVED_4 0x0000000e
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#define opcode_ILOAD_FILTER 0x0000000f
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#define atype_MASK 0x00000070
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#define atype_RPL 0x00000000
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#define atype_RSTR 0x00000010
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#define atype_RESERVED_1 0x00000020
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#define atype_ZI 0x00000030
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#define atype_BLK 0x00000040
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#define atype_RESERVED_2 0x00000050
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#define atype_RESERVED_3 0x00000060
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#define atype_I 0x00000070
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#define linear_MASK 0x00000080
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#define linear_XY_BITBLT 0x00000000
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#define linear_LINEAR_BITBLT 0x00000080
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#define zmode_MASK 0x00000700
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#define zmode_NOZCMP 0x00000000
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#define zmode_RESERVED_1 0x00000100
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#define zmode_ZE 0x00000200
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#define zmode_ZNE 0x00000300
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#define zmode_ZLT 0x00000400
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#define zmode_ZLTE 0x00000500
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#define zmode_ZGT 0x00000600
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#define zmode_ZGTE 0x00000700
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#define solid_MASK 0x00000800
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#define solid_NO_SOLID 0x00000000
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#define solid_SOLID 0x00000800
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#define arzero_MASK 0x00001000
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#define arzero_NO_ZERO 0x00000000
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#define arzero_ZERO 0x00001000
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#define sgnzero_MASK 0x00002000
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#define sgnzero_NO_ZERO 0x00000000
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#define sgnzero_ZERO 0x00002000
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#define shftzero_MASK 0x00004000
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#define shftzero_NO_ZERO 0x00000000
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#define shftzero_ZERO 0x00004000
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#define bop_MASK 0x000F0000
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#define bop_BLACK 0x00000000 // 0 0
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#define bop_BLACKNESS 0x00000000 // 0 0
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#define bop_NOTMERGEPEN 0x00010000 // DPon ~(D | S)
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#define bop_MASKNOTPEN 0x00020000 // DPna D & ~S
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#define bop_NOTCOPYPEN 0x00030000 // Pn ~S
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#define bop_MASKPENNOT 0x00040000 // PDna (~D) & S
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#define bop_NOT 0x00050000 // Dn ~D
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#define bop_XORPEN 0x00060000 // DPx D ^ S
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#define bop_NOTMASKPEN 0x00070000 // DPan ~(D & S)
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#define bop_MASKPEN 0x00080000 // DPa D & S
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#define bop_NOTXORPEN 0x00090000 // DPxn ~(D ^ S)
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#define bop_NOP 0x000a0000 // D D
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#define bop_MERGENOTPEN 0x000b0000 // DPno D | ~S
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#define bop_COPYPEN 0x000c0000 // P S
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#define bop_SRCCOPY 0x000c0000 // P S
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#define bop_MERGEPENNOT 0x000d0000 // PDno (~D)| S
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#define bop_MERGEPEN 0x000e0000 // DPo D | S
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#define bop_WHITE 0x000f0000 // 1 1
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#define bop_WHITENESS 0x000f0000 // 1 1
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#define bop_SHIFT 16
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#define trans_MASK 0x00F00000
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#define trans_0 0x00000000
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#define trans_1 0x00100000
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#define trans_2 0x00200000
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#define trans_3 0x00300000
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#define trans_4 0x00400000
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#define trans_5 0x00500000
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#define trans_6 0x00600000
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#define trans_7 0x00700000
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#define trans_8 0x00800000
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#define trans_9 0x00900000
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#define trans_10 0x00a00000
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#define trans_11 0x00b00000
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#define trans_12 0x00c00000
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#define trans_13 0x00d00000
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#define trans_14 0x00e00000
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#define trans_15 0x00f00000
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#define trans_SHIFT 20
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#define bltmod_MASK 0x1E000000
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#define bltmod_BMONOLEF 0x00000000
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#define bltmod_BPLAN 0x02000000
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#define bltmod_BFCOL 0x04000000
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#define bltmod_BU32BGR 0x06000000
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#define bltmod_BMONOWF 0x08000000
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#define bltmod_RESERVED_1 0x0a000000
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#define bltmod_RESERVED_2 0x0c000000
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#define bltmod_BU32RGB 0x0e000000
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#define bltmod_RESERVED_3 0x10000000
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#define bltmod_RESERVED_4 0x12000000
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#define bltmod_RESERVED_5 0x14000000
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#define bltmod_BU24BGR 0x16000000
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#define bltmod_RESERVED_6 0x18000000
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#define bltmod_RESERVED_7 0x1a000000
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#define bltmod_BUYUV 0x1c000000
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#define bltmod_BU24RGB 0x1e000000
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#define pattern_MASK 0x20000000
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#define pattern_OFF 0x00000000
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#define pattern_ON 0x20000000
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#define transc_MASK 0x40000000
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#define transc_BG_OPAQUE 0x00000000
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#define transc_BG_TRANSP 0x40000000
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#define transc_SHIFT 30
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/*--------------------------------------------------------------------------*\
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| Private I/O request control codes
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\*--------------------------------------------------------------------------*/
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#define COMMON_FLAG 0x80000000
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#define CUSTOM_FLAG 0x00002000
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#define IOCTL_VIDEO_MTX_QUERY_NUM_OFFSCREEN_BLOCKS \
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CTL_CODE(FILE_DEVICE_VIDEO, 0x800, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_VIDEO_MTX_QUERY_OFFSCREEN_BLOCKS \
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CTL_CODE(FILE_DEVICE_VIDEO, 0x801, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_VIDEO_MTX_INITIALIZE_MGA \
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CTL_CODE(FILE_DEVICE_VIDEO, 0x802, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_VIDEO_MTX_QUERY_RAMDAC_INFO \
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CTL_CODE(FILE_DEVICE_VIDEO, 0x803, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_VIDEO_MTX_GET_UPDATED_INF \
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CTL_CODE(FILE_DEVICE_VIDEO, 0x804, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_VIDEO_MTX_QUERY_BOARD_ID \
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CTL_CODE(FILE_DEVICE_VIDEO, 0x805, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_VIDEO_MTX_QUERY_HW_DATA \
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CTL_CODE(FILE_DEVICE_VIDEO, 0x806, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_VIDEO_MTX_QUERY_BOARD_ARRAY \
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CTL_CODE(FILE_DEVICE_VIDEO, 0x807, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_VIDEO_MTX_MAKE_BOARD_CURRENT \
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CTL_CODE(FILE_DEVICE_VIDEO, 0x808, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_VIDEO_MTX_INIT_MODE_LIST \
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CTL_CODE(FILE_DEVICE_VIDEO, 0x809, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_VIDEO_MTX_QUERY_INITBUF_DATA \
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CTL_CODE(FILE_DEVICE_VIDEO, 0x80A, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_VIDEO_MTX_QUERY_USER3D_SUBPIXEL \
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CTL_CODE(FILE_DEVICE_VIDEO, 0x80B, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_VIDEO_MTX_DPMS_REPORT \
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CTL_CODE(FILE_DEVICE_VIDEO, 0x80C, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_VIDEO_MTX_DPMS_GET_STATE \
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CTL_CODE(FILE_DEVICE_VIDEO, 0x80D, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_VIDEO_MTX_DPMS_SET_STATE \
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CTL_CODE(FILE_DEVICE_VIDEO, 0x80E, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_VIDEO_MTX_QUERY_USER_FLAGS \
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CTL_CODE(FILE_DEVICE_VIDEO, 0x80F, METHOD_BUFFERED, FILE_ANY_ACCESS)
|