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246 lines
6.3 KiB
246 lines
6.3 KiB
/*++
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Copyright (c) 1994 FirePower Systems, Inc.
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Module Name:
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psidisp.h
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Abstract:
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This header file contains definition information
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for PSI's DCC Miniport driver. All register definitons
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for DCC and Bt445 are included in psidcc.h,
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and all common information between psidisp.dll (display driver)
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and psidisp.sys (miniport driver) is defined in common header
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file of pcomm.h.
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Author:
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Neil Ogura (9-7-1994)
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Environment:
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Version history:
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--*/
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/*
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* Copyright (c) 1995 FirePower Systems, Inc.
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* DO NOT DISTRIBUTE without permission
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*
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* $RCSfile: psidisp.h $
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* $Revision: 1.2 $
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* $Date: 1996/04/24 00:07:44 $
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* $Locker: $
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*/
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/** This flag is to use timer function for performance measurement - need to be set to FALSE
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for production also, INVESTIGATION flag in driver.h in PSIDISP.DLL has to be set to FALSE **/
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#define INVESTIGATE FALSE
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/** This flag is to determine wether to support 5-6-5 16 bit mode (in addition to
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5-5-5 15 bit mode. This flag should be matching with the same flag in driver.h
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for PSIDISP.DLL. **/
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#define SUPPORT_565 TRUE
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/** This flag is to determine wether to support 1280X1024X8 bit 60 Hz mode (in addition to
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75Hz). It's not VESA standard, but it's convenient to have such mode for testing. **/
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#define SUPPORT_NON_VESA FALSE
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#define NO_MASK 0
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#define MEM1MB 0x00100000
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#define MEM2MB 0x00200000
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#define MEM4MB 0x00400000
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#define ADDRESS_MUNGE_FOR_BYTE 0x07 // Access 7 bytes ahead for munge
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#define ADDRESS_MUNGE_FOR_SHORT 0x03 // Access 3 half words ahead (6 bytes) for munge
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#define ADDRESS_MUNGE_FOR_WORD 0x01 // Access 1 word (4 bytes) ahead for munge
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#define SYSTEM_REG_SIZE 0x08
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#define VRAM_PHYSICAL_ADDRESS_BASE 0x70000000
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#define MAX_VRAM_SIZE MEM4MB
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#define ISA_IO_PHYSICAL_ADDRESS_BASE 0x80000000
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#define DCC_REGISTER_BASE 0x840
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#define DCC_SIZE 0x02
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#define Bt445_REGISTER_BASE 0x860
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#define Bt445_SIZE 0x0f
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#define NUM_ACCESS_RANGE_CHECK 3 // Don't check system registers conflict
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#define VRAM_DETECT_REGISTER_BASE_1 0x890
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#define VRAM_DETECT_REGISTER_BASE_2 0x8c0
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#define VRAM_DETECT_REGISTER_SIZE 0x01
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#define VRAM_CTRL_REGISTER_BASE (0xff100008 - ISA_IO_PHYSICAL_ADDRESS_BASE)
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#define VRAM_CTRL_REGISTER_SIZE 0x08
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#define VRAM_CTRL_REGISTER_MASK 0x07
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#define MEM_BANK7_CONFIG_REGISTER_BASE (0xff100438 - ISA_IO_PHYSICAL_ADDRESS_BASE)
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#define MEM_BANK7_CONFIG_REGISTER_SIZE 0x08
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#define MEM_BANK7_CONFIG_REGISTER_MASK 0x80
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#define VRAM_TIMING_REGISTER_BASE (0xff100508 - ISA_IO_PHYSICAL_ADDRESS_BASE)
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#define VRAM_TIMING_REGISTER_SIZE 0x08
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#define VRAM_TIMING_REGISTER_MASK 0x7f
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#define MEM_REFRESH_REGISTER_BASE (0xff100510 - ISA_IO_PHYSICAL_ADDRESS_BASE)
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#define MEM_REFRESH_REGISTER_SIZE 0x08
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#define SYSTEM_INTERRUPT_REGISTER_BASE (0xff000000 - ISA_IO_PHYSICAL_ADDRESS_BASE)
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#define SYSTEM_INTERRUPT_REGISTER_SIZE 0x08
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#define SYSTEM_INTERRUPT_DISPLAY_BIT 0x0020
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#define PCI_DEVICE_ID_REGISTER_BASE (0xff400108 - ISA_IO_PHYSICAL_ADDRESS_BASE)
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#define PCI_DEVICE_ID_REGISTER_SIZE 0x08
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#define NUM_ACCESS_RANGE 11
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#if INVESTIGATE
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#define TSC_STATUS_REGISTER_BASE (0xff100200 - ISA_IO_PHYSICAL_ADDRESS_BASE)
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#define TSC_STATUS_REGISTER_SIZE 0x08
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#endif
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//
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// PCI ID for models
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//
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#define PCI_ID_FOR_POWER_PRO 0x6073
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#define PCI_ID_FOR_POWER_TOP 0x6037
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//
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// Define structures for initializing system registers
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//
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typedef struct _SYSTEM_REG_INIT {
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UCHAR VramTiming;
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UCHAR VramControl;
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UCHAR Mem7Config;
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UCHAR MemRefresh;
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} SYSTEM_REG_INIT,*PSYSTEM_REG_INIT;
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//
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// Define structures for controller configuration structure
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//
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typedef struct _DCC_CONFIGURATION_DATA {
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USHORT Version;
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USHORT Revision;
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USHORT Irql;
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USHORT Vector;
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ULONG ControlBase;
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ULONG ControlSize;
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ULONG CursorBase;
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ULONG CursorSize;
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ULONG FrameBase;
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ULONG FrameSize;
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} DCC_CONFIGURATION_DATA, *PDCC_CONFIGURATION_DATA;
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//
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// Define generic display configuration data structure found in ARC
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// machine PROM
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//
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typedef struct _MONITOR_CONFIG_DATA {
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USHORT Version;
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USHORT Revision;
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USHORT HorizontalResolution;
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USHORT HorizontalDisplayTime;
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USHORT HorizontalBackPorch;
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USHORT HorizontalFrontPorch;
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USHORT HorizontalSync;
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USHORT VerticalResolution;
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USHORT VerticalBackPorch;
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USHORT VerticalFrontPorch;
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USHORT VerticalSync;
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USHORT HorizontalScreenSize;
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USHORT VerticalScreenSize;
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} MONITOR_CONFIG_DATA, *PMONITOR_CONFIG_DATA;
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//
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// Image type list.
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//
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typedef enum _DCC_PIXEL_TYPE {
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PIXEL_8 = 0,
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PIXEL_15,
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#if SUPPORT_565
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PIXEL_16,
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#endif
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PIXEL_32,
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NUMBER_OF_PIXEL_TYPES
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} DCC_PIXEL_TYPE;
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//
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// Video mode table structure - Lists the information about each individual mode
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//
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typedef struct _DCC_VIDEO_MODES {
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ULONG minimumMemoryRequired;
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DCC_PIXEL_TYPE pixelType;
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VIDEO_MODE_INFORMATION modeInformation;
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} DCC_VIDEO_MODES, PDCC_VIDEO_MODES;
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//
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// List of mode indexes.
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//
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typedef enum _DCC_MODE_LIST {
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mode640_480_8_72 = 0,
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mode640_480_8_75,
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mode640_480_15_72,
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mode640_480_15_75,
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#if SUPPORT_565
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mode640_480_16_72,
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mode640_480_16_75,
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#endif
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mode640_480_32_72,
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mode640_480_32_75,
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mode800_600_8_60,
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mode800_600_8_72,
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mode800_600_8_75,
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mode800_600_15_60,
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mode800_600_15_72,
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mode800_600_15_75,
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#if SUPPORT_565
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mode800_600_16_60,
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mode800_600_16_72,
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mode800_600_16_75,
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#endif
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mode800_600_32_60,
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mode800_600_32_72,
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mode800_600_32_75,
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mode1024_768_8_60,
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mode1024_768_8_70,
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mode1024_768_8_75,
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mode1024_768_15_60,
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mode1024_768_15_70,
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mode1024_768_15_75,
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#if SUPPORT_565
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mode1024_768_16_60,
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mode1024_768_16_70,
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mode1024_768_16_75,
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#endif
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mode1024_768_32_60,
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mode1024_768_32_70,
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mode1024_768_32_75,
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#if SUPPORT_NON_VESA
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mode1152_864_8_60,
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mode1152_864_8_70,
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mode1152_864_8_75,
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mode1152_864_15_60,
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mode1152_864_15_70,
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mode1152_864_15_75,
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#if SUPPORT_565
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mode1152_864_16_60,
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mode1152_864_16_70,
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mode1152_864_16_75,
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#endif
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mode1152_864_32_60,
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mode1152_864_32_70,
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mode1152_864_32_75,
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mode1280_1024_8_60,
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mode1280_1024_8_70,
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#endif
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mode1280_1024_8_75,
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#if SUPPORT_NON_VESA
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mode1280_1024_15_60,
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mode1280_1024_15_70,
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#endif
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mode1280_1024_15_75,
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#if SUPPORT_565
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#if SUPPORT_NON_VESA
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mode1280_1024_16_60,
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mode1280_1024_16_70,
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#endif
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mode1280_1024_16_75,
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#endif
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NUMBER_OF_MODES
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} DCC_MODE_LIST;
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#define NUMBER_OF_COLORS 256 // number of colorsto set to the palette
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