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436 lines
13 KiB
436 lines
13 KiB
/*++
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Copyright (c) 1993 Digital Equipment Corporation
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Module Name:
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tga.h
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Abstract:
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Private include file for the TGA Device Driver.
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Author:
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Ritu Bahl 22-Jul-1993
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Environment:
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Kernel mode only.
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Notes:
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Revision History
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02-23-94 (ritub) Added CursorMaskSize field to hwDeviceEXtension.
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10-27-94 (macinnes) Added additional modes to TGA_MODES.
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12-14-94 (macinnes) Added adapter_number field to device extension.
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12-15-94 (macinnes) Add device extension fields for TGA2
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12-27-94 (macinnes) Add new mode field for TGA2 pll data
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12-29-94 (macinnes) Update BT485 macros to support TGA2
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01-06-95 (macinnes) Add entry points for RAMDAC functions
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01-18-95 (macinnes) Remove some of the DMA data types that are not
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supported by the videoport .h files.
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03-02-95 (macinnes) Remove lots of unreferenced definitions.
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03-03-95 (macinnes) Removed ioctl code definitions.
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04-17-95 (macinnes) Increased the size of VIDEO_MAX_COLOR_REGISTER
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for the BT463 color map table.
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05-23-95 (macinnes) Added some definitions for the Interrupt
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Status register.
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--*/
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#include "tgaioctl.h"
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#ifndef _TGA_
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#define _TGA_
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//
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// Define
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#define DMA 1 // Compile the DMA ioctl code
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#define NUM_TGA_VIDEO_MODES 10
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#define TARGET_ABORT 0x10000000
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#define MASTER_ABORT 0x20000000
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typedef struct _TGA_DMADATA_
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{
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VOID *source;
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ULONG target; // offset into framebuffer
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ULONG command;
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ULONG shift;
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} TGA_DMADATA, *PTGA_DMADATA;
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typedef struct _TGA_DMA {
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PVOID bitmap;
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ULONG size;
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} TGA_DMA, *PTGA_DMA;
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typedef struct _VIRT_TO_BUS_
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{
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PVOID vaddr;
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ULONG size;
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} VIRT_TO_BUS, *PVIRT_TO_BUS;
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#define TGA_0_0_FB_OFFSET 0x00200000
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#define TGA_0_0_FB_SIZE 0X00200000
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#define TGA_0_1_FB_OFFSET 0x00400000
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#define TGA_0_1_FB_SIZE 0x00400000
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#define TGA_0_3_FB_OFFSET 0x00800000
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#define TGA_0_3_FB_SIZE 0x00800000
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#define TGA_0_7_FB_OFFSET 0x01000000
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#define TGA_0_7_FB_SIZE 0x01000000
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#define TGA_ASIC_OFFSET 0x00100000
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#define TGA_ASIC_LENGTH 0x00100000
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#define FRAMEBUFFER_OFFSET_8 0x1000 // 4k
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#define FRAMEBUFFER_OFFSET_24 0x4000 // 16k
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#define BT_CURSOR_DISABLED 0
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#define BT_CURSOR_WINDOWS 2
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#define BT485_CURSOR_WIDTH 32 // width of hardware cursor
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#define BT485_CURSOR_HEIGHT 32 // height of hardware cursor
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#define BT485_CURSOR_BITS_PER_PIXEL 2 // hardware cursor bits per pixel
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#define BT485_CURSOR_NUMBER_OF_BYTES BT485_CURSOR_WIDTH/8 * BT485_CURSOR_HEIGHT *2
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#define IBM561_CURSOR_WIDTH 64 // width of hardware cursor
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#define IBM561_CURSOR_HEIGHT 64 // height of hardware cursor
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#define IBM561_CURSOR_BITS_PER_PIXEL 2 // hardware cursor bits per pixel
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#define IBM561_CURSOR_NUMBER_OF_BYTES IBM561_CURSOR_WIDTH/8 * IBM561_CURSOR_HEIGHT *2
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// Above means 4 pixels per byte
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typedef enum _RAMDAC_TYPE {
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BT485,
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BT463,
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IBM561
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} RAMDAC_TYPE;
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//
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// List of all the supported video modes in TGA. These must be in the
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// same order as the corresponding entries in TGAModes[] in tgadata.h.
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//
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typedef enum _TGA_MODES {
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TGA_MODE_640_480_60_8_1BUF_1HD, // Mode 0
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TGA_MODE_640_480_72_8_1BUF_1HD, // Mode 1
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TGA_MODE_640_480_60_24_1BUF_1HD, // Mode 2
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TGA_MODE_640_480_72_24_1BUF_1HD, // Mode 3
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TGA_MODE_800_600_72_8_1BUF_1HD, // Mode 4
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TGA_MODE_800_600_60_8_1BUF_1HD, // Mode 5
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TGA_MODE_800_600_72_24_1BUF_1HD, // Mode 6
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TGA_MODE_800_600_60_24_1BUF_1HD, // Mode 7
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TGA_MODE_1024_768_72_8_1BUF_1HD, // Mode 8
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TGA_MODE_1024_768_70_8_1BUF_1HD, // Mode 9
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TGA_MODE_1024_768_60_8_1BUF_1HD, // Mode a
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TGA_MODE_1024_768_72_24_1BUF_1HD, // Mode b
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TGA_MODE_1024_768_60_24_1BUF_1HD, // Mode c
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TGA_MODE_1024_864_60_8_1BUF_1HD, // Mode d
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TGA_MODE_1024_864_60_24_1BUF_1HD, // Mode e
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TGA_MODE_1280_1024_72_8_1BUF_1HD, // Mode f
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TGA_MODE_1280_1024_66_8_1BUF_1HD, // Mode 10
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TGA_MODE_1280_1024_60_8_1BUF_1HD, // Mode 11
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TGA_MODE_1280_1024_72_24_1BUF_1HD, // Mode 12
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TGA_MODE_1280_1024_60_24_1BUF_1HD, // Mode 13
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TGA_MODE_1152_900_72_8_1BUF_1HD, // Mode 14
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TGA_MODE_1152_900_66_8_1BUF_1HD, // Mode 15
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TGA_MODE_1152_900_72_24_1BUF_1HD, // Mode 16
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// tgadata.h originally only defined to this point (21 enties)
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// Following entries were added to complete the table (macinnes)
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TGA_MODE_1024_768_70_24_1BUF_1HD, // Mode 17
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TGA_MODE_1280_1024_66_24_1BUF_1HD, // Mode 18
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TGA_MODE_1152_900_66_24_1BUF_1HD, // Mode 19
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TGA_MODE_1280_1024_75_8_1BUF_1HD, // Mode 1A
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TGA_MODE_1280_1024_75_24_1BUF_1HD, // Mode 1B
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} TGA_MODES;
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typedef struct _TGA_VIDEO_MODES {
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UCHAR ModeValid;
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ULONG RequiredVideoMemory;
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H_TIMING h_cont;
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V_TIMING v_cont;
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UCHAR PllData[8];
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ULONG PllData_tga2[8];
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VIDEO_MODE_INFORMATION ModeInformation;
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} TGA_VIDEO_MODES, *PTGA_VIDEO_MODES;
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typedef struct _bt485_color_cell {
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unsigned char dirty_cell;
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unsigned char red;
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unsigned char green;
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unsigned char blue;
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} bt485_color_cell;
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typedef struct {
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ULONG pixelmask;
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TGAMode mode;
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TGARasterOp rop;
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ULONG bres3;
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ULONG address;
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} TGARegRec, *PTGARegRec;
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typedef struct _bt485_info {
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ULONG fb_xoffset;
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ULONG fb_yoffset;
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UCHAR screen_on;
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UCHAR on_off;
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UCHAR dirty_cursor;
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ULONG x_hot;
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ULONG y_hot;
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ULONG bits[256];
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bt485_color_cell cursor_fg;
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bt485_color_cell cursor_bg;
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} bt485_info, *Pbt485_info;
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#define NUMBER_OF_CURSOR_COLORS 4
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#define PCI_COMMON_HEADER_LENGTH PCI_COMMON_HDR_LENGTH
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typedef
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VOID
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(*RAMDAC_ENTRY) (
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IN PUVOID
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);
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//
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// Define device extension structure. This is device dependant/private
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// information.
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//
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typedef struct _HW_DEVICE_EXTENSION {
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PHYSICAL_ADDRESS PhysicalFrameAddress;
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UCHAR InIoSpace;
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ULONG FrameLength;
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PUCHAR RegisterSpace;
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PUCHAR RegisterAlias;
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PUCHAR ConfigSpace;
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ULONG ChipId;
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PUCHAR IoBuffer;
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ULONG image_count;
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ULONG IoBufferSize;
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PVOID DriverObject;
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ULONG dma_size;
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ULONG dma_count;
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ULONG RegisterLength;
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ULONG ModeNumber;
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ULONG ModelNumber;
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ULONG NumAvailModes;
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ULONG VideoMemoryInMegs;
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ULONG NumberOfMapRegisters;
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PUCHAR highestValidAddress;
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PVOID MapRegisterBase;
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ULONG BoardID;
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ULONG bpp;
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TGADepth depth;
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ULONG refresh_count;
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ULONG horizontol_setup;
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ULONG vertical_setup;
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ULONG fb_offset;
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ULONG AdapterMemorySize;
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ULONG CurrentModeNumber;
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TGARegRec tgastate;
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ULONG x_offset;
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ULONG y_offset;
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ULONG screen_width;
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ULONG screen_height;
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ULONG screen_max_row;
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ULONG screen_f_height;
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Pbt485_info btp;
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union{
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VIDEO_CLUTDATA RgbData;
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ULONG RgbLong;
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} cursor_clut[NUMBER_OF_CURSOR_COLORS];
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UCHAR CursorPixels[IBM561_CURSOR_NUMBER_OF_BYTES];
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UCHAR CursorEnable;
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ULONG CursorMaskSize;
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UCHAR UpdateCursorPosition;
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UCHAR RamdacBusy;
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UCHAR RamdacBusyLogged;
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UCHAR UpdateCursorPixels;
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SHORT CursorColumn;
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SHORT CursorRow;
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USHORT CursorXOrigin;
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USHORT CursorYOrigin;
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USHORT CursorWidth;
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USHORT CursorHeight;
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ULONG intr_reg;
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ULONG adapter_number;
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PUCHAR memory_space_base;
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USHORT is_tga;
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USHORT is_tga2;
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RAMDAC_TYPE ramdac_type;
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RAMDAC_ENTRY set_cursor_position;
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RAMDAC_ENTRY set_cursor_pattern;
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RAMDAC_ENTRY set_cursor_disable;
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RAMDAC_ENTRY set_cursor_enable;
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RAMDAC_ENTRY set_color_entry;
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PVOID dma_extension;
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PVOID a_tga_info;
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PVOID a_ramdac_info;
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ULONG pcrr;
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} HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION;
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#define TGA_WRITE( addr, value ) \
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VideoPortWriteRegisterUlong( (PULONG) \
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(hwDeviceExtension->RegisterSpace + (addr) ), \
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( (value) ) );
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#define TGA_READ(addr) \
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VideoPortReadRegisterUlong( (PULONG) \
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((ULONG)hwDeviceExtension->RegisterSpace + (addr) ))
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//
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// Note that in the NT source, the "addr" constants have a one
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// bit shift incorporated into them (because of a low order
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// read/write bit, read = 1).
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//
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// For Windows NT, a macro to write an 8 bit value to the RAMDAC
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//
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#define BT485_WRITE(addr, value) \
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if (hwDeviceExtension->is_tga) \
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VideoPortWriteRegisterUlong ( (PULONG) \
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(hwDeviceExtension->RegisterSpace+ RAMDAC_INTERFACE), \
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( ((addr)<<8) | ((value)&0xff))); \
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else \
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if (hwDeviceExtension->is_tga2) \
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VideoPortWriteRegisterUlong( \
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(PULONG)((ULONG)hwDeviceExtension->memory_space_base + \
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0x80000 + 0xE000 + (((addr) >> 1) << 8)), \
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value & 0xFF);
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//
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// For Windows NT, specify a RAMDAC address for a subsequent read
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// (for TGA only, not TGA2)
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//
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#define BT485_READ_SETUP( addr ) \
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if (hwDeviceExtension->is_tga) \
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VideoPortWriteRegisterUlong( (PULONG) \
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(hwDeviceExtension->RegisterSpace + RAMDAC_SETUP), \
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( (addr) | BT485_SETUP_READ ));
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#define BT485_SETUP_RW_MASK (BT485_SETUP_WRITE|BT485_SETUP_READ)
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#define BT485_SETUP_WRITE 0x00000000
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#define BT485_SETUP_READ 0x00000001
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#define BT485_SETUP_RS0_MASK 0x00000002
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#define BT485_SETUP_RS1_MASK 0x00000004
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#define BT485_SETUP_RS2_MASK 0x00000008
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#define BT485_SETUP_RS3_MASK 0x00000010
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#define BT485_PALETTE_CURSOR_WRITE_ADDR 0
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#define BT485_ADDR_COLOR_PALETTE_READ (BT485_SETUP_RS0_MASK| \
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BT485_SETUP_RS1_MASK)
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#define BT485_COLOR_PALETTE_DATA (BT485_SETUP_RS0_MASK)
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#define BT485_CURSOR_COLOR_WRITE_ADDR (BT485_SETUP_RS2_MASK)
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#define BT485_ADDR_CURS_COLOR_READ (BT485_SETUP_RS0_MASK| \
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BT485_SETUP_RS1_MASK| \
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BT485_SETUP_RS2_MASK)
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#define BT485_DATA_CURSOR_COLOR (BT485_SETUP_RS0_MASK| \
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BT485_SETUP_RS2_MASK)
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#define BT485_CURSOR_RAM_ARRAY_DATA (BT485_SETUP_RS0_MASK| \
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BT485_SETUP_RS1_MASK| \
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BT485_SETUP_RS3_MASK)
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#define BT485_PIXEL_MASK_REGISTER (BT485_SETUP_RS1_MASK)
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#define BT485_CMD_REG_0 (BT485_SETUP_RS1_MASK| \
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BT485_SETUP_RS2_MASK)
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#define BT485_CMD_REG_1 (BT485_SETUP_RS3_MASK)
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#define BT485_CMD_REG_2 (BT485_SETUP_RS0_MASK| \
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BT485_SETUP_RS3_MASK)
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#define BT485_STATUS_REG (BT485_SETUP_RS1_MASK| \
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BT485_SETUP_RS3_MASK)
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#define BT485_CURSOR_X_HIGH (BT485_SETUP_RS0_MASK| \
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BT485_SETUP_RS2_MASK| \
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BT485_SETUP_RS3_MASK)
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#define BT485_CURSOR_X_LOW (BT485_SETUP_RS2_MASK| \
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BT485_SETUP_RS3_MASK)
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#define BT485_CURSOR_Y_HIGH (BT485_SETUP_RS0_MASK| \
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BT485_SETUP_RS1_MASK| \
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BT485_SETUP_RS2_MASK| \
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BT485_SETUP_RS3_MASK)
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#define BT485_CURSOR_Y_LOW (BT485_SETUP_RS1_MASK| \
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BT485_SETUP_RS2_MASK| \
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BT485_SETUP_RS3_MASK)
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#define TGA_INTR_VSYNC 0x00000001 // VSYNC occurred
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#define TGA_INTR_ALL 0X0000001F // All possible enable bits
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#define TGA_INTR_ALL_TGA 0X00000013 // Those actually used on TGA
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#define TGA_INTR_ALL_TGA2 0X0000000F // Those actually used on TGA2
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#define TGA_INTR_ENABLE_SHIFT 16 // To get to "enable" part of
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// the Interrupt Status register
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#define VIDEO_MAX_COLOR_REGISTER 0x529
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#endif //_TGA_
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