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383 lines
10 KiB
383 lines
10 KiB
/*++
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Copyright (c) September 1993 Digital Equipment Corporation
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Module Name:
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tga_reg.h
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Abstract:
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This module contains the register definitions for the TGA miniport
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driver.
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Author:
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Ritu Bahl creation-data 15-Aug-1993
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Environment:
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Kernel mode.
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Revision Histort:
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--*/
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// TGA register offsets, organized by functionality.
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/*
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** Graphics Command Registers.
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*/
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#define BRES_CONT 0x0000004C
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#define START 0x00000054
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#define SLOPE_NO_GO_R0 0x00000100
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#define SLOPE_NO_GO_R1 0x00000104
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#define SLOPE_NO_GO_R2 0x00000108
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#define SLOPE_NO_GO_R3 0x0000010C
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#define SLOPE_NO_GO_R4 0x00000110
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#define SLOPE_NO_GO_R5 0x00000114
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#define SLOPE_NO_GO_R6 0x00000118
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#define SLOPE_NO_GO_R7 0x0000011C
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#define SLOPE_R0 0x00000120
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#define SLOPE_R1 0x00000124
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#define SLOPE_R2 0x0000012C
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#define SLOPE_R4 0x00000130
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#define SLOPE_R5 0x00000134
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#define SLOPE_R6 0x00000138
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#define SLOPE_R7 0x0000013C
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#define COPY_64_SRC 0x00000160
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#define COPY_64_DEST 0x00000164
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#define COPY_64_SRC_A1 0x00000168 // alias
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#define COPY_64_DEST_A1 0x0000016C // alias
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#define COPY_64_SRC_A2 0x00000170 // alias
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#define COPY_64_DEST_A2 0x00000174 // alias
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#define COPY_64_SRC_A3 0x00000178 // alias
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#define COPY_64_DEST_A3 0x0000017C // alias
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/*
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** Graphics Control Registers.
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*/
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#define COPY_BUFFER_0 0x00000000
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#define COPY_BUFFER_1 0x00000004
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#define COPY_BUFFER_2 0x00000008
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#define COPY_BUFFER_3 0x0000000C
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#define COPY_BUFFER_4 0x00000010
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#define COPY_BUFFER_5 0x00000014
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#define COPY_BUFFER_6 0x00000018
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#define COPY_BUFFER_7 0x0000001C
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#define FOREGROUND 0x00000020
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#define BACKGROUND 0x00000024
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#define PLANE_MASK 0x00000028
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#define ONE_SHOT_PIXEL_MASK 0x0000002C
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#define MODE 0x00000030
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#define RASTER_OP 0x00000034
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#define PIXEL_SHIFT 0x00000038
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#define ADDRESS 0x0000003C
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#define BRES_R1 0x00000040
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#define BRES_R2 0x00000044
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#define BRES_R3 0x00000048
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#define DEEP 0x00000050
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#define STENCIL_MODE 0x00000058
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#define PERS_PIXEL_MASK 0x0000005C
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#define DATA 0x00000080
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#define RED_INCR 0x00000084
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#define GREEN_INCR 0x00000088
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#define BLUE_INCR 0x0000008C
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#define Z_INCR_LOW 0x00000090
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#define Z_INCR_HIGH 0x00000094
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#define DMA_ADDRESS 0x00000098
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#define BRES_WIDTH 0x0000009C
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#define Z_VAL_LOW 0x000000A0
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#define Z_VAL_HIGH 0x000000A4
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#define Z_BASE_ADDR 0x000000A8
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#define ADDRESS_1 0x000000AC
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#define RED_VALUE 0x000000B0
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#define GREEN_VALUE 0x000000B4
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#define BLUE_VALUE 0x000000B8
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#define SPAN_WIDTH 0x000000BC
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#define BLK_COLOR_R0 0X00000140
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#define BLK_COLOR_R1 0X00000144
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#define BLK_COLOR_R2 0X00000148
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#define BLK_COLOR_R3 0X0000014C
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#define BLK_COLOR_R4 0X00000150
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#define BLK_COLOR_R5 0X00000154
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#define BLK_COLOR_R6 0X00000158
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#define BLK_COLOR_R7 0X0000015C
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/*
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** Video Timing Registers
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*/
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#define H_CONT 0x00000064
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#define V_CONT 0x00000068
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#define VIDEO_BASE_ADDR 0x0000006C
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#define VIDEO_VALID 0x00000070
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#define VIDEO_SHIFT_ADDR 0x00000078
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/*
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** Cursor Control Regsiters
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*/
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#define CUR_BASE_ADDR 0x00000060
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#define CURSOR_XY 0x00000074
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/*
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** Miscellaneous Registers.
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*/
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#define INTR_STATUS 0x0000007C
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#define RAMDAC_SETUP 0x000000C0
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#define EPROM_WRITE 0x000001e0
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#define CLOCK 0x000001e8
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#define RAMDAC_INTERFACE 0X000001f0
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#define COMMAND_STATUS 0x000001f8
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#define PIDR 0x00000000
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#define PCSR 0x00000004
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#define PDBR 0x00000010
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#define PRBR 0x00000030
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/* ********************************************************** */
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/* **** Some data structure definitions **** */
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/* **** **** */
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/************************************************************ */
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/*
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** Mode register fields. Mode definition.
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*/
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typedef struct _TGAMode {
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unsigned mode : 8;
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unsigned visual : 3;
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unsigned rotate : 2;
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unsigned line : 1;
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unsigned z16 : 1;
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unsigned cap_ends: 1;
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unsigned mbz : 16;
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} TGAMode;
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/*
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** Depth register fields. specifies the type and configuration
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** of the frame buffer.
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*/
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typedef struct _TGADepth
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{
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unsigned deep : 1;
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unsigned mbz0 : 1;
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unsigned mask : 3;
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unsigned block : 4;
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unsigned col_size: 1;
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unsigned sam_size: 1;
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unsigned parity : 1;
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unsigned write_en: 1;
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unsigned ready : 1;
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unsigned slow_dac: 1;
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unsigned dma_size: 1;
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unsigned sync_typ: 1;
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unsigned mbz1 : 15;
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} TGADepth;
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typedef union {
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ULONG deep_reg;
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TGADepth deep;
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} depth_reg;
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/*
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** Stencil Mode Register definition
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*/
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typedef struct _TGAStencilMode
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{
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unsigned s_wr_mask : 8;
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unsigned s_rd_mask : 8;
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unsigned s_test : 3;
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unsigned s_fail : 3;
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unsigned d_fail : 3;
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unsigned d_pass : 3;
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unsigned z_test : 3;
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unsigned z : 3;
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} TGAStencilMode;
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/*
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** Raster Op register definition
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*/
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typedef struct _TGARasterOp
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{
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unsigned opcode : 4;
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unsigned mbz : 4;
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unsigned visual : 2;
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unsigned rotate : 2;
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} TGARasterOp;
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/* ############################################################ */
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/* #### TGA bit position flags #### */
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/* ############################################################ */
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/*
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** TGA modes
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*/
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#define TGA_MODE_MODE_SIMPLE 0x00
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#define TGA_MODE_MODE_Z_SIMPLE 0x10
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#define TGA_MODE_MODE_OPA_STIP 0x01
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#define TGA_MODE_MODE_OPA_FILL 0x21
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#define TGA_MODE_MODE_TRA_STIP 0x05
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#define TGA_MODE_MODE_TRA_FILL 0x25
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#define TGA_MODE_MODE_BLK_STIP 0x0d
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#define TGA_MODE_MODE_BLK_FILL 0x2d
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#define TGA_MODE_MODE_CINT_TRA_LINE 0x0e
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#define TGA_MODE_MODE_CINT_TRA_DITH_LINE 0x2e
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#define TGA_MODE_MODE_SINT_TRA_LINE 0x5e
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#define TGA_MODE_MODE_Z_OPA_LINE 0x12
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#define TGA_MODE_MODE_Z_TRA_LINE 0x16
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#define TGA_MODE_MODE_Z_CINT_OPA_LINE 0x1a
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#define TGA_MODE_MODE_Z_CINT_OPA_DITH_LINE 0x3a
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#define TGA_MODE_MODE_Z_SINT_OPA_LINE 0x5a
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#define TGA_MODE_MODE_Z_CINT_TRA_LINE 0x1e
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#define TGA_MODE_MODE_Z_CINT_TRA_DITH_LINE 0x3e
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#define TGA_MODE_MODE_Z_SINT_TRA_LINE 0x5e
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#define TGA_MODE_MODE_COPY 0x07
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#define TGA_MODE_MODE_DMA_READ_COPY 0x17
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#define TGA_MODE_MODE_DMA_READ_COPY_DITH 0x37
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#define TGA_MODE_MODE_DMA_WRITE_COPY 0x1f
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/*
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** Source bitmap for 32-bpp TGA frame buffers.
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** Not available in 8-bpp TGA systems.
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*/
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#define TGA_MODE_VISUAL_8_PACKED 0x00
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#define TGA_MODE_VISUAL_8_UNPAKCED 0x01
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#define TGA_MODE_VISUAL_12_LOW 0x02
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#define TGA_MODE_VISUAL_12_HIGH 0x06
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#define TGA_MODE_VISUAL_24 0x03
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/*
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** rotation in mode register
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*/
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#define TGA_MODE__ROTATE_0_BYTES 0x00
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#define TGA_MODE__ROTATE_1_BYTES 0x01
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#define TGA_MODE__ROTATE_2_BYTES 0x02
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#define TGA_MODE__ROTATE_3_BYTES 0x03
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/*
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** Raster Op definitions
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*/
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#define TGA_ROP_OP_CLEAR 0
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#define TGA_ROP_OP_AND 1
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#define TGA_ROP_OP_AND_REVERSE 2
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#define TGA_ROP_OP_COPY 3
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#define TGA_ROP_OP_AND_INVERTED 4
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#define TGA_ROP_OP_NOP 5
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#define TGA_ROP_OP_XOR 6
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#define TGA_ROP_OP_OR 7
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#define TGA_ROP_OP_NOR 8
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#define TGA_ROP_OP_EQUIV 9
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#define TGA_ROP_OP_INVERT 10
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#define TGA_ROP_OP_OR_REVERSE 11
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#define TGA_ROP_OP_COPY_INVERTED 12
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#define TGA_ROP_OP_OR_INVERTED 13
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#define TGA_ROP_OP_NAND 14
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#define TGA_ROP_OP_SET 15
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/*
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** rasted op register destination bitmap
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*/
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#define TGA_ROP_VISUAL_8_PACKED 0x00
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#define TGA_ROP_VISUAL_8_UNPACKED 0x01
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#define TGA_ROP_VISUAL_12 0x02
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#define TGA_ROP_VISUAL_24 0x03
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/* ########################################################### */
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/* #### TGA Interrupts #### */
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/* ########################################################### */
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/*
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** specifics of interrupt register (assumes low to high bit ordering)
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*/
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typedef union {
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ULONG intr_reg;
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struct {
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unsigned TGA_vsync :1;
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unsigned TGA_shift_addr :1;
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unsigned TGA_dma_error :1;
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unsigned TGA_parity_error :1;
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unsigned TGA_timer :1;
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unsigned unused :11;
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unsigned TGA_enb_vsync :1;
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unsigned TGA_enb_shift_addr :1;
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unsigned TGA_enb_dma_error :1;
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unsigned TGA_enb_parity_error :1;
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unsigned TGA_enb_timer :1;
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unsigned unused1 :11;
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} intr_status;
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} TGAIntrStatus;
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typedef union _H_TIMING{
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struct {
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unsigned pixels : 9 ;
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unsigned front_porch:5;
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unsigned sync:7;
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unsigned back_porch:7;
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unsigned ignore:3;
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unsigned odd:1;
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} horizontol_setup;
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unsigned long h_setup;
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} H_TIMING;
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typedef union _V_TIMING{
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struct {
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unsigned scan_lines:11;
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unsigned front_porch:5;
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unsigned sync:6;
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unsigned back_porch:6;
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unsigned ignore:3;
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unsigned odd:1;
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} vertical_setup;
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unsigned int v_setup;
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} V_TIMING;
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