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507 lines
8.6 KiB
507 lines
8.6 KiB
//
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// Copyright (c) 1995 FirePower Systems, Inc.
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//
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// Module Name:
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// pat32.s
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//
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// Abstract:
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// This module includes asmmebler functions to be used
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// in PSIDISP.DLL display driver for PowerPro & PowerTop. These
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// functions are used for faster pattern fill operation.
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//
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// Environment:
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// User mode.
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//
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// Revision History:
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//
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//--
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//
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// Copyright (c) 1995 FirePower Systems, Inc.
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// DO NOT DISTRIBUTE without permission
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//
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// $RCSfile: pat32.s $
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// $Revision: 1.2 $
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// $Date: 1996/04/10 17:59:26 $
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// $Locker: $
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//
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//++
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//--
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#include "ladj.h"
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#include <ksppc.h>
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// __fill_pat32(pbDst, pdSrc, cbX, cy, ld, pSave)
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// pbDst -> byte addr of destination
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// pdSrc -> double word addr of fill value needed for 1st word of CB
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// cbX -> count of words to fill per scan line
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// cy -> count of scan lines
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// ld -> stride between scan lines
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// pSave -> 4 word register save area
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//
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// Optimizations:
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//
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// Special cases for "skinny" fills
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// Used 64 bit stores when possible
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// uses dcbz instruction when possible
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// Register defs
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#define pprocRet r0
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#define pbDst r3
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#define pdSrc r4
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#define pprocFirst r4 // Redefines pdSrc
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#define cbX r5
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#define pprocLast r5 // Redefines cbX
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#define t1 r5 // Redefines cbX
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#define cy r6
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#define ld r7
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#define pSave r8
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#define t r9
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#define w r10
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#define prgpproc r11
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// something funny about r13 & the debugger
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#define pdInner r15 // r14-r17 must not be used by short (<= 7 bytes) rtns
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#define cdInner r16
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#define w1 r17
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#define d f1
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#define d1 f2
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#define d2 f3
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#define d3 f4
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// Stacl Slack offset
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#define SLACK1 -4
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#define SLACK2 -8
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#define SLACK3 -12
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#define SLACK4 -16
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#define SLACK5 -20
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#define SLACK6 -24
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#define SLACK7 -28
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#define SLACK8 -32
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.text
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SPECIAL_ENTRY(__fill_pat32)
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mflr pprocRet
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//
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// Save non-volatile registers
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//
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stw r15,SLACK3(sp)
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stw r16,SLACK4(sp)
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stw r17,SLACK5(sp)
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//
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PROLOGUE_END(__fill_pat32)
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//
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bl __past_tables
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__rgpproc:
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.ualong __ret
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.ualong __ret
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.ualong __cx1
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.ualong __cx1
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.ualong __cx2M0
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.ualong __cx2M1
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.ualong __cx3M0
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.ualong __cx3M1
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.ualong __cx4M0
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.ualong __cx4M1
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.ualong __cx5M0
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.ualong __cx5M1
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.ualong __cx6M0
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.ualong __cx6M1
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.ualong __cx7M0
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.ualong __cx7M1
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__rgpprocFirst:
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.ualong __al0
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.ualong __al1
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.ualong __al2
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.ualong __al3
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.ualong __al4
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.ualong __al5
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.ualong __al6
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.ualong __al7
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__rgpprocLast:
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.ualong __last0
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.ualong __last1
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.ualong __last2
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.ualong __last3
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.ualong __last4
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.ualong __last5
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.ualong __last6
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.ualong __last7
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__past_tables:
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cmpwi cr0, cbX, 32 // Short fill?
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mflr prgpproc
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rlwinm t, cbX, 1, 26, 28
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rlwimi t, pbDst, 0, 29, 29 // (3 bits of cx) || (MOD 2 of dest word addr) || (2 bits of 0)
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lwzx t, prgpproc, t // t = dispatch table index
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mtctr cy
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mtlr t
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rlwinm t, pbDst, 0, 27, 31 // alignment in pat of 1st pixel
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lwzx w, pdSrc, t // 1st pixel to store
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bltlr // Dispatch short fills
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lfd d, 0(pdSrc) // load up inner loop store values
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add w1, pbDst, cbX
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lfd d1, 8(pdSrc)
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subi w1, w1, 4
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lfd d2, 16(pdSrc)
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rlwinm w1, w1, 0, 27, 31 // alignment in pat of last pixel
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lwzx w1, pdSrc, w1 // last pixel to store
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rlwinm t, pbDst, 0, 27, 29 // (MOD 8 of dest word addr) || ( 2 bits of 0)
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lfd d3, 24(pdSrc)
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addi t, t, __rgpprocFirst-__rgpproc
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lwzx pprocFirst, prgpproc, t // code addr for CB alignment
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subfic t, pbDst, 32
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mtlr pprocFirst
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rlwinm t, t, 0, 27, 31
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add pdInner, pbDst, t // addr first in CB
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sub t, cbX, t // Remaining count after alignment
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rlwinm pprocLast, t, 0, 27, 29 // (MOD 8 of rem word count) || ( 2 bits of 0)
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addi pprocLast, pprocLast, __rgpprocLast-__rgpproc
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lwzx pprocLast, prgpproc, pprocLast // code addr for final 0-7 pixel
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srwi cdInner, t, 3 // count of full d/w
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blr // Dispatch to First/Inner/Last
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//
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// Short cases, no need to restore non-volatile registers
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//
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__cx1: mtlr pprocRet
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__cx1Loop:
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stw w, 0(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx1Loop
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blr
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__cx2M0:mtlr pprocRet
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lfdx d, pdSrc, t
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__cx2M0Loop:
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stfd d, 0(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx2M0Loop
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blr
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__cx2M1:mtlr pprocRet
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addi t, t, 4
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rlwinm t, t, 0, 27, 31
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lwzx t, pdSrc, t
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__cx2M1Loop:
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stw w, 0(pbDst)
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stw t, 4(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx2M1Loop
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blr
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__cx3M0:mtlr pprocRet
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lfdx d, pdSrc, t
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addi t, t, 8
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rlwinm t, t, 0, 27, 31
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lwzx w, pdSrc, t
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__cx3M0Loop:
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stfd d, 0(pbDst)
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stw w, 8(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx3M0Loop
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blr
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__cx3M1:mtlr pprocRet
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addi t, t, 4
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rlwinm t, t, 0, 27, 31
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lfdx d, pdSrc, t
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__cx3M1Loop:
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stw w, 0(pbDst)
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stfd d, 4(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx3M1Loop
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blr
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__cx4M0:mtlr pprocRet
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lfdx d, pdSrc, t
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addi t, t, 8
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rlwinm t, t, 0, 27, 31
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lfdx d1, pdSrc, t
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__cx4M0Loop:
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stfd d, 0(pbDst)
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stfd d1, 8(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx4M0Loop
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blr
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__cx4M1:mtlr pprocRet
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addi t, t, 4
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rlwinm t, t, 0, 27, 31
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lfdx d, pdSrc, t
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addi t, t, 8
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rlwinm t, t, 0, 27, 31
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lwzx t, pdSrc, t
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__cx4M1Loop:
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stw w, 0(pbDst)
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stfd d, 4(pbDst)
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stw t, 12(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx4M1Loop
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blr
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__cx5M0:mtlr pprocRet
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lfdx d, pdSrc, t
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addi t, t, 8
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rlwinm t, t, 0, 27, 31
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lfdx d1, pdSrc, t
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addi t, t, 8
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rlwinm t, t, 0, 27, 31
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lwzx w, pdSrc, t
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__cx5M0Loop:
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stfd d, 0(pbDst)
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stfd d1, 8(pbDst)
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stw w, 16(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx5M0Loop
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blr
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__cx5M1:mtlr pprocRet
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addi t, t, 4
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rlwinm t, t, 0, 27, 31
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lfdx d, pdSrc, t
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addi t, t, 8
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rlwinm t, t, 0, 27, 31
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lfdx d1, pdSrc, t
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__cx5M1Loop:
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stw w, 0(pbDst)
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stfd d, 4(pbDst)
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stfd d1, 12(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx5M1Loop
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blr
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__cx6M0:mtlr pprocRet
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lfdx d, pdSrc, t
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addi t, t, 8
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rlwinm t, t, 0, 27, 31
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lfdx d1, pdSrc, t
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addi t, t, 8
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rlwinm t, t, 0, 27, 31
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lfdx d2, pdSrc, t
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__cx6M0Loop:
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stfd d, 0(pbDst)
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stfd d1, 8(pbDst)
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stfd d2, 16(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx6M0Loop
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blr
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__cx6M1:mtlr pprocRet
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addi t, t, 4
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rlwinm t, t, 0, 27, 31
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lfdx d, pdSrc, t
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addi t, t, 8
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rlwinm t, t, 0, 27, 31
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lfdx d1, pdSrc, t
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addi t, t, 8
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rlwinm t, t, 0, 27, 31
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lwzx t, pdSrc, t
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__cx6M1Loop:
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stw w, 0(pbDst)
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stfd d, 4(pbDst)
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stfd d1, 12(pbDst)
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stw t, 20(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx6M1Loop
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blr
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__cx7M0:mtlr pprocRet
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lfdx d, pdSrc, t
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addi t, t, 8
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rlwinm t, t, 0, 27, 31
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lfdx d1, pdSrc, t
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addi t, t, 8
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rlwinm t, t, 0, 27, 31
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lfdx d2, pdSrc, t
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addi t, t, 8
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rlwinm t, t, 0, 27, 31
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lwzx w, pdSrc, t
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__cx7M0Loop:
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stfd d, 0(pbDst)
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stfd d1, 8(pbDst)
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stfd d2, 16(pbDst)
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stw w, 24(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx7M0Loop
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blr
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__cx7M1:mtlr pprocRet
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addi t, t, 4
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rlwinm t, t, 0, 27, 31
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lfdx d, pdSrc, t
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addi t, t, 8
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rlwinm t, t, 0, 27, 31
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lfdx d1, pdSrc, t
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addi t, t, 8
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rlwinm t, t, 0, 27, 31
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lfdx d2, pdSrc, t
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__cx7M1Loop:
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stw w, 0(pbDst)
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stfd d, 4(pbDst)
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stfd d1, 12(pbDst)
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stfd d2, 20(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx7M1Loop
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blr
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//
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// >= 8 long initial alignment
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//
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__al1:
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addi pdInner, pbDst, 7*4
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stw w, 0(pbDst)
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stfd d1, 4(pbDst)
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stfd d2, 12(pbDst)
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stfd d3, 20(pbDst)
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b __inner
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__al2:
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addi pdInner, pbDst, 6*4
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stfd d1, 0(pbDst)
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stfd d2, 8(pbDst)
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stfd d3, 16(pbDst)
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b __inner
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__al3:
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addi pdInner, pbDst, 5*4
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stw w, 0(pbDst)
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stfd d2, 4(pbDst)
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stfd d3, 12(pbDst)
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b __inner
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__al4:
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addi pdInner, pbDst, 4*4
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stfd d2, 0(pbDst)
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stfd d3, 8(pbDst)
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b __inner
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__al5:
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addi pdInner, pbDst, 3*4
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stw w, 0(pbDst)
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stfd d3, 4(pbDst)
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b __inner
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__al6:
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addi pdInner, pbDst, 2*4
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stfd d3, 0(pbDst)
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b __inner
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__al7:
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addi pdInner, pbDst, 1*4
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stw w, 0(pbDst)
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b __inner
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// Inner loop
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__al0:
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addi pdInner, pbDst, 0
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__inner:
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mtlr pprocLast
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subic. t, cdInner, 3
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blelr
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__innerLoop:
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#if USE_DCBZ
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dcbz 0, pdInner
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#endif
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subic. t, t, 4
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addi pdInner, pdInner, 32
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stfd d, -32(pdInner)
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stfd d1, -24(pdInner)
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stfd d2, -16(pdInner)
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stfd d3, -8(pdInner)
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bgt __innerLoop
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blr
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// Last piece & loop control
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__last0:mtlr pprocFirst
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add pbDst, pbDst, ld
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bdnzlr
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b __ret
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__last1:mtlr pprocFirst
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stw w1, 0(pdInner)
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add pbDst, pbDst, ld
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bdnzlr
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b __ret
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__last2:mtlr pprocFirst
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stfd d, 0(pdInner)
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add pbDst, pbDst, ld
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bdnzlr
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b __ret
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__last3:mtlr pprocFirst
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stfd d, 0(pdInner)
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stw w1, 8(pdInner)
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add pbDst, pbDst, ld
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bdnzlr
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b __ret
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__last4:mtlr pprocFirst
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stfd d, 0(pdInner)
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stfd d1, 8(pdInner)
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add pbDst, pbDst, ld
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bdnzlr
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b __ret
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__last5:mtlr pprocFirst
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stfd d, 0(pdInner)
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stfd d1, 8(pdInner)
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stw w1, 16(pdInner)
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add pbDst, pbDst, ld
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bdnzlr
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b __ret
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__last6:mtlr pprocFirst
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stfd d, 0(pdInner)
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stfd d1, 8(pdInner)
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stfd d2, 16(pdInner)
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add pbDst, pbDst, ld
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bdnzlr
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b __ret
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__last7:mtlr pprocFirst
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stfd d, 0(pdInner)
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stfd d1, 8(pdInner)
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stfd d2, 16(pdInner)
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stw w1, 24(pdInner)
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add pbDst, pbDst, ld
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bdnzlr
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//
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__ret: mtlr pprocRet
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//
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// Restore non-volatile registers
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//
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lwz r15,SLACK3(sp)
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lwz r16,SLACK4(sp)
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lwz r17,SLACK5(sp)
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//
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SPECIAL_EXIT(__fill_pat32)
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