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1205 lines
20 KiB
1205 lines
20 KiB
//
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// Copyright (c) 1995 FirePower Systems, Inc.
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//
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// Module Name:
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// pat8.s
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//
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// Abstract:
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// This module includes asmmebler functions to be used
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// in PSIDISP.DLL display driver for PowerPro & PowerTop. These
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// functions are used for faster pattern fill operation.
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//
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// Environment:
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// User mode.
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//
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// Revision History:
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//
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//--
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//
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// Copyright (c) 1995 FirePower Systems, Inc.
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// DO NOT DISTRIBUTE without permission
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//
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// $RCSfile: pat8.s $
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// $Revision: 1.2 $
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// $Date: 1996/04/10 17:59:16 $
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// $Locker: $
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//
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//++
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//--
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#include "ladj.h"
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#include <ksppc.h>
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// __fill_pat8(pbDst, pdSrc, cbX, cy, ld, pSave)
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// pbDst -> byte addr of destination
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// pdSrc -> double word addr of fill value
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// cbX -> count of bytes to fill per scan line
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// cy -> count of scan lines
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// ld -> stride between scan lines
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// pSave -> 4 word register save area
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//
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// Optimizations:
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//
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// Special cases for "skinny" fills
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// Used 64 bit stores when possible
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// uses dcbz instruction when possible
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// Register defs
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#define pprocRet r0
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#define pbDst r3
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#define pdSrc r4
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#define pprocFirst r4 // Redefines pdSrc
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#define cbX r5
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#define pprocLast r5 // Redefines cbX
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#define t1 r5 // Redefines cbX
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#define cy r6
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#define ld r7
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#define pSave r8
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#define t r9
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#define w r10
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#define prgpproc r11
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#define t2 r11 // Redefines prgpproc
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// something funny about r13 & the debugger
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#define pprocInner r14 // r14-r17 must not be used by short (<= 7 bytes) rtns
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#define pdInner r15
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#define cdInner r16
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#define w1 r17
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#define d f1
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// Stacl Slack offset
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#define SLACK1 -4
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#define SLACK2 -8
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#define SLACK3 -12
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#define SLACK4 -16
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#define SLACK5 -20
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#define SLACK6 -24
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#define SLACK7 -28
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#define SLACK8 -32
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.text
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SPECIAL_ENTRY(__fill_pat8)
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mflr pprocRet
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//
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// Save non-volatile registers
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//
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stw r14,SLACK2(sp)
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stw r15,SLACK3(sp)
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stw r16,SLACK4(sp)
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stw r17,SLACK5(sp)
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//
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PROLOGUE_END(__fill_pat8)
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//
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bl __past_tables
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__rgpproc:
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.ualong __ret
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.ualong __ret
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.ualong __ret
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.ualong __ret
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.ualong __cx1M0
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.ualong __cx1M1
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.ualong __cx1M2
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.ualong __cx1M3
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.ualong __cx2M0
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.ualong __cx2M1
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.ualong __cx2M2
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.ualong __cx2M3
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.ualong __cx3M0
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.ualong __cx3M1
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.ualong __cx3M2
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.ualong __cx3M3
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.ualong __cx4M0
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.ualong __cx4M1
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.ualong __cx4M2
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.ualong __cx4M3
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.ualong __cx5M0
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.ualong __cx5M1
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.ualong __cx5M2
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.ualong __cx5M3
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.ualong __cx6M0
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.ualong __cx6M1
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.ualong __cx6M2
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.ualong __cx6M3
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.ualong __cx7M0
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.ualong __cx7M1
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.ualong __cx7M2
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.ualong __cx7M3
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__rgpprocFirst:
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.ualong __al0
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.ualong __al1
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.ualong __al2
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.ualong __al3
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.ualong __al4
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.ualong __al5
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.ualong __al6
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.ualong __al7
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__rgpprocLast:
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.ualong __last0
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.ualong __last1
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.ualong __last2
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.ualong __last3
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.ualong __last4
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.ualong __last5
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.ualong __last6
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.ualong __last7
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__rgpprocInnerLt64:
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.ualong __i0
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.ualong __i0
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.ualong __i0
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.ualong __i0
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.ualong __i1
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.ualong __i1
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.ualong __i1
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.ualong __i1
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.ualong __i2
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.ualong __i2
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.ualong __i2
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.ualong __i2
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.ualong __i3
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.ualong __i3
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.ualong __i3
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.ualong __i3
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.ualong __i4M0
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.ualong __i4M1
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.ualong __i4M1
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.ualong __i4M1
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.ualong __i5M0
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.ualong __i5M1
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.ualong __i5M1
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.ualong __i5M3
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.ualong __i6M0
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.ualong __i6M1
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.ualong __i6M2
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.ualong __i6M3
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.ualong __i7M0
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.ualong __i7M1
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.ualong __i7M2
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.ualong __i7M3
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__rgpprocInnerGe64:
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.ualong __iX00 // 0 doubles before block, 0 after
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.ualong __iX10 // 1 doubles before block, 1 after
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.ualong __iX20 // 2 doubles before block, 2 after
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.ualong __iX30 // 3 doubles before block, 3 after
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.ualong __iX01 // 0 doubles before block, 1 after
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.ualong __iX11
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.ualong __iX21
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.ualong __iX31
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.ualong __iX02
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.ualong __iX12
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.ualong __iX22
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.ualong __iX32
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.ualong __iX03
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.ualong __iX13
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.ualong __iX23
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.ualong __iX33
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__past_tables:
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cmpwi cr0, cbX, 8 // Short fill?
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mflr prgpproc
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rlwinm t, cbX, 4, 25, 27
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insrwi t, pbDst, 2, 28 // (3 bits of cbX) || (MOD 4 of dest addr) || (2 bits of 0)
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lwzx t, prgpproc, t // t = dispatch table index
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lfd d, 0(pdSrc)
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mtlr t
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mtctr cy
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lwz w, 0(pdSrc)
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bltlr // Dispatch short fills
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lwz w1, 4(pdSrc)
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rlwinm t, pbDst, 2, 27, 29 // (MOD 8 of dest addr) || ( 2 bits of 0)
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addi t, t, __rgpprocFirst-__rgpproc
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lwzx pprocFirst, prgpproc, t // code addr for double word alignment
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andi. t, pbDst, 0x7
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mtlr pprocFirst
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subfic t, t, 8
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add pdInner, pbDst, t // addr first d/w
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sub t, cbX, t // Remaining count after alignment
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cmpwi cr0, t, 64
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rlwinm pprocLast, t, 2, 27, 29 // (MOD 8 of remaining count) || ( 2 bits of 0)
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addi pprocLast, pprocLast, __rgpprocLast-__rgpproc
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lwzx pprocLast, prgpproc, pprocLast // code addr for final 0-7 bytes
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rlwinm pprocInner, pdInner, 32-3+2, 28, 29 // MOD 32 dest addr >> 3
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srwi cdInner, t, 3 // count of full d/w
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blt __lt64
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srwi t, pprocInner, 2
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add t, cdInner, t // low 2 bits are MOD 4 d/w count after cache block alignment
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insrwi pprocInner, t, 2, 26 // (MOD 4 of remaining d/w count) || (MOD 32 dest addr >> 3) || ( 2 bits 0)
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addi pprocInner, pprocInner, __rgpprocInnerGe64-__rgpproc
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lwzx pprocInner, prgpproc, pprocInner // code addr for inner d/w stores
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blr // Dispatch to First/Inner/Last
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__lt64:
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insrwi pprocInner, cdInner, 3, 25 // (count of d/w) || (MOD 32 dest addr >> 3) || (2 bits of 0)
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addi pprocInner, pprocInner, __rgpprocInnerLt64-__rgpproc
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lwzx pprocInner, prgpproc, pprocInner // code addr for inner d/w stores
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blr // Dispatch to First/Inner/Last
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//
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// Short cases, no need to restore non-volatile registers
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//
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__cx1M0:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29 // short loops only 4 cases
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lbz w, 0(pdSrc) // so step to 2nd 4 in pat if needed
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__cx1M0Loop:
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stb w, 0(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx1M0Loop
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blr
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__cx1M1:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lbz w, 1(pdSrc)
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__cx1M1Loop:
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stb w, 0(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx1M1Loop
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blr
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__cx1M2:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lbz w, 2(pdSrc)
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__cx1M2Loop:
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stb w, 0(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx1M2Loop
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blr
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__cx1M3:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lbz w, 3(pdSrc)
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__cx1M3Loop:
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stb w, 0(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx1M3Loop
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blr
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__cx2M0:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lhz w, 0(pdSrc)
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__cx2M0Loop:
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sth w, 0(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx2M0Loop
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blr
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__cx2M1:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lbz w, 1(pdSrc)
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lbz t, 2(pdSrc)
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__cx2M1Loop:
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stb w, 0(pbDst)
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stb t, 1(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx2M1Loop
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blr
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__cx2M2:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lhz w, 2(pdSrc)
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__cx2M2Loop:
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sth w, 0(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx2M2Loop
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blr
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__cx2M3:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lbz w, 3(pdSrc)
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xori pdSrc, pdSrc, 4
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lbz t1, 0(pdSrc)
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__cx2M3Loop:
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stb w, 0(pbDst)
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stb t1, 1(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx2M3Loop
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blr
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__cx3M0:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lhz w, 0(pdSrc)
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lbz t, 2(pdSrc)
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__cx3M0Loop:
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sth w, 0(pbDst)
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stb t, 2(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx3M0Loop
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blr
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__cx3M1:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lbz w, 1(pdSrc)
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lhz t, 2(pdSrc)
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__cx3M1Loop:
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stb w, 0(pbDst)
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sth t, 1(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx3M1Loop
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blr
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__cx3M2:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lhz w, 2(pdSrc)
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xori pdSrc, pdSrc, 4
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lbz t1, 0(pdSrc)
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__cx3M2Loop:
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sth w, 0(pbDst)
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stb t1, 2(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx3M2Loop
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blr
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__cx3M3:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lbz w, 3(pdSrc)
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xori pdSrc, pdSrc, 4
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lhz t1, 0(pdSrc)
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__cx3M3Loop:
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stb w, 0(pbDst)
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sth t1, 1(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx3M3Loop
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blr
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__cx4M0:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lwz w, 0(pdSrc)
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__cx4M0Loop:
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stw w, 0(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx4M0Loop
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blr
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__cx4M1:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lbz w, 1(pdSrc)
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lhz t, 2(pdSrc)
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xori pdSrc, pdSrc, 4
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lbz t1, 0(pdSrc)
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__cx4M1Loop:
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stb w, 0(pbDst)
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sth t, 1(pbDst)
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stb t1, 3(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx4M1Loop
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blr
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__cx4M2:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lhz w, 2(pdSrc)
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xori pdSrc, pdSrc, 4
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lhz t, 0(pdSrc)
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__cx4M2Loop:
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sth w, 0(pbDst)
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sth t, 2(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx4M2Loop
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blr
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__cx4M3:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lbz w, 3(pdSrc)
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xori pdSrc, pdSrc, 4
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lhz t, 0(pdSrc)
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lbz t1, 2(pdSrc)
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__cx4M3Loop:
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stb w, 0(pbDst)
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sth t, 1(pbDst)
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stb t1, 3(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx4M3Loop
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blr
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__cx5M0:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lwz w, 0(pdSrc)
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xori pdSrc, pdSrc, 4
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lbz t, 0(pdSrc)
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__cx5M0Loop:
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stw w, 0(pbDst)
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stb t, 4(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx5M0Loop
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blr
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__cx5M1:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lbz w, 1(pdSrc)
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lhz t, 2(pdSrc)
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xori pdSrc, pdSrc, 4
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lhz t1, 0(pdSrc)
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__cx5M1Loop:
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stb w, 0(pbDst)
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sth t, 1(pbDst)
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sth t1, 3(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx5M1Loop
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blr
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__cx5M2:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lhz w, 2(pdSrc)
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xori pdSrc, pdSrc, 4
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lhz t, 0(pdSrc)
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lbz t1, 2(pdSrc)
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__cx5M2Loop:
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sth w, 0(pbDst)
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sth t, 2(pbDst)
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stb t1, 4(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx5M2Loop
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blr
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__cx5M3:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lbz w, 3(pdSrc)
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xori pdSrc, pdSrc, 4
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lwz t, 0(pdSrc)
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__cx5M3Loop:
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stb w, 0(pbDst)
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stw t, 1(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx5M3Loop
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blr
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__cx6M0:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lwz w, 0(pdSrc)
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xori pdSrc, pdSrc, 4
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lhz t, 0(pdSrc)
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__cx6M0Loop:
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stw w, 0(pbDst)
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sth t, 4(pbDst)
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add pbDst, pbDst, ld
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bdnz __cx6M0Loop
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blr
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__cx6M1:mtlr pprocRet
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rlwimi pdSrc, pbDst, 0, 29, 29
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lbz w, 1(pdSrc)
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lhz t, 2(pdSrc)
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xori pdSrc, pdSrc, 4
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lhz t1, 0(pdSrc)
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lbz t2, 2(pdSrc)
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__cx6M1Loop:
|
|
stb w, 0(pbDst)
|
|
sth t, 1(pbDst)
|
|
sth t1, 3(pbDst)
|
|
stb t2, 5(pbDst)
|
|
add pbDst, pbDst, ld
|
|
bdnz __cx6M1Loop
|
|
blr
|
|
|
|
__cx6M2:mtlr pprocRet
|
|
rlwimi pdSrc, pbDst, 0, 29, 29
|
|
lhz w, 2(pdSrc)
|
|
xori pdSrc, pdSrc, 4
|
|
lwz t, 0(pdSrc)
|
|
__cx6M2Loop:
|
|
sth w, 0(pbDst)
|
|
stw t, 2(pbDst)
|
|
add pbDst, pbDst, ld
|
|
bdnz __cx6M2Loop
|
|
blr
|
|
|
|
__cx6M3:mtlr pprocRet
|
|
rlwimi pdSrc, pbDst, 0, 29, 29
|
|
lbz t1, 0(pdSrc)
|
|
lbz w, 3(pdSrc)
|
|
xori pdSrc, pdSrc, 4
|
|
lwz t, 0(pdSrc)
|
|
__cx6M3Loop:
|
|
stb w, 0(pbDst)
|
|
stw t, 1(pbDst)
|
|
stb t1, 5(pbDst)
|
|
add pbDst, pbDst, ld
|
|
bdnz __cx6M3Loop
|
|
blr
|
|
|
|
__cx7M0:mtlr pprocRet
|
|
rlwimi pdSrc, pbDst, 0, 29, 29
|
|
lwz w, 0(pdSrc)
|
|
xori pdSrc, pdSrc, 4
|
|
lhz t, 0(pdSrc)
|
|
lbz t1, 2(pdSrc)
|
|
__cx7M0Loop:
|
|
stw w, 0(pbDst)
|
|
sth t, 4(pbDst)
|
|
stb t1, 6(pbDst)
|
|
add pbDst, pbDst, ld
|
|
bdnz __cx7M0Loop
|
|
blr
|
|
|
|
__cx7M1:mtlr pprocRet
|
|
rlwimi pdSrc, pbDst, 0, 29, 29
|
|
lbz w, 1(pdSrc)
|
|
lhz t, 2(pdSrc)
|
|
xori pdSrc, pdSrc, 4
|
|
lwz t1, 0(pdSrc)
|
|
__cx7M1Loop:
|
|
stb w, 0(pbDst)
|
|
sth t, 1(pbDst)
|
|
stw t1, 3(pbDst)
|
|
add pbDst, pbDst, ld
|
|
bdnz __cx7M1Loop
|
|
blr
|
|
|
|
__cx7M2:mtlr pprocRet
|
|
rlwimi pdSrc, pbDst, 0, 29, 29
|
|
lbz t1, 0(pdSrc)
|
|
lhz w, 2(pdSrc)
|
|
xori pdSrc, pdSrc, 4
|
|
lwz t, 0(pdSrc)
|
|
__cx7M2Loop:
|
|
sth w, 0(pbDst)
|
|
stw t, 2(pbDst)
|
|
stb t1, 6(pbDst)
|
|
add pbDst, pbDst, ld
|
|
bdnz __cx7M2Loop
|
|
blr
|
|
|
|
__cx7M3:mtlr pprocRet
|
|
rlwimi pdSrc, pbDst, 0, 29, 29
|
|
lhz t1, 0(pdSrc)
|
|
lbz w, 3(pdSrc)
|
|
xori pdSrc, pdSrc, 4
|
|
lwz t, 0(pdSrc)
|
|
__cx7M3Loop:
|
|
stb w, 0(pbDst)
|
|
stw t, 1(pbDst)
|
|
sth t1, 5(pbDst)
|
|
add pbDst, pbDst, ld
|
|
bdnz __cx7M3Loop
|
|
blr
|
|
//
|
|
// >= 8 long initial alignment
|
|
//
|
|
__al0: mtlr pprocInner
|
|
addi pdInner, pbDst, 8
|
|
stfd d, 0(pbDst)
|
|
blr
|
|
|
|
__al1: mtlr pprocInner
|
|
addi pdInner, pbDst, 7
|
|
srwi t, w, 8
|
|
stb t, 0(pbDst)
|
|
srwi t, w, 16
|
|
sth t, 1(pbDst)
|
|
stw w1, 3(pbDst)
|
|
blr
|
|
|
|
__al2: mtlr pprocInner
|
|
addi pdInner, pbDst, 6
|
|
srwi t, w, 16
|
|
sth t, 0(pbDst)
|
|
stw w1, 2(pbDst)
|
|
blr
|
|
|
|
__al3: mtlr pprocInner
|
|
addi pdInner, pbDst, 5
|
|
srwi t, w, 24
|
|
stb t, 0(pbDst)
|
|
stw w1, 1(pbDst)
|
|
blr
|
|
|
|
__al4: mtlr pprocInner
|
|
addi pdInner, pbDst, 4
|
|
stw w1, 0(pbDst)
|
|
blr
|
|
|
|
__al5: mtlr pprocInner
|
|
addi pdInner, pbDst, 3
|
|
srwi t, w1, 8
|
|
stb t, 0(pbDst)
|
|
srwi t, w1, 16
|
|
sth t, 1(pbDst)
|
|
blr
|
|
|
|
__al6: mtlr pprocInner
|
|
addi pdInner, pbDst, 2
|
|
srwi t, w1, 16
|
|
sth t, 0(pbDst)
|
|
blr
|
|
|
|
__al7: mtlr pprocInner
|
|
addi pdInner, pbDst, 1
|
|
srwi t, w1, 24
|
|
stb t, 0(pbDst)
|
|
blr
|
|
|
|
// Multiple of 8 loops for < 8 doubles, exit with pdInner AT last d/w
|
|
|
|
__i0: mtlr pprocLast
|
|
subi pdInner, pdInner, 8
|
|
blr
|
|
|
|
__i1: mtlr pprocLast
|
|
stfdu d, 0(pdInner)
|
|
blr
|
|
|
|
__i2: mtlr pprocLast
|
|
stfd d, 0(pdInner)
|
|
stfdu d, 8(pdInner)
|
|
blr
|
|
|
|
__i3: mtlr pprocLast
|
|
stfd d, 0(pdInner)
|
|
stfd d, 8(pdInner)
|
|
stfdu d, 16(pdInner)
|
|
blr
|
|
|
|
__i4M0:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
mtlr pprocLast
|
|
stfd d, 0(pdInner)
|
|
stfd d, 8(pdInner)
|
|
stfd d, 16(pdInner)
|
|
stfdu d, 24(pdInner)
|
|
blr
|
|
|
|
__i4M1: mtlr pprocLast
|
|
stfd d, 0(pdInner)
|
|
stfd d, 8(pdInner)
|
|
stfd d, 16(pdInner)
|
|
stfdu d, 24(pdInner)
|
|
blr
|
|
|
|
__i5M0:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
mtlr pprocLast
|
|
stfd d, 0(pdInner)
|
|
stfd d, 8(pdInner)
|
|
stfd d, 16(pdInner)
|
|
stfd d, 24(pdInner)
|
|
stfdu d, 32(pdInner)
|
|
blr
|
|
|
|
__i5M1: mtlr pprocLast
|
|
stfd d, 0(pdInner)
|
|
stfd d, 8(pdInner)
|
|
stfd d, 16(pdInner)
|
|
stfd d, 24(pdInner)
|
|
stfdu d, 32(pdInner)
|
|
blr
|
|
|
|
__i5M3:
|
|
addi pdInner, pdInner, 8
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
mtlr pprocLast
|
|
stfd d, -8(pdInner)
|
|
stfd d, 0(pdInner)
|
|
stfd d, 8(pdInner)
|
|
stfd d, 16(pdInner)
|
|
stfdu d, 24(pdInner)
|
|
blr
|
|
|
|
__i6M0:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
__i6M1: mtlr pprocLast
|
|
stfd d, 0(pdInner)
|
|
stfd d, 8(pdInner)
|
|
stfd d, 16(pdInner)
|
|
stfd d, 24(pdInner)
|
|
stfd d, 32(pdInner)
|
|
stfdu d, 40(pdInner)
|
|
blr
|
|
|
|
__i6M2:
|
|
addi pdInner, pdInner, 16
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
mtlr pprocLast
|
|
stfd d, -16(pdInner)
|
|
stfd d, -8(pdInner)
|
|
stfd d, 0(pdInner)
|
|
stfd d, 8(pdInner)
|
|
stfd d, 16(pdInner)
|
|
stfdu d, 24(pdInner)
|
|
blr
|
|
|
|
__i6M3:
|
|
addi pdInner, pdInner, 8
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
mtlr pprocLast
|
|
stfd d, -8(pdInner)
|
|
stfd d, 0(pdInner)
|
|
stfd d, 8(pdInner)
|
|
stfd d, 16(pdInner)
|
|
stfd d, 24(pdInner)
|
|
stfdu d, 32(pdInner)
|
|
blr
|
|
|
|
__i7M0:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
mtlr pprocLast
|
|
stfd d, 0(pdInner)
|
|
stfd d, 8(pdInner)
|
|
stfd d, 16(pdInner)
|
|
stfd d, 24(pdInner)
|
|
stfd d, 32(pdInner)
|
|
stfd d, 40(pdInner)
|
|
stfdu d, 48(pdInner)
|
|
blr
|
|
|
|
__i7M1:
|
|
addi pdInner, pdInner, 24
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
mtlr pprocLast
|
|
stfd d, -24(pdInner)
|
|
stfd d, -16(pdInner)
|
|
stfd d, -8(pdInner)
|
|
stfd d, 0(pdInner)
|
|
stfd d, 8(pdInner)
|
|
stfd d, 16(pdInner)
|
|
stfdu d, 24(pdInner)
|
|
blr
|
|
|
|
__i7M2:
|
|
addi pdInner, pdInner, 16
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
mtlr pprocLast
|
|
stfd d, -16(pdInner)
|
|
stfd d, -8(pdInner)
|
|
stfd d, 0(pdInner)
|
|
stfd d, 8(pdInner)
|
|
stfd d, 16(pdInner)
|
|
stfd d, 24(pdInner)
|
|
stfdu d, 32(pdInner)
|
|
blr
|
|
|
|
__i7M3:
|
|
addi pdInner, pdInner, 8
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
mtlr pprocLast
|
|
stfd d, -8(pdInner)
|
|
stfd d, 0(pdInner)
|
|
stfd d, 8(pdInner)
|
|
stfd d, 16(pdInner)
|
|
stfd d, 24(pdInner)
|
|
stfd d, 32(pdInner)
|
|
stfdu d, 40(pdInner)
|
|
blr
|
|
|
|
// "General" inner loops, exit with pdInner pointing AT last double stored
|
|
|
|
__iX00: mtlr pprocLast
|
|
subi t, cdInner, 3
|
|
__iX00Loop:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
subic. t, t, 4
|
|
addi pdInner, pdInner, 32
|
|
stfd d, -32(pdInner)
|
|
stfd d, -24(pdInner)
|
|
stfd d, -16(pdInner)
|
|
stfd d, -8(pdInner)
|
|
bgt __iX00Loop
|
|
subi pdInner, pdInner, 8
|
|
blr
|
|
|
|
__iX01: mtlr pprocLast
|
|
subi t, cdInner, 3
|
|
__iX01Loop:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
subic. t, t, 4
|
|
addi pdInner, pdInner, 32
|
|
stfd d, -32(pdInner)
|
|
stfd d, -24(pdInner)
|
|
stfd d, -16(pdInner)
|
|
stfd d, -8(pdInner)
|
|
bgt __iX01Loop
|
|
stfd d, 0(pdInner)
|
|
blr
|
|
|
|
__iX02: mtlr pprocLast
|
|
subi t, cdInner, 3
|
|
__iX02Loop:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
subic. t, t, 4
|
|
addi pdInner, pdInner, 32
|
|
stfd d, -32(pdInner)
|
|
stfd d, -24(pdInner)
|
|
stfd d, -16(pdInner)
|
|
stfd d, -8(pdInner)
|
|
bgt __iX02Loop
|
|
stfd d, 0(pdInner)
|
|
stfdu d, 8(pdInner)
|
|
blr
|
|
|
|
__iX03: mtlr pprocLast
|
|
subi t, cdInner, 3
|
|
__iX03Loop:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
subic. t, t, 4
|
|
addi pdInner, pdInner, 32
|
|
stfd d, -32(pdInner)
|
|
stfd d, -24(pdInner)
|
|
stfd d, -16(pdInner)
|
|
stfd d, -8(pdInner)
|
|
bgt __iX03Loop
|
|
stfd d, 0(pdInner)
|
|
stfd d, 8(pdInner)
|
|
stfdu d, 16(pdInner)
|
|
blr
|
|
|
|
__iX10: stfd d, 0(pdInner)
|
|
mtlr pprocLast
|
|
stfd d, 8(pdInner)
|
|
addi pdInner, pdInner, 24
|
|
stfd d, -8(pdInner)
|
|
subi t, cdInner, 6
|
|
__iX10Loop:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
subic. t, t, 4
|
|
addi pdInner, pdInner, 32
|
|
stfd d, -32(pdInner)
|
|
stfd d, -24(pdInner)
|
|
stfd d, -16(pdInner)
|
|
stfd d, -8(pdInner)
|
|
bgt __iX10Loop
|
|
subi pdInner, pdInner, 8
|
|
blr
|
|
|
|
__iX11: stfd d, 0(pdInner)
|
|
mtlr pprocLast
|
|
stfd d, 8(pdInner)
|
|
addi pdInner, pdInner, 24
|
|
stfd d, -8(pdInner)
|
|
subi t, cdInner, 6
|
|
__iX11Loop:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
subic. t, t, 4
|
|
addi pdInner, pdInner, 32
|
|
stfd d, -32(pdInner)
|
|
stfd d, -24(pdInner)
|
|
stfd d, -16(pdInner)
|
|
stfd d, -8(pdInner)
|
|
bgt __iX11Loop
|
|
stfd d, 0(pdInner)
|
|
blr
|
|
|
|
__iX12: stfd d, 0(pdInner)
|
|
mtlr pprocLast
|
|
stfd d, 8(pdInner)
|
|
addi pdInner, pdInner, 24
|
|
stfd d, -8(pdInner)
|
|
subi t, cdInner, 6
|
|
__iX12Loop:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
subic. t, t, 4
|
|
addi pdInner, pdInner, 32
|
|
stfd d, -32(pdInner)
|
|
stfd d, -24(pdInner)
|
|
stfd d, -16(pdInner)
|
|
stfd d, -8(pdInner)
|
|
bgt __iX12Loop
|
|
stfd d, 0(pdInner)
|
|
stfdu d, 8(pdInner)
|
|
blr
|
|
|
|
__iX13: stfd d, 0(pdInner)
|
|
mtlr pprocLast
|
|
stfd d, 8(pdInner)
|
|
addi pdInner, pdInner, 24
|
|
stfd d, -8(pdInner)
|
|
subi t, cdInner, 6
|
|
__iX13Loop:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
subic. t, t, 4
|
|
addi pdInner, pdInner, 32
|
|
stfd d, -32(pdInner)
|
|
stfd d, -24(pdInner)
|
|
stfd d, -16(pdInner)
|
|
stfd d, -8(pdInner)
|
|
bgt __iX13Loop
|
|
stfd d, 0(pdInner)
|
|
stfd d, 8(pdInner)
|
|
stfdu d, 16(pdInner)
|
|
blr
|
|
|
|
__iX20: stfd d, 0(pdInner)
|
|
mtlr pprocLast
|
|
stfd d, 8(pdInner)
|
|
addi pdInner, pdInner, 16
|
|
subi t, cdInner, 5
|
|
__iX20Loop:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
subic. t, t, 4
|
|
addi pdInner, pdInner, 32
|
|
stfd d, -32(pdInner)
|
|
stfd d, -24(pdInner)
|
|
stfd d, -16(pdInner)
|
|
stfd d, -8(pdInner)
|
|
bgt __iX20Loop
|
|
subi pdInner, pdInner, 8
|
|
blr
|
|
|
|
__iX21: stfd d, 0(pdInner)
|
|
mtlr pprocLast
|
|
stfd d, 8(pdInner)
|
|
addi pdInner, pdInner, 16
|
|
subi t, cdInner, 5
|
|
__iX21Loop:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
subic. t, t, 4
|
|
addi pdInner, pdInner, 32
|
|
stfd d, -32(pdInner)
|
|
stfd d, -24(pdInner)
|
|
stfd d, -16(pdInner)
|
|
stfd d, -8(pdInner)
|
|
bgt __iX21Loop
|
|
stfd d, 0(pdInner)
|
|
blr
|
|
|
|
__iX22: stfd d, 0(pdInner)
|
|
mtlr pprocLast
|
|
stfd d, 8(pdInner)
|
|
addi pdInner, pdInner, 16
|
|
subi t, cdInner, 5
|
|
__iX22Loop:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
subic. t, t, 4
|
|
addi pdInner, pdInner, 32
|
|
stfd d, -32(pdInner)
|
|
stfd d, -24(pdInner)
|
|
stfd d, -16(pdInner)
|
|
stfd d, -8(pdInner)
|
|
bgt __iX22Loop
|
|
stfd d, 0(pdInner)
|
|
stfdu d, 8(pdInner)
|
|
blr
|
|
|
|
__iX23: stfd d, 0(pdInner)
|
|
mtlr pprocLast
|
|
stfd d, 8(pdInner)
|
|
addi pdInner, pdInner, 16
|
|
subi t, cdInner, 5
|
|
__iX23Loop:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
subic. t, t, 4
|
|
addi pdInner, pdInner, 32
|
|
stfd d, -32(pdInner)
|
|
stfd d, -24(pdInner)
|
|
stfd d, -16(pdInner)
|
|
stfd d, -8(pdInner)
|
|
bgt __iX23Loop
|
|
stfd d, 0(pdInner)
|
|
stfd d, 8(pdInner)
|
|
stfdu d, 16(pdInner)
|
|
blr
|
|
|
|
__iX30: stfd d, 0(pdInner)
|
|
mtlr pprocLast
|
|
addi pdInner, pdInner, 8
|
|
subi t, cdInner, 4
|
|
__iX30Loop:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
subic. t, t, 4
|
|
addi pdInner, pdInner, 32
|
|
stfd d, -32(pdInner)
|
|
stfd d, -24(pdInner)
|
|
stfd d, -16(pdInner)
|
|
stfd d, -8(pdInner)
|
|
bgt __iX30Loop
|
|
subi pdInner, pdInner, 8
|
|
blr
|
|
|
|
__iX31: stfd d, 0(pdInner)
|
|
mtlr pprocLast
|
|
addi pdInner, pdInner, 8
|
|
subi t, cdInner, 4
|
|
__iX31Loop:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
subic. t, t, 4
|
|
addi pdInner, pdInner, 32
|
|
stfd d, -32(pdInner)
|
|
stfd d, -24(pdInner)
|
|
stfd d, -16(pdInner)
|
|
stfd d, -8(pdInner)
|
|
bgt __iX31Loop
|
|
stfd d, 0(pdInner)
|
|
blr
|
|
|
|
__iX32: stfd d, 0(pdInner)
|
|
mtlr pprocLast
|
|
addi pdInner, pdInner, 8
|
|
subi t, cdInner, 4
|
|
__iX32Loop:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
subic. t, t, 4
|
|
addi pdInner, pdInner, 32
|
|
stfd d, -32(pdInner)
|
|
stfd d, -24(pdInner)
|
|
stfd d, -16(pdInner)
|
|
stfd d, -8(pdInner)
|
|
bgt __iX32Loop
|
|
stfd d, 0(pdInner)
|
|
stfdu d, 8(pdInner)
|
|
blr
|
|
|
|
__iX33: stfd d, 0(pdInner)
|
|
mtlr pprocLast
|
|
addi pdInner, pdInner, 8
|
|
subi t, cdInner, 4
|
|
__iX33Loop:
|
|
#if USE_DCBZ
|
|
dcbz 0, pdInner
|
|
#endif
|
|
subic. t, t, 4
|
|
addi pdInner, pdInner, 32
|
|
stfd d, -32(pdInner)
|
|
stfd d, -24(pdInner)
|
|
stfd d, -16(pdInner)
|
|
stfd d, -8(pdInner)
|
|
bgt __iX33Loop
|
|
stfd d, 0(pdInner)
|
|
stfd d, 8(pdInner)
|
|
stfdu d, 16(pdInner)
|
|
blr
|
|
|
|
// Last piece & vertical loop control
|
|
|
|
__last0:mtlr pprocFirst
|
|
add pbDst, pbDst, ld
|
|
bdnzlr
|
|
b __ret
|
|
|
|
__last1:mtlr pprocFirst
|
|
stb w, 8(pdInner)
|
|
add pbDst, pbDst, ld
|
|
bdnzlr
|
|
b __ret
|
|
|
|
__last2:mtlr pprocFirst
|
|
sth w, 8(pdInner)
|
|
add pbDst, pbDst, ld
|
|
bdnzlr
|
|
b __ret
|
|
|
|
__last3:mtlr pprocFirst
|
|
sth w, 8(pdInner)
|
|
srwi t, w, 16
|
|
stb t, 10(pdInner)
|
|
add pbDst, pbDst, ld
|
|
bdnzlr
|
|
b __ret
|
|
|
|
__last4:mtlr pprocFirst
|
|
stw w, 8(pdInner)
|
|
add pbDst, pbDst, ld
|
|
bdnzlr
|
|
b __ret
|
|
|
|
__last5:mtlr pprocFirst
|
|
stw w, 8(pdInner)
|
|
stb w1, 12(pdInner)
|
|
add pbDst, pbDst, ld
|
|
bdnzlr
|
|
b __ret
|
|
|
|
__last6:mtlr pprocFirst
|
|
stw w, 8(pdInner)
|
|
sth w1, 12(pdInner)
|
|
add pbDst, pbDst, ld
|
|
bdnzlr
|
|
b __ret
|
|
|
|
__last7:mtlr pprocFirst
|
|
stw w, 8(pdInner)
|
|
srwi t, w1, 16
|
|
sth w1, 12(pdInner)
|
|
stb t, 14(pdInner)
|
|
add pbDst, pbDst, ld
|
|
bdnzlr
|
|
//
|
|
__ret: mtlr pprocRet
|
|
//
|
|
// Restore non-volatile registers
|
|
//
|
|
lwz r14,SLACK2(sp)
|
|
lwz r15,SLACK3(sp)
|
|
lwz r16,SLACK4(sp)
|
|
lwz r17,SLACK5(sp)
|
|
//
|
|
SPECIAL_EXIT(__fill_pat8)
|