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917 lines
26 KiB
917 lines
26 KiB
#ifndef TGAPARAM_H
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#define TGAPARAM_H
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/*
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*
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* Copyright (C) 1993-1995 by
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* DIGITAL EQUIPMENT CORPORATION, Maynard, MA.
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*
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* This software is furnished under a license and may be used and copied
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* only in accordance with the terms of such license and with the inclusion
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* of the above copyright notice. This software or any other copies there-
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* of may not be provided or otherwise made available to any other person.
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* No title to and ownership of the software is hereby transferred.
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*
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* The information in this software is subject to change without notice
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* and should not be construed as a commitment by DIGITAL EQUIPMENT COR-
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* PORATION.
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*
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* DIGITAL assumes no responsibility for the use or reliability of its
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* software on equipment which is not supplied by DIGITAL.
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*
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*******************************************************************************
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*
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* Module: tgaparam.h
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*
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* Abstract: Contains many, if not all, of the 'base' TGA constants.
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* Should always be the first header file included.
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*
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* HISTORY
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*
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* 10-Sep-1993 Bob Seitsinger
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* Initial version. Plagarized from FFBPARAMS.H
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*
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* 30-Sep-1993 Barry Tannenbaum
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* Removed illegal trailing comma in definition of TGAMode
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*
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* 30-Sep-1993 Bob Seitsinger
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* Add macro to test equality of ternary and quarternary rop -
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* ROP3_ROP4_EQUAL.
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*
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* 30-Sep-1993 Bob Seitsinger
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* Add macro to validate incoming rop4 code as one we are
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* accelerating - ACCELROP.
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*
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* 30-Sep-1993 Bob Seitsinger
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* Renamed ACCELROP to be ACCEL_ROP and added NOT_ACCEL_ROP.
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*
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* 30-Sep-1993 Bob Seitsinger
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* Add some comments removed from tgamacro.h. They are more relevant
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* here.
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*
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* 01-Oct-1993 Bob Seitsinger
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* Add TGA_ROP_ROTATE_? constants. Add TGA_MODE_? constants for
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* graphics environment, z value and cap ends.
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*
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* 04-Oct-1993 Bob Seitsinger
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* Add some 'defines' from tgamacro.h. More appropriate here.
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*
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* 04-Oct-1993 Bob Seitsinger
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* Add macros to extract a rop3 from a rop3 (ROP3_FROM_ROP3) and
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* a rop3 from a rop4 (ROP3_FROM_ROP4).
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*
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* 07-Oct-1993 Bob Seitsinger
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* Delete DDXPointPtr and BoxPtr structure definitions. X'isms that
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* were originally added to clean compile FFB code. Now use Win32
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* POINTL and RECTL structures, instead.
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*
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* 08-Oct-1993 Barry Tannenbaum
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* Replaced register definitions with definitions from vars.h which was
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* included with the behavioral model. The def's from vars.h include
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* an alias which allows us to zap the register to zero easily before
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* setting fields.
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*
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* 11-Oct-1993 Bob Seitsinger
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* Added FIRSTREG_ADDRESS and FIRSTRAM_ADDRESS. Originally added by
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* Barry T. Only used with the behavioral model.
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*
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* 12-Oct-1993 Barry Tannenbaum
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* Renamed TGA mode definitions to be closer to FFB names. Added missing
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* line mode definitions.
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*
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* 19-Oct-1993 Barry Tannenbaum
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* Added offset to base address of framebuffer. The BitBlt code needs to
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* be able to access up to 7 bytes *before* the framebuffer.
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*
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* 27-Oct-1993 Bob Seitsinger
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* Add FOREGROUND_FROM_ROP4, BACKGROUND_FROM_ROP4, ROP4_FG_BG_EQUAL
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* and ROP4_FG_BG_NEQUAL macros.
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*
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* 09-Nov-1993 Bob Seitsinger
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* Make MERGECOPY, PATCOPY and PATINVERT suported ROPs.
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*
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* 10-Nov-1993 Bob Seitsinger
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* Add VALID_XLATE_TYPE() and INVALID_XLATE_TYPE() macros.
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*
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* 23-Nov-1993 Bob Seitsinger
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* Add MAKE_ROP4() macro to make a rop4 from a pair of rop3's.
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*
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* 07-Dec-1993 Bob Seitsinger
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* Move numerous macros to TGAMACRO.H, where they belong. Also, add
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* constant TGASIMPLEALIGNMENT.
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*
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* 08-Dec-1993 Bob Seitsinger
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* Add Win32 ROP constants that relate to TGA ROPs that currently have
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* no Win32 constants.
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*
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* 23-Feb-1994 Bob Seitsinger
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* Add some constants in support of DMA.
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*
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* 07-Mar-1994 Bob Seitsinger
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* Delete TGAMAINPAGEBYTES and TGAMAINPAGEMASK. Replaced by ulMainPageBytes
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* and ulMainPageBytesMask in PDEV.
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*
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* 08-Mar-1994 Bob Seitsinger
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* Modify IOCTL constants to be only *_LOCK_PAGES and *_UNLOCK_PAGES.
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* DMA pass 4.
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*
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* 16-May-1994 Bob Seitsinger
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* Add TGA_WIN32_ROP_DPna (0x00000A0A).
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*
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* 25-May-1994 Bob Seitsinger
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* Deleted the TGA_WIN32_ROP_* constants. No longer used.
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*
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* 14-Jul-1994 Bob Seitsinger
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* Modify FRAMEBUFFER_OFFSET to be FRAMEBUFFER_OFFSET_8 and
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* FRAMEBUFFER_OFFSET_24 in support of 24 plane development.
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*
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* 9-Aug-1994 Barry Tannenbaum
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* Setup for 24 plane support:
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* - TGAMODE and TGAROP now take simple ULONGs instead of structures
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* - Use default values from ppdev->ulModeTemplate & ppdev->ulRopTemplate
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*
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* 6-Oct-1994 Bob Seitsinger
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* Make FIRSTRAM_ADDRESSs 'FRAMEBUFFER_OFFSET' => 'FRAMEBUFFER_OFFSET_8'.
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* This can be changed to the '_24' version at build time, if needed.
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* This only comes into play when building for the behavioral model.
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*
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* 3-Nov-1994 Bob Seitsinger
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* Add TGA_CURSOR_BUFFER_SIZE constant and VVALID and VVALIDREG structures
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* in support of 24 plane TGA-based cursor management.
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*
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* 2-Mar-1995 Barry Tannenbaum
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* IOCTL declarations moved to tgaioctl.h
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*/
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#include "tgaioctl.h"
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/****************************************************************************
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* Parameterization of Smart Frame Buffer *
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***************************************************************************/
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/*
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The following parameters determine everything else.
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As of 1993, there is one TGA+ chip, which accepts 32 bits from the bus, has a
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64 bit interface to VRAM, and supports pixels that are 8, 12, or 32 bits deep.
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To support other possible chips, several key definitions are parameterized.
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Perhaps you can just change these parameters and everything will work. No
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guarantees, though.
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Since a single TGA+ graphics system can support multiple pixel depths
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simultaneously, some of the parameters come from the Imakefile, so that some .c
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files can be compiled up for different depth pixels. (Many files have been
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made depth-independent, so only need be compiled up once for all pixel depths.)
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The masks provided to copy mode, stipple mode, and the pixel mask register are
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always packed; one bit in the mask represents one pixel in memory.
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``Meg'' is the minimum megabytes of VRAM that the TGA can talk to, assuming
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256kx4-bit wide chips.
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** Note that TGAPIXELBITS, TGADEPTHBITS, TGASRCPIXELBITS, and TGASRCDEPTHBITS
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are usually defined using -D in the Makefile. If not, we're looking at
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depth-independent code.
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*/
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/*
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* These definitons are *ONLY* used by the software model. They specify
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* where in memory the TGA registers and virtual framebuffer are. The
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* framebuffer is mapped to the actual location in routine do_rams.
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*
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* "Why do we offset the framebuffer?" I hear you cry. We do this because
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* it's much more efficient for the BitBlt code if it can access up to 7 bytes
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* *before* the start of the frame buffer. To let it do this, we map the
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* framebuffer to the page (4096 bytes) *after* the actual start of the frame
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* buffer. This memory can be used later for off-screen storage
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*/
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#define FRAMEBUFFER_OFFSET_8 0x1000 // 4k
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#define FRAMEBUFFER_OFFSET_24 0x4000 // 16k
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#define FIRSTREG_ADDRESS 0x100000
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#define FIRSTRAM_ADDRESS 0x800000 + FRAMEBUFFER_OFFSET_8
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/*
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* TGAPIXELBITS is the physical number of bits per pixel in memory for the
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* destination drawable. 8 for packed 8-plane visuals; 32 for unpacked 8-plane
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* visuals; and 32 for 12-plane and 24-plane visuals.
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*/
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#ifndef TGAPIXELBITS
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#define TGAPIXELBITS 8
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#endif
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/*
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* TGADEPTHBITS is the logical number of bits per pixel that the TGA+ operates
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* on for the destination drawable. 8 for 8-plane visuals; 32 for 12-plane and
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* 24-plane visuals.
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*/
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#ifndef TGADEPTHBITS
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#define TGADEPTHBITS 8
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#endif
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/*
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* If TGAPIXELBITS/TGADEPTHBITS = 4, you have an unpacked 8-bit destination
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* visual. Otherwise TGAPIXELBITS/TGADEPTHBITS = 1.
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*/
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/*
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* TGASRCPIXELBITS is the physical number of bits per pixel in memory for the
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* source drawable (copies only).
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*/
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#ifndef TGASRCPIXELBITS
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#define TGASRCPIXELBITS 8
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#endif
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/*
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* TGASRCDEPTHBITS is the logical number of bits per pixel that the TGA+
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* operates on for the source drawable (copies only).
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*/
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#ifndef TGASRCDEPTHBITS
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#define TGASRCDEPTHBITS 8
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#endif
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/*
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* If TGASRCPIXELBITS/TGASRCDEPTHBITS = 4, you have an unpacked 8-bit source
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* visual. Otherwise TGASRCPIXELBITS/TGASRCDEPTHBITS = 1.
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*/
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/* Number of pixels that opaque and transparent stipple modes affect. */
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#define TGASTIPPLEBITS 32
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/* Number of pixels that masked copies can affect. */
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#define TGACOPYBITS 32
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/* size of on-chip copy buffer; also used to identify copy64 capability */
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#define TGACOPYBUFFERBYTES 64
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/* Maximum number of bits that Bresenham line-drawing engine can handle. */
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#define TGALINEBITS 16
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/*
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* The number of bits on the bus that TGA pays attention to in dumb frame
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* buffer mode, and when reading or writing the internal copy buffer.
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*/
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#define TGABUSBITS 32
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/*
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* The number of bits in the path to VRAM; accelerated modes must use this
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* alignment for the address they provide the smart frame buffer.
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*/
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#define TGAVRAMBITS 64
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#define TGABUFFERWORDS 8
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/* Alignment for transparent and opaque stipples */
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#if TGAPIXELBITS==8
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#define TGASTIPPLEALIGNMENT 4
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#else
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#define TGASTIPPLEALIGNMENT 16
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#endif
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/* Alignment for simple mode operations */
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/* 4 bytes for all but 8bpp unpacked, which is 16 bytes */
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/* The numbers below represent pixels */
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#if (TGAPIXELBITS==32) && (TGADEPTHBITS==8)
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#define TGASIMPLEALIGNMENT 16
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#else
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#if (TGAPIXELBITS==32)
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#define TGASIMPLEALIGNMENT 1
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#else
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#define TGASIMPLEALIGNMENT 4
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#endif
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#endif
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/*
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* Constants in support of 24 plane TGA-based cursor management.
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*/
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// This should be evenly divisible by 4.
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#define TGA_CURSOR_BUFFER_SIZE 1024
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/*
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* The effective size of the copy pixel shifter for COPY, DMAREAD,
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* and DMAWRITE modes. These parameters precisely determine source
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* and destination alignment constraints, except for a DMAWRITE
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* destination.
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*/
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#define TGACOPYSHIFTBYTES 8
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#define TGACOPYSHIFTBYTESMASK (TGACOPYSHIFTBYTES - 1)
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#define TGADMAWRITESHIFTBYTES 8
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#define TGADMAWRITESHIFTBYTESMASK (TGADMAWRITESHIFTBYTES - 1)
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#define TGADMAREADSHIFTBYTES 4
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#define TGADMAREADSHIFTBYTESMASK (TGADMAREADSHIFTBYTES - 1)
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/* X data types that need to be translated into non-X (Win32) equivalents */
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typedef unsigned char Pixel8;
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typedef unsigned long Pixel32;
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typedef unsigned long Bits32;
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typedef int Int32;
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#if TGABUSBITS == 32
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typedef Pixel32 PixelWord;
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typedef Bits32 CommandWord;
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#elif TGABUSBITS == 64
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typedef Pixel64 PixelWord;
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typedef Bits64 CommandWord;
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#endif
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// TGA register offsets, organized by functionality.
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/*
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** Graphics Command Registers.
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*/
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#define REG_BRES_CONT 0x0000004C
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#define REG_START 0x00000054
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#define REG_SLOPE_NO_GO_R0 0x00000100
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#define REG_SLOPE_NO_GO_R1 0x00000104
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#define REG_SLOPE_NO_GO_R2 0x00000108
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#define REG_SLOPE_NO_GO_R3 0x0000010C
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#define REG_SLOPE_NO_GO_R4 0x00000110
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#define REG_SLOPE_NO_GO_R5 0x00000114
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#define REG_SLOPE_NO_GO_R6 0x00000118
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#define REG_SLOPE_NO_GO_R7 0x0000011C
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#define REG_SLOPE_R0 0x00000120
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#define REG_SLOPE_R1 0x00000124
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#define REG_SLOPE_R2 0x00000128
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#define REG_SLOPE_R3 0x0000012C
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#define REG_SLOPE_R4 0x00000130
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#define REG_SLOPE_R5 0x00000134
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#define REG_SLOPE_R6 0x00000138
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#define REG_SLOPE_R7 0x0000013C
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#define REG_COPY_64_SRC 0x00000160
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#define REG_COPY_64_DEST 0x00000164
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#define REG_COPY_64_SRC_A1 0x00000168 // alias
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#define REG_COPY_64_DEST_A1 0x0000016C // alias
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#define REG_COPY_64_SRC_A2 0x00000170 // alias
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#define REG_COPY_64_DEST_A2 0x00000174 // alias
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#define REG_COPY_64_SRC_A3 0x00000178 // alias
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#define REG_COPY_64_DEST_A3 0x0000017C // alias
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/*
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** Graphics Control Registers.
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*/
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#define REG_COPY_BUFFER_0 0x00000000
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#define REG_COPY_BUFFER_1 0x00000004
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#define REG_COPY_BUFFER_2 0x00000008
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#define REG_COPY_BUFFER_3 0x0000000C
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#define REG_COPY_BUFFER_4 0x00000010
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#define REG_COPY_BUFFER_5 0x00000014
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#define REG_COPY_BUFFER_6 0x00000018
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#define REG_COPY_BUFFER_7 0x0000001C
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#define REG_FOREGROUND 0x00000020
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#define REG_BACKGROUND 0x00000024
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#define REG_PLANE_MASK 0x00000028
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#define REG_ONE_SHOT_PIXEL_MASK 0x0000002C
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#define REG_MODE 0x00000030
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#define REG_RASTER_OP 0x00000034
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#define REG_PIXEL_SHIFT 0x00000038
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#define REG_ADDRESS 0x0000003C
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#define REG_BRES_R1 0x00000040
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#define REG_BRES_R2 0x00000044
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#define REG_BRES_R3 0x00000048
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#define REG_DEEP 0x00000050
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#define REG_STENCIL_MODE 0x00000058
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#define REG_PERS_PIXEL_MASK 0x0000005C
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#define REG_DATA 0x00000080
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#define REG_RED_INCR 0x00000084
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#define REG_GREEN_INCR 0x00000088
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#define REG_BLUE_INCR 0x0000008C
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#define REG_Z_INCR_LOW 0x00000090
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#define REG_Z_INCR_HIGH 0x00000094
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#define REG_DMA_BASE_ADDRESS 0x00000098
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#define REG_BRES_WIDTH 0x0000009C
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#define REG_Z_VAL_LOW 0x000000A0
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#define REG_Z_VAL_HIGH 0x000000A4
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#define REG_Z_BASE_ADDR 0x000000A8
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#define REG_ADDRESS_1 0x000000AC
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#define REG_RED_VALUE 0x000000B0
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#define REG_GREEN_VALUE 0x000000B4
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#define REG_BLUE_VALUE 0x000000B8
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#define REG_SPAN_WIDTH 0x000000BC
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#define REG_BLK_COLOR_R0 0X00000140
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#define REG_BLK_COLOR_R1 0X00000144
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#define REG_BLK_COLOR_R2 0X00000148
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#define REG_BLK_COLOR_R3 0X0000014C
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#define REG_BLK_COLOR_R4 0X00000150
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#define REG_BLK_COLOR_R5 0X00000154
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#define REG_BLK_COLOR_R6 0X00000158
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#define REG_BLK_COLOR_R7 0X0000015C
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/*
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** Video Timing Registers
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*/
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#define REG_H_CONT 0x00000064
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#define REG_V_CONT 0x00000068
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#define REG_VIDEO_BASE_ADDR 0x0000006C
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#define REG_VIDEO_VALID 0x00000070
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#define REG_VIDEO_SHIFT_ADDR 0x00000078
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/*
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** Cursor Control Regsiters
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*/
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#define REG_CUR_BASE_ADDR 0x00000060
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#define REG_CURSOR_XY 0x00000074
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/*
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** Miscellaneous Registers.
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*/
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#define REG_INTR_STATUS 0x0000007C
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#define REG_RAMDAC_SETUP 0x000000C0
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#define REG_EPROM_WRITE 0x00000180
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#define REG_CLOCK 0x00000184
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#define REG_RAMDAC_INTERFACE 0X00000188
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#define REG_COMMAND_STATUS 0x0000018C
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/* ********************************************************** */
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/* **** Some data structure definitions **** */
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/* **** **** */
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/************************************************************ */
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typedef struct
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{
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unsigned rOp : 4;
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unsigned fill : 4;
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unsigned visual : 2; /* defines type of dst
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* visual on 32-plane systems */
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unsigned rotate : 2; /* defines position of dst 8-bit
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* visual on 32-plane systems */
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} ROP;
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typedef struct
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{
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unsigned e1 : 16; /* e1 is always positive */
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int a1 : 16; /* address/error inc if e < 0 */
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} BRES1;
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typedef struct
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{
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unsigned e2 : 16; /* e2 is positive (it's negated when used) */
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int a2 : 16; /* address/error inc if e >= 0 */
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} BRES2;
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typedef struct
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{
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unsigned lineLength : 4; /* line length count */
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unsigned ignored : 11;
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int e : 17; /* e is sign-extended */
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} BRES3;
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typedef struct
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{
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unsigned value : 20; /* color value */
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unsigned ignored : 7;
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unsigned rowcol : 5; /* row/column dither index */
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} RGVAL;
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typedef struct
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{
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unsigned mode : 7; /* basic mode */
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unsigned ignored : 1;
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unsigned visual : 3; /* defines type of src
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* visual on 32-plane systems */
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|
unsigned rotate : 2; /* defines position of src 8-bit
|
|
* visual on 32-plane systems */
|
|
unsigned ntLines : 1; /* Windows32 GQI style lines */
|
|
unsigned z16 : 1; /* Z buffer size is 16 bits */
|
|
unsigned capEnds : 1; /* cap ends of lines (or not) */
|
|
} MODE;
|
|
|
|
typedef struct
|
|
{
|
|
unsigned sWrMask : 8;
|
|
unsigned sRdMask : 8;
|
|
unsigned sTest : 3; /* comparison to perform on stencil buffer */
|
|
unsigned sFail : 3; /* op if stencil test fails */
|
|
unsigned zFail : 3; /* op if stencil test passes, Z test fails */
|
|
unsigned zPass : 3; /* op if stencil test passes, Z test passes */
|
|
unsigned zTest : 3; /* comparison to perform on Z-buffer */
|
|
unsigned zOp : 1; /* 0 -> KEEP, 1 -> REPLACE */
|
|
} STENCIL;
|
|
|
|
typedef struct
|
|
{
|
|
unsigned active : 11;
|
|
unsigned fp : 5;
|
|
unsigned sync : 6;
|
|
unsigned bp : 6;
|
|
} VERT;
|
|
|
|
typedef struct
|
|
{
|
|
unsigned active : 9;
|
|
unsigned fp : 5;
|
|
unsigned sync : 7;
|
|
unsigned bp : 7;
|
|
unsigned ignore : 3;
|
|
unsigned odd : 1;
|
|
} HORIZ;
|
|
|
|
typedef struct
|
|
{
|
|
unsigned x : 12;
|
|
unsigned y : 12;
|
|
} CURSORXYSTRUCT;
|
|
|
|
typedef struct
|
|
{
|
|
unsigned ignore : 4;
|
|
unsigned base : 6;
|
|
unsigned rowsMinusOne : 6;
|
|
} CURSORBASESTRUCT;
|
|
|
|
/*
|
|
* the following is a pseudo-register.
|
|
* no storage actually exists for it.
|
|
*/
|
|
typedef struct
|
|
{
|
|
unsigned linedata : 16;
|
|
unsigned addrLo : 2;
|
|
} BSTART;
|
|
|
|
typedef struct
|
|
{
|
|
unsigned pixCount : 11;
|
|
unsigned ignore1 : 5;
|
|
unsigned addrLo : 2;
|
|
unsigned ignore2 : 14;
|
|
} BLKFILL;
|
|
|
|
typedef struct
|
|
{
|
|
unsigned left1 : 4;
|
|
unsigned left2 : 4;
|
|
unsigned right1 : 4;
|
|
unsigned right2 : 4;
|
|
unsigned count : 11;
|
|
unsigned ignore : 5;
|
|
} DMAREADCMD;
|
|
|
|
typedef struct
|
|
{
|
|
unsigned left : 8;
|
|
unsigned right : 8;
|
|
unsigned count : 11;
|
|
unsigned ignore : 5;
|
|
} DMAWRITECMD;
|
|
|
|
typedef struct
|
|
{
|
|
unsigned dx : 16; /* magnitude of delta-x */
|
|
unsigned dy : 16; /* magnitude of delta-y */
|
|
} DXDY;
|
|
|
|
typedef struct
|
|
{
|
|
unsigned drawable : 16; /* width of drawable */
|
|
unsigned zbuffer : 16; /* width of zbuffer */
|
|
} BWIDTH;
|
|
|
|
typedef struct
|
|
{
|
|
unsigned base : 24;
|
|
unsigned ignored : 8;
|
|
} ZADDR;
|
|
|
|
typedef struct
|
|
{
|
|
unsigned base : 9;
|
|
unsigned ignored : 23;
|
|
} VBASE;
|
|
|
|
typedef struct
|
|
{
|
|
unsigned video_valid : 1;
|
|
unsigned blank_disable : 1;
|
|
unsigned cursor_enable : 1;
|
|
unsigned ignored : 29;
|
|
} VVALID;
|
|
|
|
typedef struct
|
|
{
|
|
unsigned fract : 32;
|
|
} ZINCLO;
|
|
|
|
typedef struct
|
|
{
|
|
unsigned whole : 4;
|
|
unsigned ignored : 28;
|
|
} ZINCHI;
|
|
|
|
typedef struct
|
|
{
|
|
unsigned fract : 32;
|
|
} ZVALLO;
|
|
|
|
typedef struct
|
|
{
|
|
unsigned whole : 4;
|
|
unsigned ignore : 20;
|
|
unsigned stencil : 8;
|
|
} ZVALHI;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
VERT reg;
|
|
} VERTICAL;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
HORIZ reg;
|
|
} HORIZONTAL;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
CURSORXYSTRUCT reg;
|
|
} CURSORXYREG;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
CURSORBASESTRUCT reg;
|
|
} CURSORBASEREG;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
ROP reg;
|
|
} ROPREG;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
MODE reg;
|
|
} MODEREG;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
STENCIL reg;
|
|
} STENCILREG;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
BWIDTH reg;
|
|
} BWIDTHREG;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
BRES1 reg;
|
|
} BRES1REG;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
BRES2 reg;
|
|
} BRES2REG;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
BRES3 reg;
|
|
} BRES3REG;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
BSTART reg;
|
|
} BSTARTREG;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
BLKFILL reg;
|
|
} BLKFILLREG;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
DMAREADCMD rdCmd;
|
|
DMAWRITECMD wrCmd;
|
|
} DMACMD;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
RGVAL reg;
|
|
} RGVALREG;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
DXDY reg;
|
|
} DXDYREG;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
ZADDR reg;
|
|
} ZADDRREG;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
ZINCLO reg;
|
|
} ZINCLOREG;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
VBASE reg;
|
|
} VBASEREG;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
VVALID reg;
|
|
} VVALIDREG;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
ZINCHI reg;
|
|
} ZINCHIREG;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
ZVALLO reg;
|
|
} ZVALLOREG;
|
|
|
|
typedef union {
|
|
unsigned u32;
|
|
ZVALHI reg;
|
|
} ZVALHIREG;
|
|
|
|
/* ############################################################ */
|
|
/* #### TGA bit position flags #### */
|
|
/* ############################################################ */
|
|
|
|
/* rotation and visual field definitions - from FFB code */
|
|
/* Once we redo the FFB code to use the TGA_MODE_ and TGA_ROP_ */
|
|
/* constants below, then we don't need these. */
|
|
|
|
#define PACKED_EIGHT_DEST 0
|
|
#define UNPACKED_EIGHT_DEST 1
|
|
#define TWELVE_BIT_DEST 2
|
|
#define TWENTYFOUR_BIT_DEST 3
|
|
|
|
#define PACKED_EIGHT_SRC 0
|
|
#define UNPACKED_EIGHT_SRC 1
|
|
#define TWELVE_BIT_BUF0_SRC 6
|
|
#define TWELVE_BIT_BUF1_SRC 2
|
|
#define TWENTYFOUR_BIT_SRC 3
|
|
|
|
#define ROTATE_DESTINATION_0 0
|
|
#define ROTATE_DESTINATION_1 1
|
|
#define ROTATE_DESTINATION_2 2
|
|
#define ROTATE_DESTINATION_3 3
|
|
|
|
#define ROTATE_SOURCE_0 0
|
|
#define ROTATE_SOURCE_1 1
|
|
#define ROTATE_SOURCE_2 2
|
|
#define ROTATE_SOURCE_3 3
|
|
|
|
#define ROTATE_DONT_CARE 0
|
|
|
|
#define DST_VISUAL_SHIFT 8
|
|
#define DST_ROTATE_SHIFT 10
|
|
|
|
#define SRC_VISUAL_SHIFT 8
|
|
#define SRC_ROTATE_SHIFT 11
|
|
|
|
/* end rotation and visual field definitions */
|
|
|
|
/*
|
|
* TGA modes
|
|
*/
|
|
|
|
typedef enum {
|
|
/* 000000 */ TGA_MODE_SIMPLE = 0x00,
|
|
/* 000001 */ TGA_MODE_OPAQUE_STIPPLE = 0x01,
|
|
/* 000010 */ TGA_MODE_OPAQUE_LINE = 0x02,
|
|
/* 000101 */ TGA_MODE_TRANSPARENT_STIPPLE = 0x05,
|
|
/* 000110 */ TGA_MODE_TRANSPARENT_LINE = 0x06,
|
|
/* 000111 */ TGA_MODE_COPY = 0x07,
|
|
/* 001101 */ TGA_MODE_BLOCK_STIPPLE = 0x0d,
|
|
/* 001110 */ TGA_MODE_CINTERP_TRANSPARENT_NONDITHER_LINE = 0x0e,
|
|
/* 001111 */ TGA_MODE_WICKED_FAST_COPY = 0x0f,
|
|
/* 010000 */ TGA_MODE_Z_SIMPLE = 0x10,
|
|
/* 010010 */ TGA_MODE_Z_OPAQUE_LINE = 0x12,
|
|
/* 010110 */ TGA_MODE_Z_TRANSPARENT_LINE = 0x16,
|
|
/* 010111 */ TGA_MODE_DMA_READ_COPY = 0x17,
|
|
/* 011010 */ TGA_MODE_Z_CINTERP_OPAQUE_NONDITHER_LINE = 0x1a,
|
|
/* 011110 */ TGA_MODE_Z_CINTERP_TRANSPARENT_NONDITHER_LINE = 0x1e,
|
|
/* 011111 */ TGA_MODE_DMA_WRITE_COPY = 0x1f,
|
|
/* 100001 */ TGA_MODE_OPAQUE_FILL = 0x21,
|
|
/* 100101 */ TGA_MODE_TRANSPARENT_FILL = 0x25,
|
|
/* 101101 */ TGA_MODE_BLOCK_FILL = 0x2d,
|
|
/* 101110 */ TGA_MODE_CINTERP_TRANSPARENT_DITHER_LINE = 0x2e,
|
|
/* 110111 */ TGA_MODE_DMA_READ_COPY_DITHER = 0x37,
|
|
/* 111010 */ TGA_MODE_Z_CINTERP_OPAQUE_DITHER_LINE = 0x3a,
|
|
/* 111110 */ TGA_MODE_Z_CINTERP_TRANSPARENT_DITHER_LINE = 0x3e,
|
|
/*1001110 */ TGA_MODE_SEQ_INTERP_TRANSPARENT_LINE = 0x4e,
|
|
/*1011010 */ TGA_MODE_Z_SEQ_INTERP_OPAQUE_LINE = 0x5a,
|
|
/*1011110 */ TGA_MODE_Z_SEQ_INTERP_TRANSPARENT_LINE = 0x5e
|
|
} TGAMode;
|
|
|
|
/*
|
|
** MODE register source bitmap
|
|
** For 32-bpp TGA frame buffers. Not available in 8-bpp TGA systems.
|
|
*/
|
|
|
|
#define TGA_MODE_VISUAL_8_PACKED 0x0000
|
|
#define TGA_MODE_VISUAL_8_UNPACKED 0x0100
|
|
#define TGA_MODE_VISUAL_12_LOW 0x0200
|
|
#define TGA_MODE_VISUAL_12_HIGH 0x0600
|
|
#define TGA_MODE_VISUAL_24 0x0300
|
|
|
|
/*
|
|
** MODE register rotation
|
|
*/
|
|
|
|
#define TGA_MODE_ROTATE_0_BYTES 0x0000
|
|
#define TGA_MODE_ROTATE_1_BYTES 0x0800
|
|
#define TGA_MODE_ROTATE_2_BYTES 0x1000
|
|
#define TGA_MODE_ROTATE_3_BYTES 0x1800
|
|
|
|
/*
|
|
** MODE register environment
|
|
*/
|
|
|
|
#define TGA_MODE_X_ENVIRONMENT 0x0000
|
|
#define TGA_MODE_WIN32_ENVIRONMENT 0x2000
|
|
|
|
/*
|
|
** MODE register Z value
|
|
*/
|
|
|
|
#define TGA_MODE_Z_24BITS 0x0000
|
|
#define TGA_MODE_Z_16BITS 0x4000
|
|
|
|
/*
|
|
** MODE register Cap Ends
|
|
*/
|
|
|
|
#define TGA_MODE_CAPENDS_DISABLE 0x0000
|
|
#define TGA_MODE_CAPENDS_ENABLE 0x8000
|
|
|
|
/*
|
|
** Raster Op definitions - from TGA's perspective,
|
|
** i.e. Win32 has its own definitions (those in comments)
|
|
*/
|
|
|
|
#define TGA_ROP_CLEAR 0 /* BLACKNESS */
|
|
#define TGA_ROP_AND 1 /* SRCAND, MERGECOPY */
|
|
#define TGA_ROP_AND_REVERSE 2 /* SRCERASE */
|
|
#define TGA_ROP_COPY 3 /* SRCCOPY, PATCOPY */
|
|
#define TGA_ROP_AND_INVERTED 4
|
|
#define TGA_ROP_NOP 5
|
|
#define TGA_ROP_XOR 6 /* SRCINVERT, PATINVERT */
|
|
#define TGA_ROP_OR 7 /* SRCPAINT */
|
|
#define TGA_ROP_NOR 8 /* NOTSRCERASE */
|
|
#define TGA_ROP_EQUIV 9
|
|
#define TGA_ROP_INVERT 10 /* DSTINVERT */
|
|
#define TGA_ROP_OR_REVERSE 11
|
|
#define TGA_ROP_COPY_INVERTED 12 /* NOTSRCCOPY */
|
|
#define TGA_ROP_OR_INVERTED 13 /* MERGEPAINT */
|
|
#define TGA_ROP_NAND 14
|
|
#define TGA_ROP_SET 15 /* WHITENESS */
|
|
|
|
/*
|
|
** ROP register destination bitmap
|
|
*/
|
|
|
|
#define TGA_ROP_VISUAL_8_PACKED 0x0000
|
|
#define TGA_ROP_VISUAL_8_UNPACKED 0x0100
|
|
#define TGA_ROP_VISUAL_12 0x0200
|
|
#define TGA_ROP_VISUAL_24 0x0300
|
|
|
|
/*
|
|
** ROP register rotation
|
|
*/
|
|
|
|
#define TGA_ROP_ROTATE_0_BYTES 0x0000
|
|
#define TGA_ROP_ROTATE_1_BYTES 0x1000
|
|
#define TGA_ROP_ROTATE_2_BYTES 0x2000
|
|
#define TGA_ROP_ROTATE_3_BYTES 0x3000
|
|
|
|
/* ########################################################### */
|
|
/* #### TGA Interrupts #### */
|
|
/* ########################################################### */
|
|
|
|
#define DISABLE_INTERRUPTS 0
|
|
#define ENABLE_INTERRUPTS 1
|
|
|
|
/*
|
|
** specifics of interrupt register (assumes low to high bit ordering)
|
|
*/
|
|
typedef union {
|
|
volatile unsigned char *reg;
|
|
struct {
|
|
volatile unsigned char TGA_vsync :1;
|
|
volatile unsigned char TGA_shift_addr :1;
|
|
volatile unsigned char TGA_dma_error :1;
|
|
volatile unsigned char TGA_parity_error :1;
|
|
volatile unsigned char TGA_timer :1;
|
|
volatile unsigned char unused :3;
|
|
} *flags;
|
|
} intr_reg_t;
|
|
|
|
#endif /* TGAPARAM_H */
|