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928 lines
32 KiB
928 lines
32 KiB
/********************************** module *********************************/
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/* */
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/* disasm */
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/* disassembler for CodeView */
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/* */
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/***************************************************************************/
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/* */
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/* @ Purpose: To disassemble one 80x86 instruction at address loc and */
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/* return the resulting string in dst. */
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/* */
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/* @ Functions included: */
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/* */
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/* void DIdisasm(ADDR *loc, int option,char *dst, struct ea *ea) */
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/* */
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/* */
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/* @ Author: Gerd Immeyer @ Version: */
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/* */
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/* @ Creation Date: 10.19.89 @ Modification Date: */
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/* */
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/* 27-Oct-1992 BobDay Gutted most of the code since it was duplicated */
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/* in 86DIS.C */
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/* */
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/***************************************************************************/
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#include "ntsdp.h"
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#include "ntreg.h"
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#include <ppcinst.h>
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#include "ntdis.h"
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#include <stddef.h>
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#include <string.h>
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// internal function definitions
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// PowerPC definitions
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#define OPSTART 35
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#define MSKSTART 63
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UCHAR pszBreak[] = "break";
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struct instrmask {
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ULONG low;
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ULONG high;
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ULONG shift;
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};
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struct instrmask maskfield;
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PPC_INSTRUCTION disinstr;
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ULONG EAaddr = 0;
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PPC_INSTRUCTION tempinstr;
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BOOLEAN dispmsk32 = FALSE;
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BOOLEAN dispmsk64 = FALSE;
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static PUCHAR pBufStart;
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static PUCHAR pBuf;
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ULONG InstrOffset;
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UCHAR HexDigit[16] = {
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'0', '1', '2', '3', '4', '5', '6', '7',
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'8', '9', 'a', 'b', 'c', 'd', 'e', 'f'
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};
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/*****************************************************************
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*
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* Table of operand masks and shift counts indexed by operand type
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*
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*****************************************************************/
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static struct {
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unsigned long opnd_mask;
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unsigned long shift_count;
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} possibilities[] = {
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0x001F0000,16, // procopBA
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0x0000F800,11, // procopBB
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0x0000FFFC, 0, // procopBD
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0x0000FFFC, 0, // procopBDA
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0x03800000,23, // procopBFcr
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0x03800000,23, // procopBFfpscr
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0x001C0000,18, // procopBFAcr
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0x001C0000,18, // procopBFAfpscr
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0x001F0000,16, // procopBI
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0x03E00000,21, // procopBO
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0x03E00000,21, // procopBTcr
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0x03E00000,21, // procopBTfpscr
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0x001FF800,11, // procopDBATL
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0x001FF800,11, // procopDBATU
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0x01FE0000,17, // procopFLM
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0x0000F000, 0, // procopFL1
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0x0000001C, 0, // procopFL2
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0x001F0000,16, // procopFRA
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0x0000F800,11, // procopFRB
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0x000007C0, 6, // procopFRC
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0x03E00000,21, // procopFRS
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0x03E00000,21, // procopFRT
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0x000FF000,12, // procopFXM
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0x001FF800,11, // procopIBATL
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0x001FF800,11, // procopIBATU
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0x00200000,21, // procopL
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0x00000FE0, 0, // procopLEV
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0x03FFFFFC, 0, // procopLI
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0x03FFFFFC, 0, // procopLIA
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0x000007C0, 6, // procopMB32
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0x000007E0, 5, // procopMB64
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0x0000003E, 1, // procopME32
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0x000007E0, 5, // procopME64
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0x0000F800, 0, // procopNB
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0x001F0000,16, // procopRA
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0x0000F800,11, // procopRB
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0x03E00000,21, // procopRS
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0x03E00000,21, // procopRT
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0x0000F800,11, // procopSH32
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0x0000F802, 0, // procopSH64
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0x0000FFFF, 0, // procopSI
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0x0000FFFF, 0, // procopSIneg
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0x0000FFFF, 0, // procopSIign
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0x0000FFFF, 0, // procopSInegign
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0x001FF800,11, // procopSPR
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0x001FF800,11, // procopSPRG
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0x000F0000,16, // procopSR
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0x0000FFFC, 0, // procopSV
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0x03E00000,21, // procopTO
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0x0000F000,16, // procopU
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0x0000FFFF, 0, // procopUI
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0x00007FFE, 0, // procopMASK32
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0x00007E00, 5, // procopMASK64L
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0x00007E00, 5, // procopMASK64R
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0x00007E00, 0, // procopMASK64SH
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0x00007E00, 0, // procopMB64X
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0x00007E00, 0, // procopME64X
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0x00007E00, 0, // procopME64XSH
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0x001FFFFF, 0, // procopBDISP
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0x001FFFFC, 0, // procopBDISP14
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0x0000FFFE, 0, // procopBP32
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0x0000FFFE, 0, // procopBP64
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0x0000FFFE, 0, // procopMB32
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0x0000FFFE, 0, // procopNB64
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0x001FF800, 0, // procopTBfrom
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0x001FF800, 0, // procopTBto
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0x00000000, 0, // procopBS
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0x00000000, 0, // procopBT
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0x00000000, 0, // procopC
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0x00000000, 0, // procopCT
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0x00000000, 0, // procopMA
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0x00000000, 0, // procopMB
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0x00000000, 0, // procopMI
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0x00000000, 0, // procopMS
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0x00000000, 0, // procopMT
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0x00000000, 0, // procopMX
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0x00000000, 0, // procopMXC
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0x00000000, 0, // procopMXCT
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0x00000000, 0 // procopIGNORE
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};
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static int num_possibilities =
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(sizeof (possibilities) / sizeof (possibilities[1]));
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extern PUCHAR pszReg[];
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extern PUCHAR pszBreakOp[];
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extern ULONG SubRegSPR[];
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BOOLEAN disasm(PADDR poffset, PUCHAR bufptr, BOOLEAN fEAout);
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void OutputDisSymbol (ULONG offset);
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void BlankFill(ULONG count);
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void OutputString(PUCHAR pStr);
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void OutputHex(ULONG outvalue, ULONG length, BOOLEAN fsigned, BOOLEAN trunc0s);
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void OutputDec(ULONG outvalue, BOOLEAN fSigned);
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void OutputReg(ULONG regnum);
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void OutputFReg(ULONG regnum);
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void OutputBreakOp(ULONG opnum);
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void OutputCReg(ULONG regnum);
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void OutputSReg(ULONG regnum);
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void OutputSPRReg(ULONG regnum);
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void GetNextOffset(PADDR, BOOLEAN);
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/**** disasm - disassemble an 80x86/80x87 instruction
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*
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* Input:
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* pOffset = pointer to offset to start disassembly
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* fEAout = if set, include EA (effective address)
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*
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* Output:
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* pOffset = pointer to offset of next instruction
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* pchDst = pointer to result string
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*
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***************************************************************************/
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BOOLEAN disasm (PADDR poffset, PUCHAR bufptr, BOOLEAN fEAout)
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{
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LONG bdisp;
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ULONG maskbegin;
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ULONG maskend;
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LONG masktempl;
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LONG masktemph;
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LONG signimmed;
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LONG tempmask;
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BOOLEAN special;
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ULONG dispreg;
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LONG dispimmed;
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ULONG opcode;
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ULONG count;
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ULONG operand;
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int opcnt;
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int opndcnt;
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UCHAR chSuffix = '\0';
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UCHAR EAsize = 0;
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BOOLEAN match;
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pBufStart = pBuf = bufptr;
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InstrOffset = Flat(*poffset);
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OutputHex(InstrOffset, 8, FALSE, FALSE); // output hex offset
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*pBuf++ = ' ';
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if (!GetMemDword(poffset, &disinstr.Long)) {
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OutputString("???????? ????\n");
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*pBuf = '\0';
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return FALSE;
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}
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OutputHex(disinstr.Long, 8, FALSE, FALSE); // output hex contents
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*pBuf++ = ' ';
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// isolate the instructions primary opcode.
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opcode = disinstr.Primary_Op;
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// if the instruction is a branch eliminate the branch prediction bit
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// during the instruction search
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if (opcode == 0x10 ||
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(opcode == 0x13 && ((disinstr.XLform_XO == BCLR_OP) ||
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(disinstr.XLform_XO == BCCTR_OP)))) {
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disinstr.Long = disinstr.Long & 0xFFDFFFFF;
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}
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for (opcnt=0;opcnt<num_ops;opcnt++) {
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// Locate a matching opcode in the machine_ops table
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if (machine_ops[opcode_index[opcnt].op_index].template.Primary_Op == opcode) {
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// search for an instruction template to match current instruction.
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for (count=opcode_index[opcnt].op_index;count<opcode_index[opcnt+1].op_index;count++) {
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//
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// Since the PowerPC extended opcode field varies in location
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// depending on the instruction type the instruction is XOR'd with
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// a mask after a primary opcode is found to determine the
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// actual instruction.
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//
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match = FALSE;
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opcode = disinstr.Long & machine_ops[count].inst_mask;
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if ((machine_ops[count].template.Long ^ opcode) == 0) {
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if ((machine_ops[count].arch_flags & OPT_Simplified) == 0) {
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match = TRUE;
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} else if (((machine_ops[count].arch_flags & OPT_crbA_eq_crbB) != 0) &&
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(disinstr.XLform_BA == disinstr.XLform_BB)) {
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match = TRUE;
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} else if (((machine_ops[count].arch_flags & OPT_rS_eq_rB) != 0) &&
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(disinstr.Xform_RS == disinstr.Xform_RB)) {
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match = TRUE;
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}
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}
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if (match) {
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// Located the instruction. Output the opcode string.
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OutputString(machine_ops[count].name);
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// Special opcode processing can go here.
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// Opcode end with '.'
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if ((machine_ops[count].arch_flags & OPT_RC) && disinstr.Xform_RC) {
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OutputString(".");
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}
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BlankFill(OPSTART);
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//
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// Process any potential operands.
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//
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if (machine_ops[count].count) {
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//
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// Process specified operands in instruction template
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//
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for (opndcnt=0;opndcnt<machine_ops[count].count;opndcnt++) {
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operand = (ULONG) machine_ops[count].arg_types[opndcnt];
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tempinstr.Long = disinstr.Long & possibilities[operand-1].opnd_mask;
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if (possibilities[operand-1].shift_count) {
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tempinstr.Long >>= possibilities[operand-1].shift_count;
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}
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/*** Operand Processing **************************************************
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*
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* Purpose:
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* Decode operand value out of instruction and place appropriate
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* value into the output buffer.
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*
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* Input:
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* The instruction being disassembled with an operand mask and
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* shifted by the value represented by shift count for the operand
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* type.
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*
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* Output:
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* Text representation of operand placed into ouput buffer.
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*
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*************************************************************************/
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switch((enum opnd) operand)
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{
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case opBA:
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case opBB:
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case opBFfpscr:
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case opBFAfpscr:
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case opBI:
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case opBO:
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case opBTcr:
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case opBTfpscr:
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case opL:
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case opSH32:
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case opTO:
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case opU:
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OutputDec(tempinstr.Long,FALSE);
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break;
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case opBD:
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bdisp = ((LONG)(tempinstr.Bform_BD) << 2) + InstrOffset;
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OutputDisSymbol(bdisp);
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break;
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case opBDA:
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bdisp = ((LONG)(tempinstr.Bform_BD) << 2);
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OutputDisSymbol(bdisp);
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break;
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case opBFcr:
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case opBFAcr:
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OutputCReg (tempinstr.Long);
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break;
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case opDBATL:
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case opDBATU:
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case opIBATL:
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case opIBATU:
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OutputSPRReg(tempinstr.Long);
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break;
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case opFLM:
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dispmsk32 = TRUE;
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maskfield.low = 0xF0000000 >> (tempinstr.Long * 4);
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OutputHex(tempinstr.Long, 1, FALSE, TRUE);
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break;
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case opFRA:
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case opFRB:
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case opFRC:
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case opFRS:
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case opFRT:
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OutputFReg(tempinstr.Long);
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break;
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case opFXM:
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OutputHex(tempinstr.Long,2,TRUE,FALSE);
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break;
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case opLI:
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bdisp = ((LONG)(tempinstr.Iform_LI) << 2) + InstrOffset;
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OutputDisSymbol(bdisp);
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break;
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case opLIA:
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bdisp = ((LONG)(tempinstr.Iform_LI) << 2);
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OutputDisSymbol(bdisp);
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break;
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case opMB32:
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dispmsk32 = TRUE;
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maskfield.low = 0xFFFFFFFF;
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OutputDec (tempinstr.Long,FALSE);
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maskfield.low >>= tempinstr.Long;
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break;
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case opMB64:
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dispmsk64 = TRUE;
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maskbegin = tempinstr.Long;
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OutputDec (maskbegin,FALSE);
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if (maskbegin < 32) {
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maskfield.low = 0xFFFFFFFF;
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maskfield.high = 0xFFFFFFFF >> maskbegin;
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}
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else {
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maskfield.high = 0x0;
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maskfield.low = 0xFFFFFFFF >> (31 - (63-maskbegin));
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}
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break;
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case opME32:
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tempmask = 0x80000000;
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OutputDec (tempinstr.Long,FALSE);
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tempmask >>= tempinstr.Long;
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if (maskfield.low & tempmask) {
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maskfield.low &= tempmask; // MB <= ME
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} else {
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maskfield.low ^= tempmask; // ME > MB
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}
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break;
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case opME64:
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dispmsk64 = TRUE;
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maskend = tempinstr.Long;
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OutputDec (maskend,FALSE);
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if (maskend > 31) {
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masktemph = 0xFFFFFFFF;
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masktempl = ((LONG) 0x80000000) >> (maskend-32);
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}
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else {
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masktempl = 0;
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masktemph = ((LONG) 0x80000000) >> maskend;
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}
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maskfield.low &= masktempl;
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maskfield.high &= masktemph;
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break;
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case opRA:
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case opRB:
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case opRS:
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case opRT:
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OutputReg(tempinstr.Long);
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break;
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case opSH64:
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maskfield.shift = ((tempinstr.Long >> 1) & 0x00000001) << 5;
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maskfield.shift |= tempinstr.Long >> 11;
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OutputDec (maskfield.shift,FALSE);
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break;
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case opSI:
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case opUI:
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case opSIign:
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signimmed = (USHORT) (tempinstr.Long);
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OutputHex (signimmed,4,TRUE,FALSE);
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break;
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case opSIneg:
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case opSInegign:
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signimmed = 0;
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signimmed -= (SHORT) (tempinstr.Long);
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OutputHex (signimmed,4, TRUE, TRUE);
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break;
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case opSPR:
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case opSPRG:
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OutputSPRReg (tempinstr.Long);
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break;
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case opSR:
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OutputSReg (tempinstr.Long);
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break;
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case opMASK64L:
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dispmsk64 = TRUE;
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maskfield.low = 1;
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maskfield.high= 0;
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maskbegin = tempinstr.Long;
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OutputDec (maskbegin,FALSE);
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if (maskbegin < 32) {
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maskfield.low = (ULONG)-1;
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maskfield.high = 1 << (31-maskbegin);
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}
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else {
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maskfield.low <<= (63-maskbegin);
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}
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break;
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case opMASK64R:
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dispmsk64 = TRUE;
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maskfield.low = 0;
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maskfield.high= 0x80000000;
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maskend = tempinstr.Long;
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OutputDec (maskend,FALSE);
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if (maskend > 31) {
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maskfield.high = (ULONG)-1;
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maskfield.low = 0x80000000 >> (maskend-32);
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}
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else {
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maskfield.high >>= maskend;
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}
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break;
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case opMB64X:
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dispmsk64 = TRUE;
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maskfield.low = 0xFFFFFFFF;
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maskfield.high= 0xFFFFFFFF;
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OutputDec (0,FALSE);
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break;
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case opME64X:
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OutputDec (63,FALSE);
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break;
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case opME64XSH:
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dispmsk64 = TRUE;
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maskend = 63-maskfield.shift;
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OutputDec (maskend,FALSE);
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if (maskend > 31) {
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masktemph = 0xFFFFFFFF;
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masktempl = ((LONG) 0x80000000) >> (maskend-32);
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}
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else {
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masktempl = 0;
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masktemph = ((LONG) 0x80000000) >> maskend;
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}
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maskfield.low &= masktempl;
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maskfield.high &= masktemph;
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break;
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case opBDISP14: // intentionally fall through
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tempinstr.Long = tempinstr.Long & 0xFFFFFFFC;
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case opBDISP:
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dispreg = tempinstr.DSform_RA;
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dispimmed = (LONG)(tempinstr.Dform_D);
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OutputHex (dispimmed,4,FALSE,TRUE);
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OutputString("(");
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OutputReg (dispreg);
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OutputString(")");
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break;
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case opFL1:
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case opFL2:
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|
case opLEV:
|
|
case opNB:
|
|
case opSV:
|
|
case opMASK32:
|
|
case opMASK64SH:
|
|
case opBP32:
|
|
case opBP64:
|
|
case opNB32:
|
|
case opNB64:
|
|
case opTBfrom:
|
|
case opTBto:
|
|
case opBS:
|
|
case opBT:
|
|
case opC:
|
|
case opCT:
|
|
case opMA:
|
|
case opMB:
|
|
case opMI:
|
|
case opMS:
|
|
case opMT:
|
|
case opMX:
|
|
case opMXC:
|
|
case opMXCT:
|
|
case opIGNORE:
|
|
break;
|
|
}
|
|
|
|
if (opndcnt < (machine_ops[count].count-1)) {
|
|
OutputString(",");
|
|
}
|
|
}
|
|
if (dispmsk32) {
|
|
BlankFill(MSKSTART);
|
|
OutputString("MASK=0x");
|
|
OutputHex(maskfield.low, 8, FALSE, FALSE);
|
|
dispmsk32 = FALSE;
|
|
maskfield.low = 0;
|
|
}
|
|
if (dispmsk64) {
|
|
BlankFill(MSKSTART-8);
|
|
OutputString("MASK=0x");
|
|
OutputHex(maskfield.high, 8, FALSE, FALSE);
|
|
OutputHex(maskfield.low, 8, FALSE, FALSE);
|
|
dispmsk64 = FALSE;
|
|
maskfield.high = 0;
|
|
maskfield.low = 0;
|
|
}
|
|
}
|
|
count = opcode_index[opcnt+1].op_index; // Force control out of loop
|
|
}
|
|
}
|
|
opcnt = num_ops; // Force control out of loop
|
|
}
|
|
}
|
|
|
|
|
|
// check for "twi 31,0,#" where # < DEBUG_UNLOAD_SYMBOLS_BREAKPOINT
|
|
// display as break instruction
|
|
if ((disinstr.Long >= BREAK_INSTR) &&
|
|
(disinstr.Long <= (BREAK_INSTR | DEBUG_UNLOAD_SYMBOLS_BREAKPOINT))) {
|
|
pBuf = pBufStart + 18;
|
|
OutputString(pszBreak);
|
|
BlankFill(OPSTART);
|
|
OutputBreakOp(disinstr.Dform_SI);
|
|
}
|
|
|
|
Off(*poffset) += sizeof(ULONG);
|
|
NotFlat(*poffset);
|
|
ComputeFlatAddress(poffset, NULL);
|
|
*pBuf++ = '\n';
|
|
*pBuf = '\0';
|
|
return TRUE;
|
|
}
|
|
|
|
/*** BlankFill - blank-fill buffer
|
|
*
|
|
* Purpose:
|
|
* To fill the buffer at *pBuf with blanks until
|
|
* position count is reached.
|
|
*
|
|
* Input:
|
|
* None.
|
|
*
|
|
* Output:
|
|
* None.
|
|
*
|
|
*************************************************************************/
|
|
|
|
void BlankFill(ULONG count)
|
|
{
|
|
do
|
|
*pBuf++ = ' ';
|
|
while (pBuf < pBufStart + count);
|
|
}
|
|
|
|
/*** OutputHex - output hex value
|
|
*
|
|
* Purpose:
|
|
* Output the value in outvalue into the buffer
|
|
* pointed by *pBuf. The value may be signed
|
|
* or unsigned depending on the value fSigned.
|
|
*
|
|
* Input:
|
|
* outvalue - value to output
|
|
* length - length in digits
|
|
* fSigned - TRUE if signed else FALSE
|
|
*
|
|
* Output:
|
|
* None.
|
|
*
|
|
*************************************************************************/
|
|
|
|
void OutputHex(ULONG outvalue, ULONG length, BOOLEAN fSigned, BOOLEAN trunc0s)
|
|
{
|
|
UCHAR digit[8];
|
|
LONG index = 0;
|
|
|
|
if (fSigned && (long)outvalue < 0) {
|
|
*pBuf++ = '-';
|
|
outvalue = ~outvalue + 1;
|
|
}
|
|
if (fSigned) {
|
|
*pBuf++ = '0';
|
|
*pBuf++ = 'x';
|
|
}
|
|
do {
|
|
digit[index++] = HexDigit[outvalue & 0xf];
|
|
outvalue >>= 4;
|
|
}
|
|
while ((fSigned && outvalue) || (!fSigned && index < (LONG)length));
|
|
|
|
while (--index >= 0) {
|
|
if (!trunc0s || (digit[index] != '0')) {
|
|
*pBuf++ = digit[index];
|
|
trunc0s = FALSE;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*** OutputDec - output decimal value
|
|
*
|
|
* Purpose:
|
|
* Output the value in outvalue into the buffer
|
|
* pointed by *pBuf.
|
|
*
|
|
* Input:
|
|
* outvalue - value to output
|
|
* length - length in digits
|
|
* fSigned - TRUE if signed else FALSE
|
|
*
|
|
* Output:
|
|
* None.
|
|
*
|
|
*************************************************************************/
|
|
|
|
void OutputDec (ULONG outvalue, BOOLEAN fSigned)
|
|
{
|
|
UCHAR digit[12];
|
|
LONG index = 0;
|
|
|
|
if (fSigned && (long)outvalue < 0) {
|
|
*pBuf++ = '-';
|
|
outvalue = ~outvalue + 1;
|
|
}
|
|
do {
|
|
digit[index++] = (UCHAR)('0' + outvalue % 10);
|
|
outvalue /= 10;
|
|
}
|
|
while (outvalue);
|
|
|
|
while (--index >= 0)
|
|
*pBuf++ = digit[index];
|
|
}
|
|
|
|
/*** Outputxxxxx - output string procedures
|
|
*
|
|
* Purpose:
|
|
* Copy a specified string into the buffer pointed by pBuf.
|
|
*
|
|
* Input:
|
|
* *pStr - pointer to string
|
|
*
|
|
* Output:
|
|
* None.
|
|
*
|
|
*************************************************************************/
|
|
|
|
void OutputString (PUCHAR pStr)
|
|
{
|
|
while (*pStr)
|
|
*pBuf++ = *pStr++;
|
|
return;
|
|
}
|
|
|
|
void OutputReg (ULONG regnum)
|
|
{
|
|
OutputString(pszReg[regnum + REGBASE]);
|
|
return;
|
|
}
|
|
|
|
void OutputFReg (ULONG regnum)
|
|
{
|
|
OutputString(pszReg[regnum*2]);
|
|
return;
|
|
}
|
|
|
|
void OutputCReg (ULONG regnum)
|
|
{
|
|
OutputString(pszReg[regnum + CRBASE]);
|
|
return;
|
|
}
|
|
|
|
void OutputSReg (ULONG regnum)
|
|
{
|
|
OutputString(pszReg[regnum + SRBASE]);
|
|
return;
|
|
}
|
|
|
|
void OutputBreakOp (ULONG opnum)
|
|
{
|
|
OutputString(pszBreakOp[(opnum > 10) ? (opnum-10):opnum]);
|
|
return;
|
|
}
|
|
|
|
void OutputSPRReg (ULONG regnum)
|
|
{
|
|
ULONG numsubregs;
|
|
|
|
for (numsubregs=0;numsubregs<(SPREND-SPRBASE);numsubregs++) {
|
|
if (regnum == SubRegSPR[numsubregs]) {
|
|
OutputString(pszReg[SPRBASE+numsubregs]);
|
|
return;
|
|
}
|
|
}
|
|
OutputString("UNDEFSPR");
|
|
return;
|
|
|
|
}
|
|
|
|
/*** OutputDisSymbol - output symbol for disassembly
|
|
*
|
|
* Purpose:
|
|
* Access symbol table with given offset and put string into buffer.
|
|
*
|
|
* Input:
|
|
* offset - offset of address to output
|
|
*
|
|
* Output:
|
|
* buffer pointed by pBuf updated with string:
|
|
* if symbol, no disp: <symbol>(<offset>)
|
|
* if symbol, disp: <symbol>+<disp>(<offset>)
|
|
* if no symbol, no disp: <offset>
|
|
*
|
|
*************************************************************************/
|
|
|
|
void OutputDisSymbol (ULONG offset)
|
|
{
|
|
UCHAR chAddrBuffer[SYMBOLSIZE + 16];
|
|
ULONG displacement;
|
|
PUCHAR pszTemp;
|
|
UCHAR ch;
|
|
|
|
GetSymbolStdCall(offset, chAddrBuffer, &displacement, NULL);
|
|
|
|
if (chAddrBuffer[0]) {
|
|
pszTemp = chAddrBuffer;
|
|
while (ch = *pszTemp++)
|
|
*pBuf++ = ch;
|
|
if (displacement) {
|
|
*pBuf++ = '+';
|
|
OutputHex(displacement, 8, TRUE, TRUE);
|
|
}
|
|
*pBuf++ = '(';
|
|
}
|
|
OutputHex(offset, 8, FALSE, TRUE);
|
|
if (chAddrBuffer[0])
|
|
*pBuf++ = ')';
|
|
}
|
|
|
|
//
|
|
// Conditional Branch Options Structure
|
|
// (BranchOp0-3) correspond to the PowerPC Architecture Book Names.
|
|
//
|
|
typedef union _BRANCHOPS {
|
|
ULONG BranchOps;
|
|
struct {
|
|
ULONG Pred: 1;
|
|
ULONG Op3 : 1;
|
|
ULONG Op2 : 1;
|
|
ULONG Op1 : 1;
|
|
ULONG Op0 : 1;
|
|
ULONG bit0_26 :27;
|
|
} Branch;
|
|
} BRANCHOPS;
|
|
|
|
|
|
/*** GetNextOffset - compute offset for trace or step
|
|
*
|
|
* Purpose:
|
|
* From a limited disassembly of the instruction pointed
|
|
* by the FIR register, compute the offset of the next
|
|
* instruction for either a trace or step operation.
|
|
*
|
|
* Input:
|
|
* fStep - TRUE if step offset returned - FALSE for trace offset
|
|
*
|
|
* Returns:
|
|
* step or trace offset if input is TRUE or FALSE, respectively
|
|
* -1 returned for trace flag to be used
|
|
*
|
|
*************************************************************************/
|
|
void GetNextOffset (PADDR pcaddr, BOOLEAN fStep)
|
|
{
|
|
LONG returnvalue;
|
|
ULONG firaddr;
|
|
ADDR fir;
|
|
BRANCHOPS BranchOp;
|
|
ULONG CondBit = 0x80000000;
|
|
ULONG Counter;
|
|
ULONG CondReg;
|
|
|
|
firaddr = (ULONG)GetRegValue(REGIP);
|
|
ADDR32( &fir, firaddr );
|
|
GetMemDword(&fir, &disinstr.Long);
|
|
returnvalue = firaddr + sizeof(ULONG); // assume delay slot
|
|
|
|
switch(disinstr.Primary_Op)
|
|
{
|
|
case 0x11: // sc 0x44xxxxxx
|
|
// stepping over a syscall instruction must set the breakpoint
|
|
// at the caller's return address, not the inst after the syscall
|
|
returnvalue = (ULONG)GetRegValue(SPRLR);
|
|
|
|
case 0x13: // bclr, bclrl, bcctr, bcctrl
|
|
// 0x4Cxxxxxx
|
|
if (!((fStep) && disinstr.Bform_LK)) { // !(Step and LR)
|
|
BranchOp.BranchOps = disinstr.Bform_BO; // Branch Cond. Options
|
|
CondReg = (ULONG)GetRegValue(REGCR);
|
|
Counter = (ULONG)GetRegValue(SPRCTR);
|
|
if (disinstr.Bform_BI != 0) {
|
|
CondBit = 0x80000000 >> disinstr.Bform_BI;
|
|
}
|
|
CondBit = ((CondBit & CondReg) != 0);
|
|
if ((disinstr.Long & 0xFC0007FE) == 0x4C000420) { // bcctr, bcctrl
|
|
if ((CondBit ^ (BranchOp.Branch.Op1 ^ 1L)) ||
|
|
BranchOp.Branch.Op0) {
|
|
returnvalue = Counter & 0xFFFFFFFC;
|
|
}
|
|
} else if ((disinstr.Long & 0xFC0007FE) == 0x4C000020) { // bclr, bclrl
|
|
if (!BranchOp.Branch.Op2) {
|
|
Counter -= 1;
|
|
}
|
|
if (((Counter != 0) ^ (BranchOp.Branch.Op3)) ||
|
|
BranchOp.Branch.Op2) {
|
|
if ((CondBit ^ BranchOp.Branch.Op1) ||
|
|
BranchOp.Branch.Op0) {
|
|
returnvalue = (ULONG)GetRegValue(SPRLR) & 0xFFFFFFFC;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 0x12: // b, ba, bl, bla
|
|
// 0x48xxxxxx
|
|
if (!((fStep) && disinstr.Bform_LK)) { // !(Step and LR)
|
|
if (disinstr.Bform_AA) { // absolute
|
|
returnvalue = (LONG)(disinstr.Iform_LI << 2);
|
|
} else { // relative to CIA
|
|
returnvalue = (LONG)(disinstr.Iform_LI << 2) + firaddr;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 0x10: // bc, bca, bcl, bcla
|
|
// 0x40xxxxxx
|
|
if (!((fStep) && disinstr.Bform_LK)) { // !(Step and LR)
|
|
BranchOp.BranchOps = disinstr.Bform_BO; // Branch Cond. Options
|
|
CondReg = (ULONG)GetRegValue(REGCR);
|
|
Counter = (ULONG)GetRegValue(SPRCTR);
|
|
if (disinstr.Bform_BI != 0) {
|
|
CondBit = 0x80000000 >> disinstr.Bform_BI;
|
|
}
|
|
CondBit = ((CondBit & CondReg) != 0);
|
|
if (!BranchOp.Branch.Op2) {
|
|
Counter -= 1;
|
|
}
|
|
if (((Counter != 0) ^ (BranchOp.Branch.Op3)) ||
|
|
BranchOp.Branch.Op2) {
|
|
if ((CondBit ^ (BranchOp.Branch.Op1 ^ 1L)) ||
|
|
BranchOp.Branch.Op0) {
|
|
if (disinstr.Bform_AA) { // absolute
|
|
returnvalue = (LONG)(disinstr.Bform_BD << 2);
|
|
} else { // relative to CIA
|
|
returnvalue = (LONG)(disinstr.Bform_BD << 2) + firaddr;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
ADDR32( pcaddr, returnvalue );
|
|
}
|