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77 lines
5.4 KiB
77 lines
5.4 KiB
//
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// Technically, all these registers are 64 bits, not 32 bits
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// but I don't know yet if WINDBG can handle that.
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// MBH TODO bugbug
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#define RSIZE 64
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{ szR0, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntV0 },
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{ szR1, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntT0 },
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{ szR2, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntT1 },
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{ szR3, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntT2 },
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{ szR4, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntT3 },
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{ szR5, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntT4 },
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{ szR6, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntT5 },
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{ szR7, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntT6 },
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{ szR8, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntT7 },
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{ szR9, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntS0 },
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{ szR10, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntS1 },
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{ szR11, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntS2 },
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{ szR12, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntS3 },
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{ szR13, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntS4 },
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{ szR14, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntS5 },
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{ szR15, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntFP },
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{ szR16, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntA0 },
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{ szR17, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntA1 },
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{ szR18, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntA2 },
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{ szR19, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntA3 },
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{ szR20, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntA4 },
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{ szR21, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntA5 },
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{ szR22, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntT8 },
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{ szR23, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntT9 },
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{ szR24, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntT10 },
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{ szR25, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntT11 },
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{ szR26, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntRA },
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{ szR27, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntT12 },
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{ szR28, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntAT },
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{ szR29, rtCPU | rtRegular | rtInteger | rtExtended, RSIZE, CV_ALPHA_IntGP },
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{ szR30, rtCPU | rtRegular | rtInteger | rtExtended | rtFrame, RSIZE, CV_ALPHA_IntSP },
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{ szR31, rtCPU | rtInteger | rtInvisible, RSIZE, CV_ALPHA_IntZERO },
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{ szFpcr,rtFPU | rtRegular | rtExtended | rtInteger, RSIZE, CV_ALPHA_Fpcr},
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{ szSoftFpcr,
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rtFPU | rtRegular | rtExtended | rtInteger, RSIZE, CV_ALPHA_SoftFpcr},
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{ szFir, rtCPU | rtExtended | rtInteger | rtExtended | rtPC, 64, CV_ALPHA_Fir },
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{ szPsr, rtCPU | rtExtended | rtInteger | rtExtended, 32, CV_ALPHA_Psr },
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{ szF0, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF0 },
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{ szF1, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF1 },
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{ szF2, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF2 },
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{ szF3, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF3 },
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{ szF4, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF4 },
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{ szF5, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF5 },
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{ szF6, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF6 },
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{ szF7, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF7 },
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{ szF8, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF8 },
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{ szF9, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF9 },
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{ szF10, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF10 },
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{ szF11, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF11 },
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{ szF12, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF12 },
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{ szF13, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF13 },
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{ szF14, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF14 },
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{ szF15, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF15 },
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{ szF16, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF16 },
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{ szF17, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF17 },
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{ szF18, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF18 },
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{ szF19, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF19 },
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{ szF20, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF20 },
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{ szF21, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF21 },
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{ szF22, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF22 },
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{ szF23, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF23 },
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{ szF24, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF24 },
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{ szF25, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF25 },
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{ szF26, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF26 },
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{ szF27, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF27 },
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{ szF28, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF28 },
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{ szF29, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF29 },
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{ szF30, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF30 },
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{ szF31, rtFPU | rtRegular | rtFloat | rtExtended, RSIZE, CV_ALPHA_FltF31 }
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