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71 lines
5.0 KiB
71 lines
5.0 KiB
{ SzAH, rtCPU | rtInvisible | rtInteger, 8, CV_REG_AH },
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{ SzAL, rtCPU | rtInvisible | rtInteger, 8, CV_REG_AL },
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{ SzAX, rtCPU | rtRegular | rtInteger, 16, CV_REG_AX },
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{ SzEAX, rtCPU | rtExtended | rtInteger, 32, CV_REG_EAX },
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{ SzBH, rtCPU | rtInvisible | rtInteger, 8, CV_REG_BH },
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{ SzBL, rtCPU | rtInvisible | rtInteger, 8, CV_REG_BL },
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{ SzBX, rtCPU | rtRegular | rtInteger, 16, CV_REG_BX },
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{ SzEBX, rtCPU | rtExtended | rtInteger, 32, CV_REG_EBX },
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{ SzCH, rtCPU | rtInvisible | rtInteger, 8, CV_REG_CH },
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{ SzCL, rtCPU | rtInvisible | rtInteger, 8, CV_REG_CL },
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{ SzCX, rtCPU | rtRegular | rtInteger, 16, CV_REG_CX },
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{ SzECX, rtCPU | rtExtended | rtInteger, 32, CV_REG_ECX },
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{ SzDH, rtCPU | rtInvisible | rtInteger, 8, CV_REG_DH },
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{ SzDL, rtCPU | rtInvisible | rtInteger, 8, CV_REG_DL },
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{ SzDX, rtCPU | rtRegular | rtInteger, 16, CV_REG_DX },
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{ SzEDX, rtCPU | rtExtended | rtInteger, 32, CV_REG_EDX },
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{ SzSI, rtCPU | rtRegular | rtInteger, 16, CV_REG_SI },
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{ SzESI, rtCPU | rtExtended | rtInteger, 32, CV_REG_ESI },
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{ SzDI, rtCPU | rtRegular | rtInteger, 16, CV_REG_DI },
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{ SzEDI, rtCPU | rtExtended | rtInteger, 32, CV_REG_EDI },
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{ SzIP, rtCPU | rtRegular | rtInteger | rtPC | rtNewLine, 16, CV_REG_IP },
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{ SzEIP, rtCPU | rtExtended | rtInteger | rtPC | rtNewLine, 32, CV_REG_EIP },
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{ SzSP, rtCPU | rtRegular | rtInteger | rtFrame, 16, CV_REG_SP },
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{ SzESP, rtCPU | rtExtended | rtInteger | rtFrame, 32, CV_REG_ESP },
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{ SzBP, rtCPU | rtRegular | rtInteger | rtFrame, 16, CV_REG_BP },
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{ SzEBP, rtCPU | rtExtended | rtInteger | rtFrame, 32, CV_REG_EBP },
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{ SzFlags, rtCPU | rtRegular | rtInteger, 16, CV_REG_FLAGS },
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{ SzEFlags, rtCPU | rtExtended | rtInteger, 32, CV_REG_EFLAGS },
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{ SzCS, rtCPU | rtExtended | rtRegular | rtInteger | rtPC | rtNewLine, 16, CV_REG_CS },
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{ SzDS, rtCPU | rtExtended | rtRegular | rtInteger, 16, CV_REG_DS },
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{ SzES, rtCPU | rtExtended | rtRegular | rtInteger, 16, CV_REG_ES },
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{ SzSS, rtCPU | rtExtended | rtRegular | rtInteger | rtFrame, 16, CV_REG_SS },
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{ SzFS, rtCPU | rtExtended | rtRegular | rtInteger, 16, CV_REG_FS },
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{ SzGS, rtCPU | rtExtended | rtRegular | rtInteger, 16, CV_REG_GS },
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{ SzCr0, rtCPU | rtSpecial | rtInteger | rtNewLine, 32, CV_REG_CR0 },
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{ SzCr2, rtCPU | rtSpecial | rtInteger, 32, CV_REG_CR2 },
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{ SzCr3, rtCPU | rtSpecial | rtInteger, 32, CV_REG_CR3 },
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{ SzCr4, rtCPU | rtSpecial | rtInteger, 32, CV_REG_CR4 },
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{ SzDr0, rtCPU | rtSpecial | rtInteger | rtNewLine, 32, CV_REG_DR0 },
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{ SzDr1, rtCPU | rtSpecial | rtInteger, 32, CV_REG_DR1 },
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{ SzDr2, rtCPU | rtSpecial | rtInteger, 32, CV_REG_DR2 },
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{ SzDr3, rtCPU | rtSpecial | rtInteger, 32, CV_REG_DR3 },
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{ SzDr6, rtCPU | rtSpecial | rtInteger, 32, CV_REG_DR6 },
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{ SzDr7, rtCPU | rtSpecial | rtInteger, 32, CV_REG_DR7 },
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{ SzGdtr, rtCPU | rtSpecial | rtInteger | rtNewLine, 32, CV_REG_GDTR },
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{ SzGdtl, rtCPU | rtSpecial | rtInteger, 16, CV_REG_GDTL },
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{ SzIdtr, rtCPU | rtSpecial | rtInteger, 32, CV_REG_IDTR },
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{ SzIdtl, rtCPU | rtSpecial | rtInteger, 16, CV_REG_IDTL },
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{ SzTr, rtCPU | rtSpecial | rtInteger, 16, CV_REG_TR },
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{ SzLdtr, rtCPU | rtSpecial | rtInteger, 16, CV_REG_LDTR },
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{ SzST0, rtFPU | rtRegular | rtExtended | rtFloat, 80, CV_REG_ST0 },
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{ SzST1, rtFPU | rtRegular | rtExtended | rtFloat, 80, CV_REG_ST1 },
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{ SzST2, rtFPU | rtRegular | rtExtended | rtFloat, 80, CV_REG_ST2 },
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{ SzST3, rtFPU | rtRegular | rtExtended | rtFloat, 80, CV_REG_ST3 },
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{ SzST4, rtFPU | rtRegular | rtExtended | rtFloat, 80, CV_REG_ST4 },
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{ SzST5, rtFPU | rtRegular | rtExtended | rtFloat, 80, CV_REG_ST5 },
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{ SzST6, rtFPU | rtRegular | rtExtended | rtFloat, 80, CV_REG_ST6 },
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{ SzST7, rtFPU | rtRegular | rtExtended | rtFloat, 80, CV_REG_ST7 },
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{ SzCtrl, rtFPU | rtRegular | rtExtended | rtInteger | rtNewLine, 16, CV_REG_CTRL },
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{ SzStat, rtFPU | rtRegular | rtExtended | rtInteger, 16, CV_REG_STAT },
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{ SzTag, rtFPU | rtRegular | rtExtended | rtInteger, 16, CV_REG_TAG },
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{ SzFpIp, rtFPU | rtRegular | rtInteger, 16, CV_REG_FPIP },
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{ SzFpEip, rtFPU | rtExtended | rtInteger, 32, CV_REG_FPEIP },
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{ SzFpCs, rtFPU | rtRegular | rtExtended | rtInteger | rtNewLine, 16, CV_REG_FPCS },
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{ SzFpDs, rtFPU | rtRegular | rtExtended | rtInteger, 16, CV_REG_FPDS },
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{ SzFpEdo, rtFPU | rtExtended | rtInteger, 32, CV_REG_FPEDO },
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{ SzFpDo, rtFPU | rtRegular | rtInteger, 16, CV_REG_FPDO }
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