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120 lines
7.5 KiB
120 lines
7.5 KiB
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#define SIZE 64
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{ szR0, rtCPU | rtInvisible| rtInteger, SIZE, CV_M4_IntZERO },
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{ szR1, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntAT },
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{ szR2, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntV0 },
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{ szR3, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntV1 },
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{ szR4, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntA0 },
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{ szR5, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntA1 },
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{ szR6, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntA2 },
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{ szR7, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntA3 },
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{ szR8, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT0 },
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{ szR9, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT1 },
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{ szR10, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT2 },
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{ szR11, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT3 },
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{ szR12, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT4 },
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{ szR13, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT5 },
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{ szR14, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT6 },
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{ szR15, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT7 },
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{ szR24, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT8 },
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{ szR25, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT9 },
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{ szR16, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntS0 },
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{ szR17, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntS1 },
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{ szR18, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntS2 },
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{ szR19, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntS3 },
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{ szR20, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntS4 },
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{ szR21, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntS5 },
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{ szR22, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntS6 },
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{ szR23, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntS7 },
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{ szR30, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntS8 },
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{ szR26, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntKT0 },
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{ szR27, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntKT1 },
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{ szR28, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntGP },
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{ szR29, rtCPU | rtRegular | rtExtended | rtInteger | rtFrame, SIZE, CV_M4_IntSP },
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{ szR31, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntRA },
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{ szLo, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntLO },
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{ szHi, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntHI },
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{ szFir, rtCPU | rtRegular | rtExtended | rtInteger | rtPC, 32, CV_M4_Fir },
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{ szPsr, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_M4_Psr },
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{ szFr0, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF0 },
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{ szFr1, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF1 },
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{ szFr2, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF2 },
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{ szFr3, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF3 },
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{ szFr4, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF4 },
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{ szFr5, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF5 },
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{ szFr6, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF6 },
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{ szFr7, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF7 },
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{ szFr8, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF8 },
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{ szFr9, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF9 },
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{ szFr10, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF10 },
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{ szFr11, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF11 },
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{ szFr12, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF12 },
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{ szFr13, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF13 },
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{ szFr14, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF14 },
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{ szFr15, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF15 },
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{ szFr16, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF16 },
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{ szFr17, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF17 },
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{ szFr18, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF18 },
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{ szFr19, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF19 },
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{ szFr20, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF20 },
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{ szFr21, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF21 },
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{ szFr22, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF22 },
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{ szFr23, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF23 },
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{ szFr24, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF24 },
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{ szFr25, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF25 },
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{ szFr26, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF26 },
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{ szFr27, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF27 },
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{ szFr28, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF28 },
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{ szFr29, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF29 },
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{ szFr30, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF30 },
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{ szFr31, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF31 },
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{ szFp0, rtFPU | rtExtended | rtFloat, 64,
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(CV_M4_FltF0 << 8) | CV_M4_FltF1 },
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{ szFp2, rtFPU | rtExtended | rtFloat, 64,
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(CV_M4_FltF2 << 8) | CV_M4_FltF3 },
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{ szFp4, rtFPU | rtExtended | rtFloat, 64,
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(CV_M4_FltF4 << 8) | CV_M4_FltF5 },
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{ szFp6, rtFPU | rtExtended | rtFloat, 64,
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(CV_M4_FltF6 << 8) | CV_M4_FltF7 },
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{ szFp8, rtFPU | rtExtended | rtFloat, 64,
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(CV_M4_FltF8 << 8) | CV_M4_FltF9 },
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{ szFp10, rtFPU | rtExtended | rtFloat, 64,
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(CV_M4_FltF10 << 8) | CV_M4_FltF11 },
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{ szFp12, rtFPU | rtExtended | rtFloat, 64,
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(CV_M4_FltF12 << 8) | CV_M4_FltF13 },
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{ szFp14, rtFPU | rtExtended | rtFloat, 64,
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(CV_M4_FltF14 << 8) | CV_M4_FltF15 },
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{ szFp16, rtFPU | rtExtended | rtFloat, 64,
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(CV_M4_FltF16 << 8) | CV_M4_FltF17 },
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{ szFp18, rtFPU | rtExtended | rtFloat, 64,
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(CV_M4_FltF18 << 8) | CV_M4_FltF19 },
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{ szFp20, rtFPU | rtExtended | rtFloat, 64,
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(CV_M4_FltF20 << 8) | CV_M4_FltF21 },
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{ szFp22, rtFPU | rtExtended | rtFloat, 64,
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(CV_M4_FltF22 << 8) | CV_M4_FltF23 },
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{ szFp24, rtFPU | rtExtended | rtFloat, 64,
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(CV_M4_FltF24 << 8) | CV_M4_FltF25 },
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{ szFp26, rtFPU | rtExtended | rtFloat, 64,
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(CV_M4_FltF26 << 8) | CV_M4_FltF27 },
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{ szFp28, rtFPU | rtExtended | rtFloat, 64,
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(CV_M4_FltF28 << 8) | CV_M4_FltF29 },
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{ szFp30, rtFPU | rtExtended | rtFloat, 64,
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(CV_M4_FltF30 << 8) | CV_M4_FltF31 },
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/*
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{ szFq0, rtFPU | rtExtended | rtFloat, 128, CV_M4_FltF0 },
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{ szFq4, rtFPU | rtExtended | rtFloat, 128, CV_M4_FltF4 },
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{ szFq8, rtFPU | rtExtended | rtFloat, 128, CV_M4_FltF8 },
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{ szFq12, rtFPU | rtExtended | rtFloat, 128, CV_M4_FltF12 },
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{ szFq16, rtFPU | rtExtended | rtFloat, 128, CV_M4_FltF16 },
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{ szFq20, rtFPU | rtExtended | rtFloat, 128, CV_M4_FltF20 },
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{ szFq24, rtFPU | rtExtended | rtFloat, 128, CV_M4_FltF24 },
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{ szFq28, rtFPU | rtExtended | rtFloat, 128, CV_M4_FltF28 }
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*/
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{ szFsr, rtFPU | rtRegular | rtExtended | rtInteger, 32, CV_M4_FltFsr }
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