Leaked source code of windows server 2003
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  1. /****************************************************************************
  2. ** COPYRIGHT (C) 1994-1997 INTEL CORPORATION **
  3. ** DEVELOPED FOR MICROSOFT BY INTEL CORP., HILLSBORO, OREGON **
  4. ** HTTP://WWW.INTEL.COM/ **
  5. ** THIS FILE IS PART OF THE INTEL ETHEREXPRESS PRO/100B(TM) AND **
  6. ** ETHEREXPRESS PRO/100+(TM) NDIS 5.0 MINIPORT SAMPLE DRIVER **
  7. ****************************************************************************/
  8. /****************************************************************************
  9. Module Name:
  10. e100_557.h (82557.h)
  11. This driver runs on the following hardware:
  12. - 82558 based PCI 10/100Mb ethernet adapters
  13. (aka Intel EtherExpress(TM) PRO Adapters)
  14. Environment:
  15. Kernel Mode - Or whatever is the equivalent on WinNT
  16. Revision History
  17. - JCB 8/14/97 Example Driver Created
  18. - Dchen 11-01-99 Modified for the new sample driver
  19. *****************************************************************************/
  20. #ifndef _E100_557_H
  21. #define _E100_557_H
  22. //-------------------------------------------------------------------------
  23. // D100 Stepping Defines
  24. //-------------------------------------------------------------------------
  25. #define D100_A_STEP 0 // NEVER SHIPPED
  26. #define D100_B_STEP 1 // d100 first shipped silicon
  27. #define D100_C_STEP 2 // d100' (c-step) with vendor/id and hw fix
  28. #define D101_A_STEP 4 // first silicon of d101
  29. //-------------------------------------------------------------------------
  30. // E100 Stepping Defines - used in PoMgmt Decisions
  31. //-------------------------------------------------------------------------
  32. #define E100_82557_A_STEP 1
  33. #define E100_82557_B_STEP 2
  34. #define E100_82557_C_STEP 3
  35. #define E100_82558_A_STEP 4
  36. #define E100_82558_B_STEP 5
  37. #define E100_82559_A_STEP 6
  38. #define E100_82559_B_STEP 7
  39. #define E100_82559_C_STEP 8
  40. #define E100_82559ER_A_STEP 9
  41. //-------------------------------------------------------------------------
  42. // D100 PORT functions -- lower 4 bits
  43. //-------------------------------------------------------------------------
  44. #define PORT_SOFTWARE_RESET 0
  45. #define PORT_SELFTEST 1
  46. #define PORT_SELECTIVE_RESET 2
  47. #define PORT_DUMP 3
  48. //-------------------------------------------------------------------------
  49. // CSR field definitions -- Offsets from CSR base
  50. //-------------------------------------------------------------------------
  51. #define SCB_STATUS_LOW_BYTE 0x0
  52. #define SCB_STATUS_HIGH_BYTE 0x1
  53. #define SCB_COMMAND_LOW_BYTE 0x2
  54. #define SCB_COMMAND_HIGH_BYTE 0x3
  55. #define SCB_GENERAL_POINTER 0x4
  56. #define CSR_PORT_LOW_WORD 0x8
  57. #define CSR_PORT_HIGH_WORD 0x0a
  58. #define CSR_FLASH_CONTROL_REG 0x0c
  59. #define CSR_EEPROM_CONTROL_REG 0x0e
  60. #define CSR_MDI_CONTROL_LOW_WORD 0x10
  61. #define CSR_MDI_CONTROL_HIGH_WORD 0x12
  62. //-------------------------------------------------------------------------
  63. // SCB Status Word bit definitions
  64. //-------------------------------------------------------------------------
  65. //- Interrupt status fields
  66. #define SCB_STATUS_MASK BIT_12_15 // ACK Mask
  67. #define SCB_STATUS_CX BIT_15 // CU Completed Action Cmd
  68. #define SCB_STATUS_FR BIT_14 // RU Received A Frame
  69. #define SCB_STATUS_CNA BIT_13 // CU Became Inactive (IDLE)
  70. #define SCB_STATUS_RNR BIT_12 // RU Became Not Ready
  71. #define SCB_STATUS_MDI BIT_11 // MDI read or write done
  72. #define SCB_STATUS_SWI BIT_10 // Software generated interrupt
  73. //- Interrupt ACK fields
  74. #define SCB_ACK_MASK (BIT_9 | BIT_12_15 | BIT_8) // ACK Mask
  75. #define SCB_ALL_INTERRUPT_BITS BIT_8_15 // if all the bits are set, no interrupt to be served
  76. #define SCB_ACK_CX BIT_15 // CU Completed Action Cmd
  77. #define SCB_ACK_FR BIT_14 // RU Received A Frame
  78. #define SCB_ACK_CNA BIT_13 // CU Became Inactive (IDLE)
  79. #define SCB_ACK_RNR BIT_12 // RU Became Not Ready
  80. #define SCB_ACK_MDI BIT_11 // MDI read or write done
  81. #define SCB_ACK_SWI BIT_10 // Software generated interrupt
  82. #define SCB_ACK_ER BIT_9 // Early Receive interrupt
  83. #define SCB_ACK_FCP BIT_8 // Flow Control Pause interrupt
  84. //- CUS Fields
  85. #define SCB_CUS_MASK (BIT_6 | BIT_7) // CUS 2-bit Mask
  86. #define SCB_CUS_IDLE 0 // CU Idle
  87. #define SCB_CUS_SUSPEND BIT_6 // CU Suspended
  88. #define SCB_CUS_ACTIVE BIT_7 // CU Active
  89. //- RUS Fields
  90. #define SCB_RUS_IDLE 0 // RU Idle
  91. #define SCB_RUS_MASK BIT_2_5 // RUS 3-bit Mask
  92. #define SCB_RUS_SUSPEND BIT_2 // RU Suspended
  93. #define SCB_RUS_NO_RESOURCES BIT_3 // RU Out Of Resources
  94. #define SCB_RUS_READY BIT_4 // RU Ready
  95. #define SCB_RUS_SUSP_NO_RBDS (BIT_2 | BIT_5) // RU No More RBDs
  96. #define SCB_RUS_NO_RBDS (BIT_3 | BIT_5) // RU No More RBDs
  97. #define SCB_RUS_READY_NO_RBDS (BIT_4 | BIT_5) // RU Ready, No RBDs
  98. //-------------------------------------------------------------------------
  99. // SCB Command Word bit definitions
  100. //-------------------------------------------------------------------------
  101. //- CUC fields
  102. #define SCB_CUC_MASK BIT_4_6 // CUC 3-bit Mask
  103. #define SCB_CUC_START BIT_4 // CU Start
  104. #define SCB_CUC_RESUME BIT_5 // CU Resume
  105. #define SCB_CUC_DUMP_ADDR BIT_6 // CU Dump Counters Address
  106. #define SCB_CUC_DUMP_STAT (BIT_4 | BIT_6) // CU Dump statistics counters
  107. #define SCB_CUC_LOAD_BASE (BIT_5 | BIT_6) // Load the CU base
  108. #define SCB_CUC_DUMP_RST_STAT BIT_4_6 // CU Dump and reset statistics counters
  109. #define SCB_CUC_STATIC_RESUME (BIT_5 | BIT_7) // CU Static Resume
  110. //- RUC fields
  111. #define SCB_RUC_MASK BIT_0_2 // RUC 3-bit Mask
  112. #define SCB_RUC_START BIT_0 // RU Start
  113. #define SCB_RUC_RESUME BIT_1 // RU Resume
  114. #define SCB_RUC_ABORT BIT_2 // RU Abort
  115. #define SCB_RUC_LOAD_HDS (BIT_0 | BIT_2) // Load RFD Header Data Size
  116. #define SCB_RUC_LOAD_BASE (BIT_1 | BIT_2) // Load the RU base
  117. #define SCB_RUC_RBD_RESUME BIT_0_2 // RBD resume
  118. // Interrupt fields (assuming byte addressing)
  119. #define SCB_INT_MASK BIT_0 // Mask interrupts
  120. #define SCB_SOFT_INT BIT_1 // Generate a software interrupt
  121. //-------------------------------------------------------------------------
  122. // EEPROM bit definitions
  123. //-------------------------------------------------------------------------
  124. //- EEPROM control register bits
  125. #define EN_TRNF 0x10 // Enable turnoff
  126. #define EEDO 0x08 // EEPROM data out
  127. #define EEDI 0x04 // EEPROM data in (set for writing data)
  128. #define EECS 0x02 // EEPROM chip select (1=high, 0=low)
  129. #define EESK 0x01 // EEPROM shift clock (1=high, 0=low)
  130. //- EEPROM opcodes
  131. #define EEPROM_READ_OPCODE 06
  132. #define EEPROM_WRITE_OPCODE 05
  133. #define EEPROM_ERASE_OPCODE 07
  134. #define EEPROM_EWEN_OPCODE 19 // Erase/write enable
  135. #define EEPROM_EWDS_OPCODE 16 // Erase/write disable
  136. //- EEPROM data locations
  137. #define EEPROM_NODE_ADDRESS_BYTE_0 0
  138. #define EEPROM_FLAGS_WORD_3 3
  139. #define EEPROM_FLAG_10MC BIT_0
  140. #define EEPROM_FLAG_100MC BIT_1
  141. //-------------------------------------------------------------------------
  142. // MDI Control register bit definitions
  143. //-------------------------------------------------------------------------
  144. #define MDI_DATA_MASK BIT_0_15 // MDI Data port
  145. #define MDI_REG_ADDR BIT_16_20 // which MDI register to read/write
  146. #define MDI_PHY_ADDR BIT_21_25 // which PHY to read/write
  147. #define MDI_PHY_OPCODE BIT_26_27 // which PHY to read/write
  148. #define MDI_PHY_READY BIT_28 // PHY is ready for another MDI cycle
  149. #define MDI_PHY_INT_ENABLE BIT_29 // Assert INT at MDI cycle completion
  150. //-------------------------------------------------------------------------
  151. // MDI Control register opcode definitions
  152. //-------------------------------------------------------------------------
  153. #define MDI_WRITE 1 // Phy Write
  154. #define MDI_READ 2 // Phy read
  155. //-------------------------------------------------------------------------
  156. // D100 Action Commands
  157. //-------------------------------------------------------------------------
  158. #define CB_NOP 0
  159. #define CB_IA_ADDRESS 1
  160. #define CB_CONFIGURE 2
  161. #define CB_MULTICAST 3
  162. #define CB_TRANSMIT 4
  163. #define CB_LOAD_MICROCODE 5
  164. #define CB_DUMP 6
  165. #define CB_DIAGNOSE 7
  166. //-------------------------------------------------------------------------
  167. // Command Block (CB) Field Definitions
  168. //-------------------------------------------------------------------------
  169. //- CB Command Word
  170. #define CB_EL_BIT BIT_15 // CB EL Bit
  171. #define CB_S_BIT BIT_14 // CB Suspend Bit
  172. #define CB_I_BIT BIT_13 // CB Interrupt Bit
  173. #define CB_TX_SF_BIT BIT_3 // TX CB Flexible Mode
  174. #define CB_CMD_MASK BIT_0_2 // CB 3-bit CMD Mask
  175. //- CB Status Word
  176. #define CB_STATUS_MASK BIT_12_15 // CB Status Mask (4-bits)
  177. #define CB_STATUS_COMPLETE BIT_15 // CB Complete Bit
  178. #define CB_STATUS_OK BIT_13 // CB OK Bit
  179. #define CB_STATUS_UNDERRUN BIT_12 // CB A Bit
  180. #define CB_STATUS_FAIL BIT_11 // CB Fail (F) Bit
  181. //misc command bits
  182. #define CB_TX_EOF_BIT BIT_15 // TX CB/TBD EOF Bit
  183. //-------------------------------------------------------------------------
  184. // Config CB Parameter Fields
  185. //-------------------------------------------------------------------------
  186. #define CB_CFIG_BYTE_COUNT 22 // 22 config bytes
  187. #define CB_SHORT_CFIG_BYTE_COUNT 8 // 8 config bytes
  188. // byte 0 bit definitions
  189. #define CB_CFIG_BYTE_COUNT_MASK BIT_0_5 // Byte count occupies bit 5-0
  190. // byte 1 bit definitions
  191. #define CB_CFIG_RXFIFO_LIMIT_MASK BIT_0_4 // RxFifo limit mask
  192. #define CB_CFIG_TXFIFO_LIMIT_MASK BIT_4_7 // TxFifo limit mask
  193. // byte 3 bit definitions --
  194. #define CB_CFIG_B3_MWI_ENABLE BIT_0 // Memory Write Invalidate Enable Bit
  195. // byte 4 bit definitions
  196. #define CB_CFIG_RX_MIN_DMA_MASK BIT_0_6 // Rx minimum DMA count mask
  197. // byte 5 bit definitions
  198. #define CB_CFIG_TX_MIN_DMA_MASK BIT_0_6 // Tx minimum DMA count mask
  199. #define CB_CFIG_DMBC_EN BIT_7 // Enable Tx/Rx minimum DMA counts
  200. // byte 6 bit definitions
  201. #define CB_CFIG_LATE_SCB BIT_0 // Update SCB After New Tx Start
  202. #define CB_CFIG_TNO_INT BIT_2 // Tx Not OK Interrupt
  203. #define CB_CFIG_CI_INT BIT_3 // Command Complete Interrupt
  204. #define CB_CFIG_SAVE_BAD_FRAMES BIT_7 // Save Bad Frames Enabled
  205. // byte 7 bit definitions
  206. #define CB_CFIG_DISC_SHORT_FRAMES BIT_0 // Discard Short Frames
  207. #define CB_CFIG_URUN_RETRY BIT_1_2 // Underrun Retry Count
  208. // byte 8 bit definitions
  209. #define CB_CFIG_503_MII BIT_0 // 503 vs. MII mode
  210. // byte 9 bit definitions -- pre-defined all zeros
  211. // byte 10 bit definitions
  212. #define CB_CFIG_NO_SRCADR BIT_3 // No Source Address Insertion
  213. #define CB_CFIG_PREAMBLE_LEN BIT_4_5 // Preamble Length
  214. #define CB_CFIG_LOOPBACK_MODE BIT_6_7 // Loopback Mode
  215. // byte 11 bit definitions
  216. #define CB_CFIG_LINEAR_PRIORITY BIT_0_2 // Linear Priority
  217. // byte 12 bit definitions
  218. #define CB_CFIG_LINEAR_PRI_MODE BIT_0 // Linear Priority mode
  219. #define CB_CFIG_IFS_MASK BIT_4_7 // CSMA level Interframe Spacing mask
  220. // byte 13 bit definitions -- pre-defined all zeros
  221. // byte 14 bit definitions -- pre-defined 0xf2
  222. // byte 15 bit definitions
  223. #define CB_CFIG_PROMISCUOUS BIT_0 // Promiscuous Mode Enable
  224. #define CB_CFIG_BROADCAST_DIS BIT_1 // Broadcast Mode Disable
  225. #define CB_CFIG_CRS_OR_CDT BIT_7 // CRS Or CDT
  226. // byte 16 bit definitions -- pre-defined all zeros
  227. // byte 17 bit definitions -- pre-defined 0x40
  228. // byte 18 bit definitions
  229. #define CB_CFIG_STRIPPING BIT_0 // Stripping Disabled
  230. #define CB_CFIG_PADDING BIT_1 // Padding Disabled
  231. #define CB_CFIG_CRC_IN_MEM BIT_2 // Transfer CRC To Memory
  232. // byte 19 bit definitions
  233. #define CB_CFIG_FORCE_FDX BIT_6 // Force Full Duplex
  234. #define CB_CFIG_FDX_ENABLE BIT_7 // Full Duplex Enabled
  235. // byte 20 bit definitions
  236. #define CB_CFIG_MULTI_IA BIT_6 // Multiple IA Addr
  237. // byte 21 bit definitions
  238. #define CB_CFIG_MULTICAST_ALL BIT_3 // Multicast All
  239. //-------------------------------------------------------------------------
  240. // Receive Frame Descriptor Fields
  241. //-------------------------------------------------------------------------
  242. //- RFD Status Bits
  243. #define RFD_RECEIVE_COLLISION BIT_0 // Collision detected on Receive
  244. #define RFD_IA_MATCH BIT_1 // Indv Address Match Bit
  245. #define RFD_RX_ERR BIT_4 // RX_ERR pin on Phy was set
  246. #define RFD_FRAME_TOO_SHORT BIT_7 // Receive Frame Short
  247. #define RFD_DMA_OVERRUN BIT_8 // Receive DMA Overrun
  248. #define RFD_NO_RESOURCES BIT_9 // No Buffer Space
  249. #define RFD_ALIGNMENT_ERROR BIT_10 // Alignment Error
  250. #define RFD_CRC_ERROR BIT_11 // CRC Error
  251. #define RFD_STATUS_OK BIT_13 // RFD OK Bit
  252. #define RFD_STATUS_COMPLETE BIT_15 // RFD Complete Bit
  253. //- RFD Command Bits
  254. #define RFD_EL_BIT BIT_15 // RFD EL Bit
  255. #define RFD_S_BIT BIT_14 // RFD Suspend Bit
  256. #define RFD_H_BIT BIT_4 // Header RFD Bit
  257. #define RFD_SF_BIT BIT_3 // RFD Flexible Mode
  258. //- RFD misc bits
  259. #define RFD_EOF_BIT BIT_15 // RFD End-Of-Frame Bit
  260. #define RFD_F_BIT BIT_14 // RFD Buffer Fetch Bit
  261. #define RFD_ACT_COUNT_MASK BIT_0_13 // RFD Actual Count Mask
  262. #define RFD_HEADER_SIZE 0x10 // Size of RFD Header (16 bytes)
  263. //-------------------------------------------------------------------------
  264. // Receive Buffer Descriptor Fields
  265. //-------------------------------------------------------------------------
  266. #define RBD_EOF_BIT BIT_15 // RBD End-Of-Frame Bit
  267. #define RBD_F_BIT BIT_14 // RBD Buffer Fetch Bit
  268. #define RBD_ACT_COUNT_MASK BIT_0_13 // RBD Actual Count Mask
  269. #define SIZE_FIELD_MASK BIT_0_13 // Size of the associated buffer
  270. #define RBD_EL_BIT BIT_15 // RBD EL Bit
  271. //-------------------------------------------------------------------------
  272. // Size Of Dump Buffer
  273. //-------------------------------------------------------------------------
  274. #define DUMP_BUFFER_SIZE 600 // size of the dump buffer
  275. //-------------------------------------------------------------------------
  276. // Self Test Results
  277. //-------------------------------------------------------------------------
  278. #define CB_SELFTEST_FAIL_BIT BIT_12
  279. #define CB_SELFTEST_DIAG_BIT BIT_5
  280. #define CB_SELFTEST_REGISTER_BIT BIT_3
  281. #define CB_SELFTEST_ROM_BIT BIT_2
  282. #define CB_SELFTEST_ERROR_MASK ( \
  283. CB_SELFTEST_FAIL_BIT | CB_SELFTEST_DIAG_BIT | \
  284. CB_SELFTEST_REGISTER_BIT | CB_SELFTEST_ROM_BIT)
  285. //-------------------------------------------------------------------------
  286. // Driver Configuration Default Parameters for the 557
  287. // Note: If the driver uses any defaults that are different from the chip's
  288. // defaults, it will be noted below
  289. //-------------------------------------------------------------------------
  290. // Byte 0 (byte count) default
  291. #define CB_557_CFIG_DEFAULT_PARM0 CB_CFIG_BYTE_COUNT
  292. // Byte 1 (fifo limits) default
  293. #define DEFAULT_TX_FIFO_LIMIT 0x08
  294. #define DEFAULT_RX_FIFO_LIMIT 0x08
  295. #define CB_557_CFIG_DEFAULT_PARM1 0x88
  296. // Byte 2 (IFS) default
  297. #define CB_557_CFIG_DEFAULT_PARM2 0x00
  298. // Byte 3 (reserved) default
  299. #define CB_557_CFIG_DEFAULT_PARM3 0x00
  300. // Byte 4 (Rx DMA min count) default
  301. #define CB_557_CFIG_DEFAULT_PARM4 0x00
  302. // Byte 5 (Tx DMA min count, DMA min count enable) default
  303. #define CB_557_CFIG_DEFAULT_PARM5 0x00
  304. // Byte 6 (Late SCB, TNO int, CI int, Save bad frames) default
  305. #define CB_557_CFIG_DEFAULT_PARM6 0x32
  306. // Byte 7 (Discard short frames, underrun retry) default
  307. // note: disc short frames will be enabled
  308. #define DEFAULT_UNDERRUN_RETRY 0x01
  309. #define CB_557_CFIG_DEFAULT_PARM7 0x01
  310. // Byte 8 (MII or 503) default
  311. // note: MII will be the default
  312. #define CB_557_CFIG_DEFAULT_PARM8 0x01
  313. // Byte 9 - Power management for 82558B, 82559
  314. #define CB_WAKE_ON_LINK_BYTE9 0x20
  315. #define CB_WAKE_ON_ARP_PKT_BYTE9 0x40
  316. #define CB_557_CFIG_DEFAULT_PARM9 0
  317. // Byte 10 (scr addr insertion, preamble, loopback) default
  318. #define CB_557_CFIG_DEFAULT_PARM10 0x2e
  319. // Byte 11 (linear priority) default
  320. #define CB_557_CFIG_DEFAULT_PARM11 0x00
  321. // Byte 12 (IFS,linear priority mode) default
  322. #define CB_557_CFIG_DEFAULT_PARM12 0x60
  323. // Byte 13 (reserved) default
  324. #define CB_557_CFIG_DEFAULT_PARM13 0x00
  325. // Byte 14 (reserved) default
  326. #define CB_557_CFIG_DEFAULT_PARM14 0xf2
  327. // Byte 15 (promiscuous, broadcast, CRS/CDT) default
  328. #define CB_557_CFIG_DEFAULT_PARM15 0xea
  329. // Byte 16 (reserved) default
  330. #define CB_557_CFIG_DEFAULT_PARM16 0x00
  331. // Byte 17 (reserved) default
  332. #define CB_557_CFIG_DEFAULT_PARM17 0x40
  333. // Byte 18 (Stripping, padding, Rcv CRC in mem) default
  334. // note: padding will be enabled
  335. #define CB_557_CFIG_DEFAULT_PARM18 0xf2
  336. // Byte 19 (reserved) default
  337. // note: full duplex is enabled if FDX# pin is 0
  338. #define CB_557_CFIG_DEFAULT_PARM19 0x80
  339. // Byte 20 (multi-IA) default
  340. #define CB_557_CFIG_DEFAULT_PARM20 0x3f
  341. // Byte 21 (multicast all) default
  342. #define CB_557_CFIG_DEFAULT_PARM21 0x05
  343. #pragma pack(1)
  344. //-------------------------------------------------------------------------
  345. // Ethernet Frame Structure
  346. //-------------------------------------------------------------------------
  347. //- Ethernet 6-byte Address
  348. typedef struct _ETH_ADDRESS_STRUC {
  349. UCHAR EthNodeAddress[ETHERNET_ADDRESS_LENGTH];
  350. } ETH_ADDRESS_STRUC, *PETH_ADDRESS_STRUC;
  351. //- Ethernet 14-byte Header
  352. typedef struct _ETH_HEADER_STRUC {
  353. UCHAR Destination[ETHERNET_ADDRESS_LENGTH];
  354. UCHAR Source[ETHERNET_ADDRESS_LENGTH];
  355. USHORT TypeLength;
  356. } ETH_HEADER_STRUC, *PETH_HEADER_STRUC;
  357. //- Ethernet Buffer (Including Ethernet Header) for Transmits
  358. typedef struct _ETH_TX_BUFFER_STRUC {
  359. ETH_HEADER_STRUC TxMacHeader;
  360. UCHAR TxBufferData[(TCB_BUFFER_SIZE - sizeof(ETH_HEADER_STRUC))];
  361. } ETH_TX_BUFFER_STRUC, *PETH_TX_BUFFER_STRUC;
  362. typedef struct _ETH_RX_BUFFER_STRUC {
  363. ETH_HEADER_STRUC RxMacHeader;
  364. UCHAR RxBufferData[(RCB_BUFFER_SIZE - sizeof(ETH_HEADER_STRUC))];
  365. } ETH_RX_BUFFER_STRUC, *PETH_RX_BUFFER_STRUC;
  366. //-------------------------------------------------------------------------
  367. // 82557 Data Structures
  368. //-------------------------------------------------------------------------
  369. //-------------------------------------------------------------------------
  370. // Self test
  371. //-------------------------------------------------------------------------
  372. typedef struct _SELF_TEST_STRUC {
  373. ULONG StSignature; // Self Test Signature
  374. ULONG StResults; // Self Test Results
  375. } SELF_TEST_STRUC, *PSELF_TEST_STRUC;
  376. //-------------------------------------------------------------------------
  377. // Control/Status Registers (CSR)
  378. //-------------------------------------------------------------------------
  379. typedef struct _CSR_STRUC {
  380. USHORT ScbStatus; // SCB Status register
  381. UCHAR ScbCommandLow; // SCB Command register (low byte)
  382. UCHAR ScbCommandHigh; // SCB Command register (high byte)
  383. ULONG ScbGeneralPointer; // SCB General pointer
  384. ULONG Port; // PORT register
  385. USHORT FlashControl; // Flash Control register
  386. USHORT EepromControl; // EEPROM control register
  387. ULONG MDIControl; // MDI Control Register
  388. ULONG RxDMAByteCount; // Receive DMA Byte count register
  389. } CSR_STRUC, *PCSR_STRUC;
  390. //-------------------------------------------------------------------------
  391. // Error Counters
  392. //-------------------------------------------------------------------------
  393. typedef struct _ERR_COUNT_STRUC {
  394. ULONG XmtGoodFrames; // Good frames transmitted
  395. ULONG XmtMaxCollisions; // Fatal frames -- had max collisions
  396. ULONG XmtLateCollisions; // Fatal frames -- had a late coll.
  397. ULONG XmtUnderruns; // Transmit underruns (fatal or re-transmit)
  398. ULONG XmtLostCRS; // Frames transmitted without CRS
  399. ULONG XmtDeferred; // Deferred transmits
  400. ULONG XmtSingleCollision; // Transmits that had 1 and only 1 coll.
  401. ULONG XmtMultCollisions; // Transmits that had multiple coll.
  402. ULONG XmtTotalCollisions; // Transmits that had 1+ collisions.
  403. ULONG RcvGoodFrames; // Good frames received
  404. ULONG RcvCrcErrors; // Aligned frames that had a CRC error
  405. ULONG RcvAlignmentErrors; // Receives that had alignment errors
  406. ULONG RcvResourceErrors; // Good frame dropped due to lack of resources
  407. ULONG RcvOverrunErrors; // Overrun errors - bus was busy
  408. ULONG RcvCdtErrors; // Received frames that encountered coll.
  409. ULONG RcvShortFrames; // Received frames that were to short
  410. ULONG CommandComplete; // A005h indicates cmd completion
  411. } ERR_COUNT_STRUC, *PERR_COUNT_STRUC;
  412. //-------------------------------------------------------------------------
  413. // Command Block (CB) Generic Header Structure
  414. //-------------------------------------------------------------------------
  415. typedef struct _CB_HEADER_STRUC {
  416. USHORT CbStatus; // Command Block Status
  417. USHORT CbCommand; // Command Block Command
  418. ULONG CbLinkPointer; // Link To Next CB
  419. } CB_HEADER_STRUC, *PCB_HEADER_STRUC;
  420. //-------------------------------------------------------------------------
  421. // NOP Command Block (NOP_CB)
  422. //-------------------------------------------------------------------------
  423. typedef struct _NOP_CB_STRUC {
  424. CB_HEADER_STRUC NopCBHeader;
  425. } NOP_CB_STRUC, *PNOP_CB_STRUC;
  426. //-------------------------------------------------------------------------
  427. // Individual Address Command Block (IA_CB)
  428. //-------------------------------------------------------------------------
  429. typedef struct _IA_CB_STRUC {
  430. CB_HEADER_STRUC IaCBHeader;
  431. UCHAR IaAddress[ETHERNET_ADDRESS_LENGTH];
  432. } IA_CB_STRUC, *PIA_CB_STRUC;
  433. //-------------------------------------------------------------------------
  434. // Configure Command Block (CONFIG_CB)
  435. //-------------------------------------------------------------------------
  436. typedef struct _CONFIG_CB_STRUC {
  437. CB_HEADER_STRUC ConfigCBHeader;
  438. UCHAR ConfigBytes[CB_CFIG_BYTE_COUNT];
  439. } CONFIG_CB_STRUC, *PCONFIG_CB_STRUC;
  440. //-------------------------------------------------------------------------
  441. // MultiCast Command Block (MULTICAST_CB)
  442. //-------------------------------------------------------------------------
  443. typedef struct _MULTICAST_CB_STRUC {
  444. CB_HEADER_STRUC McCBHeader;
  445. USHORT McCount; // Number of multicast addresses
  446. UCHAR McAddress[(ETHERNET_ADDRESS_LENGTH * MAX_MULTICAST_ADDRESSES)];
  447. } MULTICAST_CB_STRUC, *PMULTICAST_CB_STRUC;
  448. //-------------------------------------------------------------------------
  449. // WakeUp Filter Command Block (FILTER_CB)
  450. //-------------------------------------------------------------------------
  451. typedef struct _FILTER_CB_STRUC {
  452. CB_HEADER_STRUC FilterCBHeader;
  453. ULONG Pattern[16];
  454. }FILTER_CB_STRUC , *PFILTER_CB_STRUC ;
  455. //-------------------------------------------------------------------------
  456. // Dump Command Block (DUMP_CB)
  457. //-------------------------------------------------------------------------
  458. typedef struct _DUMP_CB_STRUC {
  459. CB_HEADER_STRUC DumpCBHeader;
  460. ULONG DumpAreaAddress; // Dump Buffer Area Address
  461. } DUMP_CB_STRUC, *PDUMP_CB_STRUC;
  462. //-------------------------------------------------------------------------
  463. // Dump Area structure definition
  464. //-------------------------------------------------------------------------
  465. typedef struct _DUMP_AREA_STRUC {
  466. UCHAR DumpBuffer[DUMP_BUFFER_SIZE];
  467. } DUMP_AREA_STRUC, *PDUMP_AREA_STRUC;
  468. //-------------------------------------------------------------------------
  469. // Diagnose Command Block (DIAGNOSE_CB)
  470. //-------------------------------------------------------------------------
  471. typedef struct _DIAGNOSE_CB_STRUC {
  472. CB_HEADER_STRUC DiagCBHeader;
  473. } DIAGNOSE_CB_STRUC, *PDIAGNOSE_CB_STRUC;
  474. //-------------------------------------------------------------------------
  475. // Transmit Command Block (TxCB)
  476. //-------------------------------------------------------------------------
  477. typedef struct _GENERIC_TxCB {
  478. CB_HEADER_STRUC TxCbHeader;
  479. ULONG TxCbTbdPointer; // TBD address
  480. USHORT TxCbCount; // Data Bytes In TCB past header
  481. UCHAR TxCbThreshold; // TX Threshold for FIFO Extender
  482. UCHAR TxCbTbdNumber;
  483. ETH_TX_BUFFER_STRUC TxCbData;
  484. ULONG pad0;
  485. ULONG pad1;
  486. ULONG pad2;
  487. ULONG pad3;
  488. } TXCB_STRUC, *PTXCB_STRUC;
  489. //-------------------------------------------------------------------------
  490. // Transmit Buffer Descriptor (TBD)
  491. //-------------------------------------------------------------------------
  492. typedef struct _TBD_STRUC {
  493. ULONG TbdBufferAddress; // Physical Transmit Buffer Address
  494. unsigned TbdCount :14;
  495. unsigned :1 ; // always 0
  496. unsigned EndOfList:1 ; // EL bit in Tbd
  497. unsigned :16; // field that is always 0's in a TBD
  498. } TBD_STRUC, *PTBD_STRUC;
  499. //-------------------------------------------------------------------------
  500. // Receive Frame Descriptor (RFD)
  501. //-------------------------------------------------------------------------
  502. typedef struct _RFD_STRUC {
  503. CB_HEADER_STRUC RfdCbHeader;
  504. ULONG RfdRbdPointer; // Receive Buffer Descriptor Addr
  505. USHORT RfdActualCount; // Number Of Bytes Received
  506. USHORT RfdSize; // Number Of Bytes In RFD
  507. ETH_RX_BUFFER_STRUC RfdBuffer; // Data buffer in RFD
  508. } RFD_STRUC, *PRFD_STRUC;
  509. //-------------------------------------------------------------------------
  510. // Receive Buffer Descriptor (RBD)
  511. //-------------------------------------------------------------------------
  512. typedef struct _RBD_STRUC {
  513. USHORT RbdActualCount; // Number Of Bytes Received
  514. USHORT RbdFiller;
  515. ULONG RbdLinkAddress; // Link To Next RBD
  516. ULONG RbdRcbAddress; // Receive Buffer Address
  517. USHORT RbdSize; // Receive Buffer Size
  518. USHORT RbdFiller1;
  519. } RBD_STRUC, *PRBD_STRUC;
  520. #pragma pack()
  521. //-------------------------------------------------------------------------
  522. // 82557 PCI Register Definitions
  523. // Refer To The PCI Specification For Detailed Explanations
  524. //-------------------------------------------------------------------------
  525. //- Register Offsets
  526. #define PCI_VENDOR_ID_REGISTER 0x00 // PCI Vendor ID Register
  527. #define PCI_DEVICE_ID_REGISTER 0x02 // PCI Device ID Register
  528. #define PCI_CONFIG_ID_REGISTER 0x00 // PCI Configuration ID Register
  529. #define PCI_COMMAND_REGISTER 0x04 // PCI Command Register
  530. #define PCI_STATUS_REGISTER 0x06 // PCI Status Register
  531. #define PCI_REV_ID_REGISTER 0x08 // PCI Revision ID Register
  532. #define PCI_CLASS_CODE_REGISTER 0x09 // PCI Class Code Register
  533. #define PCI_CACHE_LINE_REGISTER 0x0C // PCI Cache Line Register
  534. #define PCI_LATENCY_TIMER 0x0D // PCI Latency Timer Register
  535. #define PCI_HEADER_TYPE 0x0E // PCI Header Type Register
  536. #define PCI_BIST_REGISTER 0x0F // PCI Built-In SelfTest Register
  537. #define PCI_BAR_0_REGISTER 0x10 // PCI Base Address Register 0
  538. #define PCI_BAR_1_REGISTER 0x14 // PCI Base Address Register 1
  539. #define PCI_BAR_2_REGISTER 0x18 // PCI Base Address Register 2
  540. #define PCI_BAR_3_REGISTER 0x1C // PCI Base Address Register 3
  541. #define PCI_BAR_4_REGISTER 0x20 // PCI Base Address Register 4
  542. #define PCI_BAR_5_REGISTER 0x24 // PCI Base Address Register 5
  543. #define PCI_SUBVENDOR_ID_REGISTER 0x2C // PCI SubVendor ID Register
  544. #define PCI_SUBDEVICE_ID_REGISTER 0x2E // PCI SubDevice ID Register
  545. #define PCI_EXPANSION_ROM 0x30 // PCI Expansion ROM Base Register
  546. #define PCI_INTERRUPT_LINE 0x3C // PCI Interrupt Line Register
  547. #define PCI_INTERRUPT_PIN 0x3D // PCI Interrupt Pin Register
  548. #define PCI_MIN_GNT_REGISTER 0x3E // PCI Min-Gnt Register
  549. #define PCI_MAX_LAT_REGISTER 0x3F // PCI Max_Lat Register
  550. #define PCI_NODE_ADDR_REGISTER 0x40 // PCI Node Address Register
  551. //-------------------------------------------------------------------------
  552. // PHY 100 MDI Register/Bit Definitions
  553. //-------------------------------------------------------------------------
  554. // MDI register set
  555. #define MDI_CONTROL_REG 0x00 // MDI control register
  556. #define MDI_STATUS_REG 0x01 // MDI Status regiser
  557. #define PHY_ID_REG_1 0x02 // Phy indentification reg (word 1)
  558. #define PHY_ID_REG_2 0x03 // Phy indentification reg (word 2)
  559. #define AUTO_NEG_ADVERTISE_REG 0x04 // Auto-negotiation advertisement
  560. #define AUTO_NEG_LINK_PARTNER_REG 0x05 // Auto-negotiation link partner ability
  561. #define AUTO_NEG_EXPANSION_REG 0x06 // Auto-negotiation expansion
  562. #define AUTO_NEG_NEXT_PAGE_REG 0x07 // Auto-negotiation next page transmit
  563. #define EXTENDED_REG_0 0x10 // Extended reg 0 (Phy 100 modes)
  564. #define EXTENDED_REG_1 0x14 // Extended reg 1 (Phy 100 error indications)
  565. #define NSC_CONG_CONTROL_REG 0x17 // National (TX) congestion control
  566. #define NSC_SPEED_IND_REG 0x19 // National (TX) speed indication
  567. #define PHY_EQUALIZER_REG 0x1A // Register for the Phy Equalizer values
  568. // MDI Control register bit definitions
  569. #define MDI_CR_COLL_TEST_ENABLE BIT_7 // Collision test enable
  570. #define MDI_CR_FULL_HALF BIT_8 // FDX =1, half duplex =0
  571. #define MDI_CR_RESTART_AUTO_NEG BIT_9 // Restart auto negotiation
  572. #define MDI_CR_ISOLATE BIT_10 // Isolate PHY from MII
  573. #define MDI_CR_POWER_DOWN BIT_11 // Power down
  574. #define MDI_CR_AUTO_SELECT BIT_12 // Auto speed select enable
  575. #define MDI_CR_10_100 BIT_13 // 0 = 10Mbs, 1 = 100Mbs
  576. #define MDI_CR_LOOPBACK BIT_14 // 0 = normal, 1 = loopback
  577. #define MDI_CR_RESET BIT_15 // 0 = normal, 1 = PHY reset
  578. // MDI Status register bit definitions
  579. #define MDI_SR_EXT_REG_CAPABLE BIT_0 // Extended register capabilities
  580. #define MDI_SR_JABBER_DETECT BIT_1 // Jabber detected
  581. #define MDI_SR_LINK_STATUS BIT_2 // Link Status -- 1 = link
  582. #define MDI_SR_AUTO_SELECT_CAPABLE BIT_3 // Auto speed select capable
  583. #define MDI_SR_REMOTE_FAULT_DETECT BIT_4 // Remote fault detect
  584. #define MDI_SR_AUTO_NEG_COMPLETE BIT_5 // Auto negotiation complete
  585. #define MDI_SR_10T_HALF_DPX BIT_11 // 10BaseT Half Duplex capable
  586. #define MDI_SR_10T_FULL_DPX BIT_12 // 10BaseT full duplex capable
  587. #define MDI_SR_TX_HALF_DPX BIT_13 // TX Half Duplex capable
  588. #define MDI_SR_TX_FULL_DPX BIT_14 // TX full duplex capable
  589. #define MDI_SR_T4_CAPABLE BIT_15 // T4 capable
  590. // Auto-Negotiation advertisement register bit definitions
  591. #define NWAY_AD_SELCTOR_FIELD BIT_0_4 // identifies supported protocol
  592. #define NWAY_AD_ABILITY BIT_5_12 // technologies that are supported
  593. #define NWAY_AD_10T_HALF_DPX BIT_5 // 10BaseT Half Duplex capable
  594. #define NWAY_AD_10T_FULL_DPX BIT_6 // 10BaseT full duplex capable
  595. #define NWAY_AD_TX_HALF_DPX BIT_7 // TX Half Duplex capable
  596. #define NWAY_AD_TX_FULL_DPX BIT_8 // TX full duplex capable
  597. #define NWAY_AD_T4_CAPABLE BIT_9 // T4 capable
  598. #define NWAY_AD_REMOTE_FAULT BIT_13 // indicates local remote fault
  599. #define NWAY_AD_RESERVED BIT_14 // reserved
  600. #define NWAY_AD_NEXT_PAGE BIT_15 // Next page (not supported)
  601. // Auto-Negotiation link partner ability register bit definitions
  602. #define NWAY_LP_SELCTOR_FIELD BIT_0_4 // identifies supported protocol
  603. #define NWAY_LP_ABILITY BIT_5_9 // technologies that are supported
  604. #define NWAY_LP_REMOTE_FAULT BIT_13 // indicates partner remote fault
  605. #define NWAY_LP_ACKNOWLEDGE BIT_14 // acknowledge
  606. #define NWAY_LP_NEXT_PAGE BIT_15 // Next page (not supported)
  607. // Auto-Negotiation expansion register bit definitions
  608. #define NWAY_EX_LP_NWAY BIT_0 // link partner is NWAY
  609. #define NWAY_EX_PAGE_RECEIVED BIT_1 // link code word received
  610. #define NWAY_EX_NEXT_PAGE_ABLE BIT_2 // local is next page able
  611. #define NWAY_EX_LP_NEXT_PAGE_ABLE BIT_3 // partner is next page able
  612. #define NWAY_EX_PARALLEL_DET_FLT BIT_4 // parallel detection fault
  613. #define NWAY_EX_RESERVED BIT_5_15 // reserved
  614. // PHY 100 Extended Register 0 bit definitions
  615. #define PHY_100_ER0_FDX_INDIC BIT_0 // 1 = FDX, 0 = half duplex
  616. #define PHY_100_ER0_SPEED_INDIC BIT_1 // 1 = 100mbs, 0= 10mbs
  617. #define PHY_100_ER0_WAKE_UP BIT_2 // Wake up DAC
  618. #define PHY_100_ER0_RESERVED BIT_3_4 // Reserved
  619. #define PHY_100_ER0_REV_CNTRL BIT_5_7 // Revsion control (A step = 000)
  620. #define PHY_100_ER0_FORCE_FAIL BIT_8 // Force Fail is enabled
  621. #define PHY_100_ER0_TEST BIT_9_13 // Revsion control (A step = 000)
  622. #define PHY_100_ER0_LINKDIS BIT_14 // Link integrity test is disabled
  623. #define PHY_100_ER0_JABDIS BIT_15 // Jabber function is disabled
  624. // PHY 100 Extended Register 1 bit definitions
  625. #define PHY_100_ER1_RESERVED BIT_0_8 // Reserved
  626. #define PHY_100_ER1_CH2_DET_ERR BIT_9 // Channel 2 EOF detection error
  627. #define PHY_100_ER1_MANCH_CODE_ERR BIT_10 // Manchester code error
  628. #define PHY_100_ER1_EOP_ERR BIT_11 // EOP error
  629. #define PHY_100_ER1_BAD_CODE_ERR BIT_12 // bad code error
  630. #define PHY_100_ER1_INV_CODE_ERR BIT_13 // invalid code error
  631. #define PHY_100_ER1_DC_BAL_ERR BIT_14 // DC balance error
  632. #define PHY_100_ER1_PAIR_SKEW_ERR BIT_15 // Pair skew error
  633. // PHY TX Register/Bit definitions
  634. #define PHY_TX_STATUS_CTRL_REG 0x10
  635. #define PHY_TX_POLARITY_MASK BIT_8 // register 10h bit 8 (the polarity bit)
  636. #define PHY_TX_NORMAL_POLARITY 0 // register 10h bit 8 =0 (normal polarity)
  637. #define PHY_TX_SPECIAL_CTRL_REG 0x11
  638. #define AUTO_POLARITY_DISABLE BIT_4 // register 11h bit 4 (0=enable, 1=disable)
  639. #define PHY_TX_REG_18 0x18 // Error counter register
  640. // National Semiconductor TX phy congestion control register bit definitions
  641. #define NSC_TX_CONG_TXREADY BIT_10 // Makes TxReady an input
  642. #define NSC_TX_CONG_ENABLE BIT_8 // Enables congestion control
  643. #define NSC_TX_CONG_F_CONNECT BIT_5 // Enables congestion control
  644. // National Semiconductor TX phy speed indication register bit definitions
  645. #define NSC_TX_SPD_INDC_SPEED BIT_6 // 0 = 100mb, 1=10mb
  646. #endif // _E100_557_H