Leaked source code of windows server 2003
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  1. #ifndef CHECK_H_INCLUDED
  2. #define CHECK_H_INCLUDED
  3. //###########################################################################
  4. //**
  5. //** Copyright (C) 1996-99 Intel Corporation. All rights reserved.
  6. //**
  7. //** The information and source code contained herein is the exclusive
  8. //** property of Intel Corporation and may not be disclosed, examined
  9. //** or reproduced in whole or in part without explicit written authorization
  10. //** from the company.
  11. //**
  12. //###########################################################################
  13. //-----------------------------------------------------------------------------
  14. // Version control information follows.
  15. //
  16. // $Header: /dev/SAL/INCLUDE/check.h 3 4/21/00 12:52p Mganesan $
  17. // $Log: /dev/SAL/INCLUDE/check.h $
  18. //
  19. // 3 4/21/00 12:52p Mganesan
  20. // Sync Up SAL 5.8
  21. //
  22. // Rev 1.8 18 Jun 1999 16:29:00 smariset
  23. //
  24. //
  25. // Rev 1.7 08 Jun 1999 11:29:04 smariset
  26. //Added Fatal Error Define
  27. //
  28. // Rev 1.6 14 May 1999 09:01:26 smariset
  29. //removal of tabs
  30. //
  31. // Rev 1.5 07 May 1999 11:27:16 smariset
  32. //Copyright update and Platform Record Hdr. Update
  33. //
  34. // Rev 1.4 06 May 1999 16:06:42 smariset
  35. //PSI Record Valid Bits Change (No bnk Regs)
  36. //
  37. // Rev 1.3 05 May 1999 14:13:12 smariset
  38. //Pre Fresh Build
  39. //
  40. // Rev 1.2 24 Mar 1999 09:40:06 smariset
  41. //
  42. //
  43. // Rev 1.1 09 Mar 1999 13:12:52 smariset
  44. //updated
  45. //
  46. // Rev 1.0 09 Mar 1999 10:02:28 smariset
  47. //First time check
  48. //
  49. //*****************************************************************************//
  50. // #define _INTEL_CHECK_H 1
  51. #if defined(_INTEL_CHECK_H)
  52. #define OEM_RECID_CMOS_RAM_ADDR 64 // OEM should define this
  53. #define INIT_IPI_VECTOR 0x500
  54. // SAL_MC_SET_PARAMS
  55. #define RZ_VECTOR 0xf3
  56. #define WKP_VECTOR 0x12 // Rendz. wakeup interrupt vector (IA-32 MCHK Exception Vector)
  57. #define CMC_VECTOR 0xf2 //
  58. #define TIMEOUT 1000
  59. #endif // _INTEL_CHECK_H
  60. #define IntrVecType 0x01
  61. #define MemSemType 0x02
  62. #define RendzType 0x01
  63. #define WakeUpType 0x02
  64. #define CpevType 0x03
  65. // SAL_SET_VECTORS
  66. #define MchkEvent 0x00
  67. #define InitEvent 0x01
  68. #define BootRzEvent 0x02
  69. #if defined(_INTEL_CHECK_H)
  70. #define ProcCmcEvent 0x02
  71. #define PlatCmcEvent 0x03
  72. #define OsMcaSize 0x20
  73. #define OsInitSize 0x20
  74. // Misc. Flags
  75. #define OS_FLAG 0x03
  76. #define OEM_FLAG 0x04
  77. // Record Type
  78. #define PROC_RECORD 0x00
  79. #define PLAT_RECORD 0x01
  80. #define NUM_PROC 0x04 // number of processors
  81. #define PSI_REC_VERSION 0x01 // 0.01
  82. // Oem SubTypes
  83. #define MEM_Record 0x00
  84. #define BUS_Record 0x02
  85. #define COMP_Record 0x04
  86. #define SEL_Record 0x08
  87. // Record valid flags
  88. #define MEM_Record_VALID 0x00
  89. #define BUS_Record_VALID 0x02
  90. #define COMP_Record_VALID 0x04
  91. #define SEL_Record_VALID 0x08
  92. #define RdNvmRecord 0x00
  93. #define WrNvmRecord 0x01
  94. #define ClrNvmRecord 0x02
  95. #define ChkIfMoreNvmRecord 0x03
  96. #else // !_INTEL_CHECK_H
  97. // SAL 0800: Reserved 0x03-0x40
  98. // SAL STATE_INFO
  99. //
  100. // Thierry 08/2000 - WARNING:
  101. // These definitions match the ntos\inc\hal.h definitions for KERNEL_MCE_DELIVERY.Reserved.EVENTYPE.
  102. //
  103. #define MCA_EVENT 0x00 // MCA Event Information
  104. #define INIT_EVENT 0x01 // INIT Event Information
  105. #define CMC_EVENT 0x02 // Processor CMC Event Information
  106. #define CPE_EVENT 0x03 // Corrected Platform Event Information
  107. // SAL 0800: Reserved other values...
  108. #endif // !_INTEL_CHECK_H
  109. // // constant defines
  110. // Processor State Parameter error conditions from PAL in GR20
  111. // Processor State Parameters from PAL during machine check bit position
  112. #define PSPrz 2 // Rendez Request Success
  113. #define PSPra 3 // Rendez Attempted
  114. #define PSPme 4
  115. #define PSPmn 5
  116. #define PSPsy 6 // storage inetgrity
  117. #define PSPco 7 // continuable error
  118. #define PSPci 8 // contained error, recovery possible
  119. #define PSPus 9 // uncontained memory failure
  120. #define PSPhd 10 // damaged hardware
  121. #define PSPtl 11
  122. #define PSPmi 12
  123. #define PSPpi 13
  124. #define PSPpm 14
  125. #define PSPdy 15
  126. #define PSPin 16
  127. #define PSPrs 17
  128. #define PSPcm 18 // machine check corrected
  129. #define PSPex 19 // machine check expected
  130. #define PSPcr 20
  131. #define PSPpc 21
  132. #define PSPdr 22
  133. #define PSPtr 23
  134. #define PSPrr 24
  135. #define PSPar 25
  136. #define PSPbr 26
  137. #define PSPpr 27
  138. #define PSPfp 28
  139. #define PSPb1 29
  140. #define PSPb0 30
  141. #define PSPgr 31
  142. #define PSPcc 59 // cache check, SAL's domain
  143. #define PSPtc 60 // tlb check error, SAL's domain
  144. #define PSPbc 61 // bus check error, SAL's domain
  145. #define PSPrc 62 // register file check error, SAL's domain
  146. #define PSPuc 63 // unknown error, SAL's domain
  147. #define BusChktv 21 // Bus check.tv bit or bus error info
  148. #define CacheChktv 23
  149. #if defined(_INTEL_CHECK_H)
  150. // SAL PSI Validation flag bit mask
  151. #define vPSIpe 0x01<<0 // start bit pos. for processor error map
  152. #define vPSIps 0x01<<1
  153. #define vPSIid 0x01<<2 // processor LID register value
  154. #define vPSIStatic 0x01<<3 // processor static info.
  155. #define vPSIcc 0x01<<4 // start bit pos. for cache error
  156. #define vPSItc 0x01<<8 // start bit pos. for tlb errors
  157. #define vPSIbc 0x01<<12 // bus check valid bit
  158. #define vPSIrf 0x01<<16 // register file check valid bit
  159. #define vPSIms 0x01<<20 // ms check valid bit
  160. // Valid bit flags for CR and AR registers for this generation of EM Processor
  161. #define vPSIMinState 0x01<<0
  162. #define vPSIBRs 0x01<<1
  163. #define vPSICRs 0x01<<2
  164. #define vPSIARs 0x01<<3
  165. #define vPSIRRs 0x01<<4
  166. #define vPSIFRs 0x01<<5
  167. #define vPSIRegs vPSIBRs+vPSICRs+vPSIARs+vPSIRRs+vPSIMinState
  168. ///*** All Processor PAL call specific info.
  169. // Processor Error Info Type Index for PAL_MC_ERROR_INFO call
  170. #define PROC_ERROR_MAP 0 // index for Proc. error map
  171. #define PROC_STATE_PARAM 1 // index for Proc. state parameter
  172. #define PROC_STRUCT 2 // index for structure specific error info.
  173. #define PEIsse 0 // index for Proc. structure specific level index
  174. #define PEIta 1 // index for target identifer
  175. #define PEIrq 2 // index for requestor
  176. #define PEIrs 3 // index for responder
  177. #define PEIip 4 // index for precise IP
  178. // processor error map starting bit positions for each field (level index)
  179. #define PEMcid 0 // core ID
  180. #define PEMtid 4 // thread ID
  181. #define PEMeic 8 // inst. cache error index
  182. #define PEMedc 12 // data cache error index
  183. #define PEMeit 16 // inst. tlb error index
  184. #define PEMedt 20 // data tlb error index
  185. #define PEMebh 24 // bus error index
  186. #define PEMerf 28 // register file error index
  187. #define PEMems 32 // micro-arch error index
  188. // processor structure specific error bit mappings
  189. #define PEtv 0x01<<60 // valid target identifier
  190. #define PErq 0x01<<61 // valid request identifier
  191. #define PErp 0x01<<62 // valid responder identifier
  192. #define PEpi 0x01<<63 // valid precise IP
  193. // Error Severity: using bits (cm) & (us) only
  194. #define RECOVERABLE 0x00
  195. #define FATAL 0x01
  196. #define CONTINUABLE 0x02
  197. #define BCib 0x05
  198. #define BCeb 0x06
  199. #else // !_INTEL_CHECK_H
  200. //
  201. // Error Severity: using vits (PSPcm) & (PSPus) only
  202. // The SAL spec'ed values are defined in ntos\inc\hal.h
  203. //
  204. // To remind you:
  205. // #define ErrorRecoverable ((USHORT)0)
  206. // #define ErrorFatal ((USHORT)1)
  207. // #define ErrorCorrected ((USHORT)2)
  208. //
  209. // The following values define some of the reserved ErrorOthers.
  210. #define ErrorBCeb ((USHORT)6)
  211. #endif // !_INTEL_CHECK_H
  212. #if defined(_INTEL_CHECK_H)
  213. // System Errors bits masks to be handled by SAL, mask bits in d64-d32
  214. #define parError 0x000100000000 // Memory parity error
  215. #define eccError 0x000200000000 // Memory ECC error
  216. #define busError PSPbc // System Bus Check/Error
  217. #define iocError 0x000800000000 // System IO Check Errors
  218. #define temError 0x002000000000 // System Temperature Error
  219. #define vccError 0x004000000000 // System Voltage Error
  220. #define intError 0x010000000000 // Intrusion Error for servers
  221. #define cacError PSPcc // Cache Error
  222. #define tlbError PSPtc // TLB error
  223. #define unkError PSPuc // Unknown/Catastrophic error
  224. // error bits masks
  225. #define PALErrMask 0x0ff // bit mask of errors correctable by PAL
  226. #define SALErrMask busError+cacError+tlbError+unkError // SAL error bit mask
  227. #define OSErrMask 0x0ff // OS expected error conditions
  228. #define MCAErrMask 0x0ff // Given MCA Error Mask bit map
  229. // New processor error Record structures ACO504
  230. typedef struct tagModInfo
  231. {
  232. U64 eValid; // Valid bits for module entries
  233. U64 eInfo; // error info cache/tlb/bus
  234. U64 ReqId; // requester ID
  235. U64 ResId; // responder ID
  236. U64 TarId; // target ID
  237. U64 IP; // Precise IP
  238. } ModInfo;
  239. typedef struct tagSAL_GUID
  240. {
  241. U32 Data1;
  242. U16 Data2;
  243. U16 Data3;
  244. U8 Data4[8];
  245. } SAL_GUID;
  246. typedef struct tagProcessorInfo
  247. {
  248. U64 ValidBits;
  249. U64 Pem; // processor map
  250. U64 Psp; // processor state parameter
  251. U64 Pid; // processor LID register value
  252. ModInfo cInfo[8]; // cache check max of 8
  253. ModInfo tInfo[8]; // tlb check max of 8
  254. ModInfo bInfo[4]; // bus check max or 4
  255. U64 rInfo[4]; // register file check max of 4
  256. U64 mInfo[4]; // micro-architectural information max of
  257. U64 Psi[584+8]; // 584 bytes
  258. } ProcessorInfo;
  259. typedef struct tagMinProcessorInfo
  260. {
  261. U64 ValidBits;
  262. U64 Psp; // processor state parameter
  263. U64 Pem; // processor map
  264. U64 Pid; // processor LID register value
  265. } MinProcessorInfo;
  266. // end ACO504 changes.
  267. // platform error Record structures
  268. typedef struct tagCfgSpace
  269. {
  270. // data - error register dump
  271. U64 CfgRegAddr; // register offset/addr
  272. U64 CfgRegVal; // register data/value
  273. } CfgSpace;
  274. typedef struct tagMemSpace
  275. {
  276. // data - error register dump
  277. U64 MemRegAddr; // register offset/addr
  278. U64 MemRegVal; // register data/value
  279. } MemSpace;
  280. typedef union tagMemCfgSpace
  281. {
  282. MemSpace mSpace;
  283. CfgSpace cSpace;
  284. } MemCfgSpace;
  285. typedef struct tagSysCompErr // per component
  286. {
  287. U64 vFlag; // bit63=PCI device Flag, LSB:valid bits for each field in the Record
  288. // header for component Record
  289. U64 BusNum; // bus number on which the component resides
  290. U64 DevNum; // same as device select
  291. U64 FuncNum; // function ID of the device
  292. U64 DevVenID; // PCI device & vendor ID
  293. U64 SegNum; // segment number as defined in SAL spec.
  294. // register dump info.
  295. U64 MemSpaceNumRegPair; // number of reg addr/value pairs returned in this Record
  296. U64 CfgSpaceNumRegPair; // number of reg addr/value pairs returned in this Record
  297. MemCfgSpace mcSpace; // register add/data value pair array
  298. } cErrRecord;
  299. #define BusNum_valid 0x01
  300. #define DevNum_valid 0x02
  301. #define FuncNum_valid 0x04
  302. #define DevVenID_valid 0x08
  303. #define SegNum_valid 0x10
  304. #define MemSpaceNumRegPair_valid 0x20
  305. #define CfgSpaceNumRegPair_valid 0x40
  306. #define mcSpace_valid 0x80
  307. typedef struct tagPlatErrSection
  308. {
  309. U64 vFlag; // valid bits for each type of Record
  310. U64 Addr; // memory address
  311. U64 Data; // memory data
  312. U64 CmdType; // command/operation type
  313. U64 BusID; // bus ID if applicable
  314. U64 RequesterID; // Requestor of the transaction if any
  315. U64 ResponderID; // Intended target or responder
  316. U64 NumOemExt; // Number of OEM Extension Arrays
  317. cErrRecord OemExt; // Value Array of OEM extensions
  318. } PlatformInfo;
  319. #define Addr_valid 0x01
  320. #define Data_valid 0x02
  321. #define CmdType_valid 0x04
  322. #define BusID_valid 0x08
  323. #define RequesterID_valid 0x10
  324. #define ResponderID_valid 0x20
  325. #define NumOemExt_valid 0x40
  326. #define OemExt_valid 0x80
  327. // over all Record structure (processor+platform)
  328. typedef union utagDeviceSpecificSection
  329. {
  330. ProcessorInfo procSection;
  331. PlatformInfo platSection;
  332. } DeviceSection;
  333. // SAL PSI Record & Section structure
  334. typedef struct tagPsiSectionHeader
  335. {
  336. SAL_GUID SectionGuid;
  337. U16 Revision;
  338. U16 Reserved;
  339. U32 SectionLength;
  340. } PsiSectionHeader;
  341. typedef struct tagPsiSection
  342. {
  343. SAL_GUID SectionGuid;
  344. U16 Revision;
  345. U16 Reserved;
  346. U32 SectionLength;
  347. DeviceSection DevSection;
  348. } PsiSection;
  349. typedef struct tagPsiRecordHeader
  350. {
  351. U64 RecordID;
  352. U16 Revision;
  353. U16 eSeverity;
  354. U32 RecordLength;
  355. U64 TimeStamp;
  356. } PsiRecordHeader;
  357. typedef struct tagPsiRecord
  358. {
  359. U64 RecordID;
  360. U16 Revision;
  361. U16 eSeverity;
  362. U32 RecordLength;
  363. U64 TimeStamp;
  364. PsiSection PsiDevSection;
  365. } PsiRecord;
  366. /*
  367. LION 460GX:
  368. SAC: SAC_FERR, SAC_FERR
  369. SDC: SDC_FERR, SDC_NERR
  370. MAC: FERR_MAC
  371. GXB: FERR_GXB, FERR_PCI, FERR_GART, FERR_F16, FERR_AGP
  372. */
  373. typedef struct tagPciCfgHdr
  374. {
  375. U8 RegAddr;
  376. U8 FuncNum;
  377. U8 DevNum;
  378. U8 BusNum;
  379. U8 SegNum;
  380. U8 Res[3];
  381. } PciCfgHdr;
  382. #define PLATFORM_REC_CNT 0x01 // number of consecutive Records in the platform Record linked list
  383. #define OEM_EXT_REC_CNT 0x06 // number of consecutive OEM extension Array count
  384. // number of registers that will be returned for each device
  385. #define SAC_REG_CNT 0x02
  386. #define SDC_REG_CNT 0x02
  387. #define MAC_REG_CNT 0x01
  388. #define GXB_REG_CNT 0x04
  389. typedef struct tagSacRegs
  390. {
  391. PciCfgHdr pHdr;
  392. U64 RegCnt;
  393. U64 RegAddr[SAC_REG_CNT];
  394. } SacDevInfo;
  395. typedef struct tagSdcRegs
  396. {
  397. PciCfgHdr pHdr;
  398. U64 RegCnt;
  399. U64 RegAddr[SDC_REG_CNT];
  400. } SdcDevInfo;
  401. typedef struct tagMacRegs
  402. {
  403. PciCfgHdr pHdr;
  404. U64 RegCnt;
  405. U64 RegAddr[MAC_REG_CNT];
  406. } MacDevInfo;
  407. typedef struct tagGxbRegs
  408. {
  409. PciCfgHdr pHdr;
  410. U64 RegCnt;
  411. U64 RegAddr[GXB_REG_CNT];
  412. } GxbDevInfo;
  413. typedef struct tagDevInfo
  414. {
  415. PciCfgHdr pHdr;
  416. U64 RegCnt;
  417. U64 RegAddr[4];
  418. } DevInfo;
  419. #define DEV_VEN_ID_ADDR 0x0
  420. #define SAC_BN 0x10
  421. #define DevNumber0 0x0
  422. #define DevNumber1 0x1
  423. #define DevNumber2 0x2
  424. #define DevNumber3 0x3
  425. #define DevNumber4 0x4
  426. #define DevNumber5 0x5
  427. #define DevNumber6 0x6
  428. // function prototypes
  429. rArg _BuildProcErrSection(PsiRecord*, U64, U64, U64);
  430. rArg _BuildPlatErrSection(PsiSection*, U64, U64, U64);
  431. rArg _BuildChipSetSection(PsiSection*, U64);
  432. rArg _GetErrRecord(PsiRecord*, U64, PsiRecord*,PsiSection*, U64*, U64);
  433. rArg _NvmErrRecordMgr(U64, U64, U64, U64);
  434. rArg GetDeviceRecord(cErrRecord*, DevInfo*);
  435. rArg SAL_PCI_CONFIG_READ_(U64, U64, U64, U64, U64, U64, U64, U64);
  436. rArg SAL_PCI_CONFIG_WRITE_(U64, U64, U64, U64, U64, U64, U64, U64);
  437. rArg OemGetInitSource();
  438. rArg _MakeStaticPALCall(U64, U64, U64, U64, U64);
  439. rArg GetProcNum();
  440. #endif // _INTEL_CHECK_H
  441. #endif // CHECK_H_INCLUDED