Leaked source code of windows server 2003
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4.4 KiB

  1. /*--------------------------------------------------------------------------
  2. *
  3. * Copyright (C) Cyclades Corporation, 1999-2001.
  4. * All rights reserved.
  5. *
  6. * Cyclom-Y Bus/Port Driver
  7. *
  8. * This file: cyyhw.h
  9. *
  10. * Description: This module contains the common hardware declarations
  11. * for the parent driver (cyclom-y) and child driver
  12. * (cyyport).
  13. *
  14. * Notes: This code supports Windows 2000 and Windows XP,
  15. * x86 and ia64 processors.
  16. *
  17. * Complies with Cyclades SW Coding Standard rev 1.3.
  18. *
  19. *--------------------------------------------------------------------------
  20. */
  21. /*-------------------------------------------------------------------------
  22. *
  23. * Change History
  24. *
  25. *--------------------------------------------------------------------------
  26. *
  27. *
  28. *--------------------------------------------------------------------------
  29. */
  30. #ifndef CYYHW_H
  31. #define CYYHW_H
  32. #define MAX_DEVICE_ID_LEN 200 // This definition was copied from NTDDK\inc\cfgmgr32.h
  33. // Always check if this value was changed.
  34. // This is the maximum length for the Hardware ID.
  35. #define CYYPORT_PNP_ID_WSTR L"Cyclom-Y\\Port"
  36. #define CYYPORT_PNP_ID_STR "Cyclom-Y\\Port"
  37. #define CYYPORT_DEV_ID_STR "Cyclom-Y\\Port"
  38. #define CYY_NUMBER_OF_RESOURCES 3 // Memory, PLX Memory, Interrupt
  39. // Cyclom-Y hardware
  40. #define CYY_RUNTIME_LENGTH 0x00000080
  41. #define CYY_MAX_CHIPS 8
  42. #define CYY_CHANNELS_PER_CHIP 4
  43. #define CYY_MAX_PORTS (CYY_CHANNELS_PER_CHIP*CYY_MAX_CHIPS)
  44. // Custom register offsets
  45. #define CYY_CLEAR_INTR 0x1800 //Isa; for PCI, multiply by 2
  46. #define CYY_RESET_16 0x1400 //Isa; for PCI, multiply by 2
  47. #define CYY_PCI_TYPE 0x3400 //PCI (no need to multiply by 2)
  48. // Values in CYY_PCI_TYPE register
  49. #define CYY_PLX9050 (0x0b)
  50. #define CYY_PLX9060 (0x0c)
  51. #define CYY_PLX9080 (0x0d)
  52. // Runtime registers (or Local Configuration registers)
  53. #define PLX9050_INT_OFFSET (0x4c)
  54. #define PLX9060_INT_OFFSET (0x68)
  55. #define PLX9050_INT_ENABLE (0x00000043UL)
  56. #define PLX9060_INT_ENABLE (0x00000900UL)
  57. // Write to Custom registers
  58. #define CYY_RESET_BOARD(BaseBoardAddress,IsPci) \
  59. do \
  60. { \
  61. WRITE_REGISTER_UCHAR( \
  62. (BaseBoardAddress)+(CYY_RESET_16 << IsPci), \
  63. 0x00 \
  64. ); \
  65. } while (0);
  66. #define CYY_CLEAR_INTERRUPT(BaseBoardAddress,IsPci) \
  67. do \
  68. { \
  69. WRITE_REGISTER_UCHAR( \
  70. (BaseBoardAddress)+(CYY_CLEAR_INTR << IsPci), \
  71. 0x00 \
  72. ); \
  73. } while (0);
  74. #define CYY_READ_PCI_TYPE(BaseBoardAddress) \
  75. (READ_REGISTER_UCHAR((BaseBoardAddress)+CYY_PCI_TYPE))
  76. #define PLX9050_READ_INTERRUPT_CONTROL(BaseBoardAddress) \
  77. (READ_REGISTER_ULONG((PULONG)((BaseBoardAddress)+PLX9050_INT_OFFSET)))
  78. #define PLX9050_WRITE_INTERRUPT_CONTROL(BaseBoardAddress,Value) \
  79. do { \
  80. WRITE_REGISTER_ULONG( \
  81. (PULONG)((BaseBoardAddress)+PLX9050_INT_OFFSET), \
  82. Value \
  83. ); \
  84. } while (0);
  85. #define PLX9060_READ_INTERRUPT_CONTROL(BaseBoardAddress) \
  86. (READ_REGISTER_ULONG((PULONG)((BaseBoardAddress)+PLX9060_INT_OFFSET)))
  87. #define PLX9060_WRITE_INTERRUPT_CONTROL(BaseBoardAddress,Value) \
  88. do { \
  89. WRITE_REGISTER_ULONG( \
  90. (PULONG)((BaseBoardAddress)+PLX9060_INT_OFFSET), \
  91. Value \
  92. ); \
  93. } while (0);
  94. #endif // ndef CYCOMMON_H