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238 lines
8.1 KiB
238 lines
8.1 KiB
//
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// agpALi.sys is a driver, make sure we get the appropriate linkage.
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//
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#define _NTDRIVER_
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#include "stdarg.h"
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#include "stdio.h"
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#include "ntddk.h"
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#include "agp.h"
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//
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// Define the location of the GART aperture control registers
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//
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//
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// The GART registers on the ALi M1541 live in the host-PCI bridge.
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// This is unfortunate, since the AGP driver attaches to the PCI-PCI (AGP)
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// bridge. So we have to get to the host-PCI bridge config space
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// and this is only possible because we KNOW this is bus 0, slot 0.
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//
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#define AGP_ALi_GART_BUS_ID 0
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#define AGP_ALi_GART_SLOT_ID 0
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#define AGP_ALi_P2P_SLOT_ID 1
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#define AGP_VGA_BUS_ID 1
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#define AGP_VGA_SLOT_ID 0
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#define AGP_ALi_1541_IDENTIFIER 0x154110b9
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#define AGP_ALi_1621_IDENTIFIER 0x162110b9
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#define AGP_ALi_1631_IDENTIFIER 0x163110b9
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#define AGP_ALi_1632_IDENTIFIER 0x163210b9
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#define AGP_ALi_1641_IDENTIFIER 0x164110b9
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#define AGP_ALi_1644_IDENTIFIER 0x164410b9
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#define AGP_ALi_1646_IDENTIFIER 0x164610b9
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#define AGP_ALi_1647_IDENTIFIER 0x164710b9
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#define AGP_ALi_1651_IDENTIFIER 0x165110b9
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#define AGP_ALi_1671_IDENTIFIER 0x167110b9
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#define AGP_ALi_1672_IDENTIFIER 0x167210b9
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#define APBASE_OFFSET 0x10 // Aperture Base Address
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#define AGP_STATUS_OFFSET 0xB4 // AGP Status Register
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#define CHIP_REVISION_OFFSET 0x08 // NorthBridge revision ID
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#define APCTRL_OFFSET 0xBC // Aperture Translation Table Base
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#define GTLBCTRL_OFFSET 0xC0 // GTLB Control Register
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#define GTLBTAGCLR_OFFSET 0xC4 // GTLB TAG Clear Register
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#define L1_2_CACHE_FLUSH_CTRL 0xD0 // L1/L2 Cache Flush Control
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#define M1541_Lock_WR 0x90 // M1541 AGP Status Lock Read/Write Control
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#define M1621_Lock_WR 0xC8 // M1621 AGP Status Lock Read/Write Control
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#define PCI_STATUS_REG 0x4 // PCI Status Register
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#define CAP_PTR 0x34 // PCI Capability Pointer
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#define AGP_ID 0x2 // AGP Capability ID
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#define M1621_HIDDEN_REV_ID 0xFB // M1621 series Hidden Revision ID
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#define ReadConfigUlong(_bus_,_slot_,_buf_,_offset_) \
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{ \
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ULONG _len_; \
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_len_ = HalGetBusDataByOffset(PCIConfiguration, \
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(_bus_), \
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(_slot_), \
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(_buf_), \
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(_offset_), \
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4); \
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ASSERT(_len_ == 4); \
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}
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#define ReadConfigUlongSafe(_bus_,_slot_,_buf_,_offset_) \
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{ \
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HalGetBusDataByOffset(PCIConfiguration, \
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(_bus_), \
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(_slot_), \
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(_buf_), \
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(_offset_), \
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4); \
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}
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#define ReadConfigUchar(_bus_,_slot_,_buf_,_offset_) \
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{ \
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ULONG _len_; \
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_len_ = HalGetBusDataByOffset(PCIConfiguration, \
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(_bus_), \
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(_slot_), \
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(_buf_), \
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(_offset_), \
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1); \
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ASSERT(_len_ == 1); \
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}
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#define WriteConfigUlong(_bus_,_slot_,_buf_,_offset_) \
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{ \
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ULONG _len_; \
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_len_ = HalSetBusDataByOffset(PCIConfiguration, \
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(_bus_), \
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(_slot_), \
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(_buf_), \
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(_offset_), \
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4); \
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ASSERT(_len_ == 4); \
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}
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#define WriteConfigUchar(_bus_,_slot_,_buf_,_offset_) \
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{ \
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ULONG _len_; \
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_len_ = HalSetBusDataByOffset(PCIConfiguration, \
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(_bus_), \
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(_slot_), \
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(_buf_), \
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(_offset_), \
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1); \
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ASSERT(_len_ == 1); \
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}
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#define AP_SIZE_4MB 0x03
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#define AP_SIZE_8MB 0x04
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#define AP_SIZE_16MB 0x06
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#define AP_SIZE_32MB 0x07
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#define AP_SIZE_64MB 0x08
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#define AP_SIZE_128MB 0x09
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#define AP_SIZE_256MB 0x0A
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#define AP_SIZE_COUNT 7
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#define AP_MIN_SIZE (4 * 1024 * 1024)
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#define AP_MAX_SIZE (256 * 1024 * 1024)
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//
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// Define the GART table entry.
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//
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typedef struct _GART_ENTRY_HW {
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ULONG Valid : 1;
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ULONG Reserved : 11;
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ULONG Page : 20;
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} GART_ENTRY_HW, *PGART_ENTRY_HW;
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//
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// GART Entry states are defined so that all software-only states
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// have the Valid bit clear.
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//
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#define GART_ENTRY_VALID 1 // 001
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#define GART_ENTRY_FREE 0 // 000
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#define GART_ENTRY_WC 2 // 010
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#define GART_ENTRY_UC 4 // 100
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#define GART_ENTRY_RESERVED_WC GART_ENTRY_WC
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#define GART_ENTRY_RESERVED_UC GART_ENTRY_UC
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#define GART_ENTRY_VALID_WC (GART_ENTRY_VALID)
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#define GART_ENTRY_VALID_UC (GART_ENTRY_VALID)
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typedef struct _GART_ENTRY_SW {
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ULONG State : 3;
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ULONG Reserved : 29;
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} GART_ENTRY_SW, *PGART_ENTRY_SW;
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typedef struct _GART_PTE {
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union {
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GART_ENTRY_HW Hard;
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ULONG AsUlong;
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GART_ENTRY_SW Soft;
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};
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} GART_PTE, *PGART_PTE;
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//
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// Define the layout of the hardware registers
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//
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typedef struct _APCTRL {
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ULONG ApSize : 4;
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ULONG Reserved1 : 8;
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ULONG ATTBase : 20;
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} APCTRL, *PAPCTRL;
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typedef struct _GTLBCTRL {
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ULONG GartLevelSelect : 1;
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ULONG Reserved1 : 3;
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ULONG GTLBSize : 2;
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ULONG Reserved2 : 1;
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ULONG GTLB_ENJ : 1; // 0:Enable 1:Desable
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ULONG NLVM_Base : 12;
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ULONG NLVM_Top : 12;
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} GTLBCTRL, *PGTLBCTRL;
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typedef struct _GTLBTAGCLR {
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ULONG GTLBTagClear : 1;
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ULONG ClearAllTag : 1;
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ULONG ClearGDir : 1;
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ULONG Reserved2 : 12;
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ULONG Page : 17;
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} GTLBTAGCLR, *PGTLBTAGCLR;
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typedef struct _CACHECTRL {
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ULONG Reserved1 : 8;
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ULONG Flush_Enable : 1;
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ULONG Reserved2 : 3;
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ULONG Address : 20;
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} CACHECTRL, *PCACHECTRL;
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//
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// Define the different chipsets supported by this driver.
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//
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typedef enum _ALI_CHIPSET_TYPE {
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ALi1541,
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ALi1621,
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ALi1631,
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ALi1632,
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ALi1641,
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ALi1644,
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ALi1646,
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ALi1647,
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ALi1651,
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ALi1671,
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ALi1672
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} ALI_CHIPSET_TYPE;
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//
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// Define the ALi-specific extension
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//
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typedef struct _AGPALi_EXTENSION {
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PHYSICAL_ADDRESS ApertureStart;
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ULONG ApertureLength;
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PGART_PTE Gart;
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ULONG GartLength;
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PHYSICAL_ADDRESS GartPhysical;
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ALI_CHIPSET_TYPE ChipsetType;
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ULONGLONG SpecialTarget;
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} AGPALi_EXTENSION, *PAGPALi_EXTENSION;
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NTSTATUS
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Agp1541FlushPages(
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IN PAGPALi_EXTENSION AgpContext,
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IN PMDL Mdl
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);
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VOID
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AgpWorkaround(
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IN PVOID AgpExtension
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);
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