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1004 lines
25 KiB
1004 lines
25 KiB
/*++
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Copyright (c) 2000 Microsoft Corporation
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Module Name:
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busno.c
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Abstract:
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This module implements routines pertaining to PCI bus numbers.
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Author:
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Andy Thornton (andrewth) 9/5/98
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Revision History:
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--*/
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#include "pcip.h"
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VOID
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PciSpreadBridges(
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IN PPCI_FDO_EXTENSION Parent,
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IN UCHAR BridgeCount
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);
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UCHAR
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PciFindBridgeNumberLimit(
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IN PPCI_FDO_EXTENSION BridgeParent,
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IN UCHAR Base
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);
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VOID
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PciFitBridge(
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IN PPCI_FDO_EXTENSION ParentFdoExtension,
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IN PPCI_PDO_EXTENSION BridgePdoExtension
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);
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VOID
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PciSetBusNumbers(
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IN PPCI_PDO_EXTENSION PdoExtension,
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IN UCHAR Primary,
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IN UCHAR Secondary,
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IN UCHAR Subordinate
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);
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VOID
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PciUpdateAncestorSubordinateBuses(
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IN PPCI_FDO_EXTENSION FdoExtension,
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IN UCHAR Subordinate
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);
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VOID
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PciDisableBridge(
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IN PPCI_PDO_EXTENSION Bridge
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);
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UCHAR
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PciFindBridgeNumberLimitWorker(
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IN PPCI_FDO_EXTENSION BridgeParent,
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IN PPCI_FDO_EXTENSION CurrentParent,
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IN UCHAR Base,
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OUT PBOOLEAN RootConstrained
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);
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#ifdef ALLOC_PRAGMA
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#pragma alloc_text(PAGE, PciConfigureBusNumbers)
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#pragma alloc_text(PAGE, PciAreBusNumbersConfigured)
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#pragma alloc_text(PAGE, PciSpreadBridges)
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#pragma alloc_text(PAGE, PciFindBridgeNumberLimit)
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#pragma alloc_text(PAGE, PciFitBridge)
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#pragma alloc_text(PAGE, PciSetBusNumbers)
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#pragma alloc_text(PAGE, PciUpdateAncestorSubordinateBuses)
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#pragma alloc_text(PAGE, PciDisableBridge)
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#pragma alloc_text(PAGE, PciFindBridgeNumberLimitWorker)
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#endif
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VOID
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PciConfigureBusNumbers(
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PPCI_FDO_EXTENSION Parent
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)
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/*++
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Routine Description:
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This routine is called after scanning a PCI bus (root or bridge) and
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configures the bus numbers for any newly encountered bridges if possible.
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Any unconfigurable bridges will be set to Primary = Secondary = Subordinate = 0
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and their IO, Memory and BusMaster bits will be disabled. When PCI is later
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asked to Add to them it will fail.
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The Parent->Mutex lock should be held before calling this function
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Arguments:
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Parent - The bridge we have just enumerated.
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Return Value:
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Status.
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--*/
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{
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PPCI_PDO_EXTENSION current, parentPdo = NULL;
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UCHAR bridgeCount = 0, configuredBridgeCount = 0;
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PAGED_CODE();
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if (!PCI_IS_ROOT_FDO(Parent)) {
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parentPdo = (PPCI_PDO_EXTENSION)Parent->PhysicalDeviceObject->DeviceExtension;
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}
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//
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// Walk the list of child PDO's for this bus and count the number of
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// bridges and configured bridges
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//
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ExAcquireFastMutex(&Parent->ChildListMutex);
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for (current = Parent->ChildBridgePdoList;
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current;
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current = current->NextBridge) {
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if (current->NotPresent) {
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PciDebugPrint(PciDbgBusNumbers,
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"Skipping not present bridge PDOX @ %p\n",
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current
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);
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continue;
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}
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bridgeCount++;
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//
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// If we configured the parent then all the children are considered
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// to be unconfigured. Root buses are always configured
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//
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if ((parentPdo &&
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parentPdo->Dependent.type1.WeChangedBusNumbers &&
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(current->DeviceState == PciNotStarted))
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|| (!PciAreBusNumbersConfigured(current))) {
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//
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// Disable this bridge and we will fix it later
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//
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PciDisableBridge(current);
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} else {
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//
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// The bios must have configured this bridge and it looks valid so
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// leave it alone!
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//
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configuredBridgeCount++;
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}
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}
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ExReleaseFastMutex(&Parent->ChildListMutex);
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//
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// Now there are four posibilities...
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//
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if (bridgeCount == 0) {
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//
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// There are no bridges so not a lot to do...
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//
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PciDebugPrint(PciDbgBusNumbers,
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"PCI - No bridges found on bus 0x%x\n",
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Parent->BaseBus
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);
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} else if (bridgeCount == configuredBridgeCount) {
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//
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// All the bridges are configured - still not a lot to do...
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//
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PciDebugPrint(PciDbgBusNumbers,
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"PCI - 0x%x bridges found on bus 0x%x - all already configured\n",
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bridgeCount,
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Parent->BaseBus
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);
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} else if (configuredBridgeCount == 0) {
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PciDebugPrint(PciDbgBusNumbers,
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"PCI - 0x%x bridges found on bus 0x%x - all need configuration\n",
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bridgeCount,
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Parent->BaseBus
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);
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//
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// All the bridges require configuration so we should use a spreading
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// out algorithm
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//
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PciSpreadBridges(Parent, bridgeCount);
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} else {
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//
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// Some of the bridges are configured and some are not - we should try
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// to fit the unconfigured ones into the holes left by the configured
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// ones
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//
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PCI_ASSERT(configuredBridgeCount < bridgeCount);
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PciDebugPrint(PciDbgBusNumbers,
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"PCI - 0x%x bridges found on bus 0x%x - 0x%x need configuration\n",
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bridgeCount,
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Parent->BaseBus,
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bridgeCount - configuredBridgeCount
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);
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//
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// Walk the list of PDO's again and configure each one seperatly
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//
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for (current = Parent->ChildBridgePdoList;
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current;
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current = current->NextBridge) {
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if (current->NotPresent) {
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PciDebugPrint(PciDbgBusNumbers,
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"Skipping not present bridge PDOX @ %p\n",
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current
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);
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continue;
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}
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//
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// Fit the bridge if we disabled it.
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//
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if ((parentPdo &&
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parentPdo->Dependent.type1.WeChangedBusNumbers &&
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(current->DeviceState == PciNotStarted))
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|| (!PciAreBusNumbersConfigured(current))) {
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PCI_ASSERT(current->Dependent.type1.PrimaryBus == 0
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&& current->Dependent.type1.SecondaryBus == 0
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&& current->Dependent.type1.SubordinateBus == 0
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);
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PciFitBridge(Parent, current);
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}
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}
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}
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}
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BOOLEAN
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PciAreBusNumbersConfigured(
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IN PPCI_PDO_EXTENSION Bridge
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)
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/*++
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Routine Description:
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This checks if the bus numbers assigned to the bridge are valid
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Arguments:
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Bridge - the bridge to check
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Return Value:
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TRUE if numbers are valid FALSE otherwise.
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--*/
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{
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PAGED_CODE();
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//
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// Check this bridge is configured to run on the bus we found it.
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//
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if (Bridge->Dependent.type1.PrimaryBus != Bridge->ParentFdoExtension->BaseBus) {
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return FALSE;
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}
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//
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// Ensure the child bus number is greater than the parent bus.
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// (HP Omnibooks actually break this rule when not plugged into
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// their docking stations).
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//
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if (Bridge->Dependent.type1.SecondaryBus <= Bridge->Dependent.type1.PrimaryBus) {
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return FALSE;
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}
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//
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// And finally, make sure the secondary bus is in the range
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// of busses the bridge is programmed for. Paranoia.
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//
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if (Bridge->Dependent.type1.SubordinateBus < Bridge->Dependent.type1.SecondaryBus) {
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return FALSE;
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}
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return TRUE;
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}
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VOID
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PciSpreadBridges(
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IN PPCI_FDO_EXTENSION Parent,
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IN UCHAR BridgeCount
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)
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/*++
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Routine Description:
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This routine attemps to spread out the available bus numbers between the
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unconfigured bridges. It is only called if ALL the bridges on a particular
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bus are not configured - eg we just hot docked!
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If a particular brigde can not be configured it is disabled (Decodes OFF and
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bus number 0->0-0) and the subsequent AddDevice will fail.
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Arguments:
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Parent - The FDO extension for the bridge we are enumerating.
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BridgeCount - The number of bridges at this level
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Return Value:
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None
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--*/
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{
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UCHAR base, limit, numberCount, currentNumber, spread, maxAssigned = 0;
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PPCI_PDO_EXTENSION current;
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PAGED_CODE();
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PCI_ASSERT(Parent->BaseBus < PCI_MAX_BRIDGE_NUMBER);
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//
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// Seeing as we only get here if all the bridges arn't configured the base
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// is the lowest bus out parent passes
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//
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base = (UCHAR)Parent->BaseBus;
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//
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// The limit is constrained by the siblings of the parent bridge or in the
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// case that there are none, by the siblings of the parent's parent and so on
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// until we find a sibling or run out of buses in which case the constraint
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// is the maximum bus number passed by this root.
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//
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limit = PciFindBridgeNumberLimit(Parent, base);
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if (limit < base) {
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//
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// This normally means the BIOS or HAL messed up and got the subordinate
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// bus number for the root bus wrong. There's not much we can do..
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//
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PCI_ASSERT(limit >= base);
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return;
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}
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//
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// Now see if we have enough numbers available to number all the busses
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//
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numberCount = limit - base;
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if (numberCount == 0) {
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//
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// We don't have any bus numbers available - bail now
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//
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return;
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} else if (BridgeCount >= numberCount) {
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//
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// We have just/not enough - don't spread things out!
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//
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spread = 1;
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} else {
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//
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// Try and spread things out a bit so we can accomodate subordinate
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// bridges of the one we are configuring. Also leave some space on the
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// parent bus for any bridges that appear here (the + 1). As we have no idea
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// what is behind each bridge treat them equally...
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//
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spread = numberCount / (BridgeCount + 1);
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}
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//
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// Now assign the bus numbers - we have already disabled all the unconfigured
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// bridges
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//
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currentNumber = base + 1;
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for (current = Parent->ChildBridgePdoList;
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current;
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current = current->NextBridge) {
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if (current->NotPresent) {
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PciDebugPrint(PciDbgBusNumbers,
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"Skipping not present bridge PDOX @ %p\n",
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current
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);
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continue;
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}
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//
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// Now go and write it out to the hardware
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//
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PCI_ASSERT(!PciAreBusNumbersConfigured(current));
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//
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// Primary is the bus we are on, secondary is our bus number.
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// We don't know if there are any bridges there - we have left space
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// just in case - therefore we don't pass any bus numbers. If we
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// need to, the subordinate number can be updated later.
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//
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PciSetBusNumbers(current,
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base,
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currentNumber,
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currentNumber
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);
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//
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// Remember the max number we assigned
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//
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maxAssigned = currentNumber;
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//
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// Check if we have run out of numbers
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//
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if ((currentNumber + spread) < currentNumber // wrapped
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|| (currentNumber + spread) > limit) {
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break;
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} else {
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//
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// Move onto the next number
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//
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//currentNumber += spread;
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currentNumber = currentNumber + spread;
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}
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}
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//
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// Now we have programmed the bridges - we need to go back and update the
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// subordinate bus numbers for all ancestor bridges.
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//
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PCI_ASSERT(maxAssigned > 0);
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PciUpdateAncestorSubordinateBuses(Parent, maxAssigned);
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}
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UCHAR
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PciFindBridgeNumberLimitWorker(
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IN PPCI_FDO_EXTENSION BridgeParent,
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IN PPCI_FDO_EXTENSION CurrentParent,
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IN UCHAR Base,
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OUT PBOOLEAN RootConstrained
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)
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/*++
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Routine Description:
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This determines the subordinate bus number a bridge on the bus BridgeParent
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with secondary number Base can have given the constraints of the configured
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busses in the system.
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Arguments:
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BridgeParent - The bus on which the bridge resides
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CurrentParent - The current bridge we are looking at (used for synchronization)
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Base - The primary bus number of this bridge (ie the parent's secondary bus number)
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Constraint - The number of the bus that constrains us
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RootConstrained - Set to TRUE if we were constrained by a root appeture, FALSE
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if constrained by another bridge
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Return Value:
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None
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--*/
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{
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PPCI_PDO_EXTENSION current;
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UCHAR currentNumber, closest = 0;
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PAGED_CODE();
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if (BridgeParent != CurrentParent) {
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//
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// We're going to mess with the child pdo list - lock the state...
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//
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ExAcquireFastMutex(&CurrentParent->ChildListMutex);
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}
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//
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// Look for any bridge that will constrain us
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//
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for (current = CurrentParent->ChildBridgePdoList;
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current;
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current = current->NextBridge) {
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if (current->NotPresent) {
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PciDebugPrint(PciDbgBusNumbers,
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"Skipping not present bridge PDOX @ %p\n",
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current
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);
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continue;
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}
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//
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// Unconfigured bridges can't constrain us
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//
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if (!PciAreBusNumbersConfigured(current)) {
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continue;
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}
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currentNumber = current->Dependent.type1.SecondaryBus;
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if (currentNumber > Base
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&& (currentNumber < closest || closest == 0)) {
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closest = currentNumber;
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}
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}
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//
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// If we haven't found a closest bridge then move up one level - yes this
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// is recursive but is bounded by the depth of the pci tree is the best way
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// of dealing with the hierarchial locking.
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//
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if (closest == 0) {
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if (CurrentParent->ParentFdoExtension == NULL) {
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//
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// We have reached the root without finding a sibling
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//
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*RootConstrained = TRUE;
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closest = CurrentParent->MaxSubordinateBus;
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} else {
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closest = PciFindBridgeNumberLimitWorker(BridgeParent,
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CurrentParent->ParentFdoExtension,
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Base,
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RootConstrained
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);
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}
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} else {
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//
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// We are constrained by a bridge so by definition not by a root.
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//
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*RootConstrained = FALSE;
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}
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if (BridgeParent != CurrentParent) {
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ExReleaseFastMutex(&CurrentParent->ChildListMutex);
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}
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return closest;
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}
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|
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UCHAR
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PciFindBridgeNumberLimit(
|
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IN PPCI_FDO_EXTENSION Bridge,
|
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IN UCHAR Base
|
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)
|
|
|
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/*++
|
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|
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Routine Description:
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|
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This determines the subordinate bus number a bridge on the bus BridgeParent
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with secondary number Base can have given the constraints of the configured
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busses in the system.
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|
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Arguments:
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BridgeParent - The bus on which the bridge resides
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Base - The primary bus number of this bridge (ie the parent's secondary bus number)
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Return Value:
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The max subordinate value.
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--*/
|
|
{
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|
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BOOLEAN rootConstrained;
|
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UCHAR constraint;
|
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|
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PAGED_CODE();
|
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|
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constraint = PciFindBridgeNumberLimitWorker(Bridge,
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Bridge,
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Base,
|
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&rootConstrained
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);
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|
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|
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if (rootConstrained) {
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|
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//
|
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// We are constrained by the maximum bus number that this root bus passes
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// - this is therefore the max subordinate bus.
|
|
//
|
|
|
|
return constraint;
|
|
|
|
} else {
|
|
|
|
//
|
|
// If we are not constrained by a root bus we must be constrained by a
|
|
// bridge and thus the max subordinate value we can assign to the bus is
|
|
// one less that the bridge that constrained us. (A bridge must have a
|
|
// bus number greater that 1 so we can't wrap)
|
|
//
|
|
|
|
PCI_ASSERT(constraint > 0);
|
|
return constraint - 1;
|
|
}
|
|
}
|
|
|
|
VOID
|
|
PciFitBridge(
|
|
IN PPCI_FDO_EXTENSION Parent,
|
|
IN PPCI_PDO_EXTENSION Bridge
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine attemps to find a range of bus numbers for Bridge given the
|
|
constraints of the already configured bridges.
|
|
|
|
If a particular brigde can not be configured it is disabled (Decodes OFF and
|
|
bus number 0->0-0) and the subsequent AddDevice will fail.
|
|
|
|
Arguments:
|
|
|
|
Parent - The FDO extension for the bridge we are enumerating.
|
|
|
|
Bridge - The brige we want to configure
|
|
|
|
Return Value:
|
|
|
|
None
|
|
|
|
--*/
|
|
|
|
{
|
|
PPCI_PDO_EXTENSION current;
|
|
UCHAR base, limit, gap, bestBase = 0, biggestGap = 0, lowest = 0xFF;
|
|
|
|
PAGED_CODE();
|
|
|
|
for (current = Parent->ChildBridgePdoList;
|
|
current;
|
|
current = current->NextBridge) {
|
|
|
|
if (current->NotPresent) {
|
|
PciDebugPrint(PciDbgBusNumbers,
|
|
"Skipping not present bridge PDOX @ %p\n",
|
|
current
|
|
);
|
|
continue;
|
|
}
|
|
|
|
|
|
//
|
|
// Only look at configured bridges - buses we disabled have
|
|
// bus numbers 0->0-0 which is helpfully invalid
|
|
//
|
|
|
|
if (PciAreBusNumbersConfigured(current)) {
|
|
|
|
//
|
|
// Get the base and limit for each bridge and calculate which bridge
|
|
// has the biggest gap.
|
|
//
|
|
|
|
base = (UCHAR) current->Dependent.type1.SubordinateBus;
|
|
limit = PciFindBridgeNumberLimit(Parent, base);
|
|
|
|
//
|
|
// This ASSERT might fail if a BIOS or HAL misreported the limits
|
|
// of a root bridge. For example, an ACPI BIOS might have a _CRS
|
|
// for the root bridge that specifies bus-numbers 0 to 0 (length 1)
|
|
// are passed down, even though the real range is 0 to 255.
|
|
//
|
|
|
|
PCI_ASSERT(limit >= base);
|
|
|
|
gap = limit - base;
|
|
|
|
if (gap > biggestGap) {
|
|
|
|
PCI_ASSERT(gap > 0);
|
|
|
|
biggestGap = gap;
|
|
bestBase = base + 1;
|
|
}
|
|
|
|
if (current->Dependent.type1.SecondaryBus < lowest) {
|
|
lowest = current->Dependent.type1.SecondaryBus;
|
|
}
|
|
}
|
|
}
|
|
|
|
//
|
|
// Now make sure the gap between the bus we are on and the first bridge
|
|
// is not the biggest - lowest must always be greater that the parents bus
|
|
// number or it is miss configured and would have failed the
|
|
// BusNumbersConfigured test above.
|
|
//
|
|
|
|
PCI_ASSERT(lowest > Parent->BaseBus);
|
|
|
|
gap = lowest - (Parent->BaseBus + 1);
|
|
|
|
if (gap > biggestGap) {
|
|
|
|
PCI_ASSERT(gap > 0);
|
|
|
|
biggestGap = gap;
|
|
bestBase = Parent->BaseBus + 1;
|
|
}
|
|
|
|
//
|
|
// Did we find anywhere to put the bridge?
|
|
//
|
|
|
|
if (biggestGap >= 1) {
|
|
|
|
//
|
|
// Ok - we have some space to play with so we can configure out bridge
|
|
// right in the middle of the gap, if the bestGap is 1 (ie the bridge
|
|
// just fits) then this still works.
|
|
//
|
|
|
|
base = bestBase + (biggestGap / 2);
|
|
|
|
//
|
|
// Set subordinate equal to secondary as we are just leaving room for
|
|
// any bridges.
|
|
//
|
|
|
|
PciSetBusNumbers(Bridge, Parent->BaseBus, base, base);
|
|
|
|
//
|
|
// Update the ancestor subordinates if we configured the bridge
|
|
//
|
|
|
|
PciUpdateAncestorSubordinateBuses(Parent,
|
|
Bridge->Dependent.type1.SecondaryBus
|
|
);
|
|
|
|
}
|
|
}
|
|
|
|
VOID
|
|
PciSetBusNumbers(
|
|
IN PPCI_PDO_EXTENSION PdoExtension,
|
|
IN UCHAR Primary,
|
|
IN UCHAR Secondary,
|
|
IN UCHAR Subordinate
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine sets the bus numbers for a bridge and tracks if we have changed
|
|
bus numbers.
|
|
|
|
Arguments:
|
|
|
|
PdoExtension - The PDO for the bridge
|
|
|
|
Primary - The primary bus number to assign
|
|
|
|
Secondary - The secondary bus number to assign
|
|
|
|
Subordinate - The subordinate bus number to assign
|
|
|
|
|
|
Return Value:
|
|
|
|
None
|
|
|
|
--*/
|
|
|
|
{
|
|
PCI_COMMON_HEADER commonHeader;
|
|
PPCI_COMMON_CONFIG commonConfig = (PPCI_COMMON_CONFIG)&commonHeader;
|
|
|
|
PAGED_CODE();
|
|
|
|
PCI_ASSERT(Primary < Secondary || (Primary == 0 && Secondary == 0));
|
|
PCI_ASSERT(Secondary <= Subordinate);
|
|
|
|
//
|
|
// Fill in in the config. Note that the Primary/Secondary/Subordinate bus
|
|
// numbers are in the same place for type1 and type2 headers.
|
|
//
|
|
|
|
commonConfig->u.type1.PrimaryBus = Primary;
|
|
commonConfig->u.type1.SecondaryBus = Secondary;
|
|
commonConfig->u.type1.SubordinateBus = Subordinate;
|
|
|
|
//
|
|
// Grab the PCI Bus lock - this will let hwverifier reliably check the
|
|
// config space against our extension.
|
|
//
|
|
|
|
ExAcquireFastMutex(&PciBusLock);
|
|
|
|
//
|
|
// Remember in the PDO
|
|
//
|
|
|
|
PdoExtension->Dependent.type1.PrimaryBus = Primary;
|
|
PdoExtension->Dependent.type1.SecondaryBus = Secondary;
|
|
PdoExtension->Dependent.type1.SubordinateBus = Subordinate;
|
|
PdoExtension->Dependent.type1.WeChangedBusNumbers = TRUE;
|
|
|
|
PciWriteDeviceConfig(
|
|
PdoExtension,
|
|
&commonConfig->u.type1.PrimaryBus,
|
|
FIELD_OFFSET(PCI_COMMON_CONFIG, u.type1.PrimaryBus),
|
|
sizeof(Primary) + sizeof(Secondary) + sizeof(Subordinate)
|
|
);
|
|
|
|
ExReleaseFastMutex(&PciBusLock);
|
|
}
|
|
|
|
|
|
VOID
|
|
PciUpdateAncestorSubordinateBuses(
|
|
IN PPCI_FDO_EXTENSION FdoExtension,
|
|
IN UCHAR Subordinate
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine walks the bridge hierarchy updating the subordinate bus numbers
|
|
of each ancestor to ensure that numbers up to Subordinate are passed.
|
|
|
|
Arguments:
|
|
|
|
FdoExtension - The Fdo for the parent of the bridge(s) we have just configured
|
|
|
|
Subordinate - The maximum (subordinate) bus number to pass
|
|
|
|
|
|
Return Value:
|
|
|
|
None
|
|
|
|
--*/
|
|
|
|
{
|
|
PPCI_FDO_EXTENSION current;
|
|
PPCI_PDO_EXTENSION currentPdo;
|
|
|
|
PAGED_CODE();
|
|
|
|
//
|
|
// For all ancestors except the root update the subordinate bus number
|
|
//
|
|
|
|
for (current = FdoExtension;
|
|
current->ParentFdoExtension; // Root has no parent
|
|
current = current->ParentFdoExtension) {
|
|
|
|
currentPdo = (PPCI_PDO_EXTENSION)current->PhysicalDeviceObject->DeviceExtension;
|
|
|
|
PCI_ASSERT(!currentPdo->NotPresent);
|
|
|
|
if (currentPdo->Dependent.type1.SubordinateBus < Subordinate) {
|
|
|
|
currentPdo->Dependent.type1.SubordinateBus = Subordinate;
|
|
|
|
PciWriteDeviceConfig(currentPdo,
|
|
&Subordinate,
|
|
FIELD_OFFSET(PCI_COMMON_CONFIG,
|
|
u.type1.SubordinateBus),
|
|
sizeof(Subordinate)
|
|
);
|
|
|
|
}
|
|
}
|
|
|
|
//
|
|
// Ok so now we're at the root - can't be too careful on a checked build
|
|
// so lets make sure the subordinate value we came up with actually gets
|
|
// down this root...
|
|
//
|
|
|
|
PCI_ASSERT(PCI_IS_ROOT_FDO(current));
|
|
PCI_ASSERT(Subordinate <= current->MaxSubordinateBus);
|
|
|
|
}
|
|
|
|
VOID
|
|
PciDisableBridge(
|
|
IN PPCI_PDO_EXTENSION Bridge
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine disables a bridge by turing of its decodes and zeroing its
|
|
bus numbers.
|
|
|
|
Arguments:
|
|
|
|
PdoExtension - The PDO for the bridge
|
|
|
|
Return Value:
|
|
|
|
node
|
|
--*/
|
|
|
|
|
|
{
|
|
PAGED_CODE();
|
|
|
|
PCI_ASSERT(Bridge->DeviceState == PciNotStarted);
|
|
|
|
//
|
|
// Zero all the bus numbers so we shouldn't pass any config cycles
|
|
//
|
|
|
|
PciSetBusNumbers(Bridge, 0, 0, 0);
|
|
|
|
// NTRAID #62594 - 04/03/2000 - andrewth
|
|
// Close the windows in case this is the VGA bridge which we must
|
|
// leave decoding...
|
|
|
|
//
|
|
// Turn off the decodes so we don't pass IO or Memory cycles and bus
|
|
// master so we don't generate any
|
|
//
|
|
|
|
PciDecodeEnable(Bridge, FALSE, NULL);
|
|
|
|
}
|